CN108538909A - 具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管及其制作方法 - Google Patents
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Abstract
本发明提出了一种具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管(VDMOS)及其制作方法，该异质结VDMOS器件是在N+型碳化硅半导体衬底材料上表面形成掺杂浓度较小的N型碳化硅外延层作为VDMOS的漂移区，然后在N型碳化硅漂移区中再形成多层P型碳化硅电荷补偿块；在此基础之上异质外延生长N型硅外延层，采用成熟硅工艺在硅外延层形成VDMOS器件的有源区。该结构利用多层P型碳化硅电荷补偿块产生的新电场峰对VDMOS器件的纵向电场进行调制，结合了硅半导体材料的成熟工艺和碳化硅半导体材料宽带隙和高临界击穿电场的特点，形成具有低比导通电阻和高击穿电压的碳化硅/硅新型VDMOS。
Description
技术领域
本发明涉及功率半导体器件领域，尤其涉及一种异质结垂直双扩散金属氧化物半导体场效应管及其制作方法。
背景技术
功率半导体器件也被称为电子功率器件，主要用于电力设备的电能变换和控制电路方面的大功率电子器件。垂直双扩散金属氧化物半导体场效应晶体管(VDMOS，VerticalDouble-diffusion Metal Oxide Semiconductor)作为功率半导体器件领域的重要元器件，因其具有开关速度快、损耗小、输入阻抗高、驱动功率小、频率特性好、跨导高线性度高等特性等优良特性，已经被广泛应用于功率集成电路与功率集成系统中。
然而VDMOS功率器件最主要的问题就是器件的比导通电阻随着击穿电压的增加而急剧增大，这在很大程度上限制了VDMOS功率器件的发展与应用。
发明内容
本发明提出一种具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，旨在进一步优化VDMOS的击穿电压和比导通电阻，改善器件性能。
本发明的技术方案如下：
该具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，包括：
半导体材料的N+型衬底，兼作漏区；
在所述N+型衬底上表面形成的相同半导体材料的N型外延层，记为第一N型外延层；
在所述第一N型外延层上表面异质外延生长或利用键合技术形成的元素半导体材料的N型外延层(利用键合技术形成的通常称之为键合层，本文统一表述为外延层)，记为第二N型外延层；
基于所述第二N型外延层在其两侧区域形成的两处P型基区；所述P型基区的纵向边界延伸到第一N型外延层内，即P型基区与第一N型外延层形成的PN结位于第一N型外延层内，沟道仍主要位于第二N型外延层中；
在每一处P型基区中形成的沟道以及N+型源区和P+沟道衬底接触；其中N+型源区与沟道邻接，P+沟道衬底接触相对于N+型源区位于沟道远端；
栅氧化层，位于所述第二N型外延层上表面，覆盖两处P型基区之间的部分以及相应的两处沟道；
栅极，位于栅氧化层上表面；
源极，覆盖于P+沟道衬底接触与N+型源区相接区域的上表面；两处源极共接；
漏极，位于所述N+型衬底下表面；
有别于现有技术的是：
所述N+型衬底和第一N型外延层均为宽带隙半导体材料；
在所述第一N型外延层中，对应于两处P型基区，分别沿纵向间隔分布有多层宽带隙半导体材料的P型电荷补偿块；
P型电荷补偿块的横向宽度从P型基区到N+型衬底呈现依次减小的趋势，其最大横向宽度不超过P型基区的横向宽度；P型电荷补偿块的掺杂浓度从P型基区到N+型衬底则呈现依次增大的趋势；
第一N型外延层的掺杂浓度比N+型衬底的掺杂浓度低4-6个数量级，P型电荷补偿块的掺杂浓度比N+型衬底的掺杂浓度低3-5个数量级。
在以上方案的基础上，本发明还进一步作了如下优化：
所述宽带隙半导体材料为氮化镓、碳化硅或金刚石；所述元素半导体材料为硅或锗。
所述P型基区、N+型源区、P+沟道衬底接触以及沟道，是基于第二N型外延层采用离子注入以及双扩散技术形成的。
P型基区以及多层P型电荷补偿块整体呈左右对称结构。
多层P型电荷补偿块横向宽度依次递减10％～40％。
多层P型电荷补偿块中最大的横向宽度为P型基区横向宽度的70％～90％；最小的横向宽度为P型基区横向宽度的10％～40％。
最接近P型基区的P型电荷补偿块与P型基区之间的纵向距离为N型外延层纵向厚度的5％～20％；最接近N+型衬底的P型电荷补偿块与N+型衬底之间纵向距离为N型外延层纵向厚度的5％～20％。
相邻两层P型电荷补偿块之间的纵向距离相等，且为N型外延层纵向厚度的5％～20％；所述多层P型电荷补偿块纵向厚度之和为N型外延层纵向厚度的40％～80％。
所述的栅极为多晶硅栅极，所述的源极和漏极为金属化电极。
一种制作上述具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管的方法，包括以下步骤：
在宽带隙半导体材料的N+型衬底的上表面形成宽带隙半导体材料的N型外延层和P型电荷补偿块；其中宽带隙半导体材料的N型外延层记为第一N型外延层；
在N+型衬底下表面形成金属化漏极；
在宽带隙半导体材料的N型外延层上表面异质外延生长或利用键合技术形成元素半导体材料的N型外延层，记为第二N型外延层；
基于第二N型外延层采用离子注入分别形成两处P型基区及N+型源区和P+沟道衬底接触，并采用双扩散技术形成相应的沟道，确保P型基区的纵向边界延伸到第一N型外延层内，即P型基区与第一N型外延层形成的PN结位于第一N型外延层内，沟道仍主要位于第二N型外延层中；
在整个第二N型外延层上表面形成栅氧化层，并淀积多晶硅，然后刻蚀多晶硅以及栅氧化层(去除位于源极上表面的部分)，形成多晶硅栅极；
在器件表面淀积钝化层，并在对应于源极的位置刻蚀接触孔；
在接触孔内淀积金属并刻蚀(去除周边其余的钝化层)形成源极，并将两处源极共接。
本发明技术方案的有益效果如下：
本发明充分利用宽带隙半导体材料(优选碳化硅)与元素半导体材料(优选硅)各自的优势。首先在N+型碳化硅半导体衬底材料上表面形成掺杂浓度较小的N型碳化硅外延层作为VDMOS的漂移区，然后在N型碳化硅漂移区的左、右两端再形成多层P型碳化硅电荷补偿块；在此基础之上异质外延生长(或利用键合技术形成)N型硅外延层，采用成熟硅工艺在硅外延层形成VDMOS器件的有源区。该结构利用多层P型碳化硅电荷补偿块产生的新电场峰对VDMOS器件的纵向电场进行调制，优化器件击穿电压与比导通电阻矛盾的同时，结合了硅半导体材料的成熟工艺和碳化硅半导体材料宽带隙和高临界击穿电场的特点，形成具有低比导通电阻和高击穿电压的碳化硅/硅新型VDMOS。
碳化硅等材料的高热导率特性还有利于新型VDMOS器件的散热，器件的性能进一步得到了有效改善。
由于器件的有源区是在硅半导体材料中形成的，因此在器件制造过程中可采用成熟的硅工艺来实现更好的欧姆接触。
附图说明
图1是本发明的结构示意图。
其中，1-源极；2-栅氧化层；3-栅极；4-源极；5-P+沟道衬底接触(P+型体区)；6-N+型源区；7-P型基区；801-N型碳化硅外延层(第一N型外延层)；802-P型碳化硅电荷补偿块；803-N+型衬底；9-漏极。
具体实施方式
下面结合附图以N沟道VDMOS为例介绍本发明。
如图1所示，本实施例的结构包括：
碳化硅材料的N+型衬底803；
在N+型衬底803上表面形成的碳化硅半导体材料的N型外延层，记为N型碳化硅外延层801；
多层P型碳化硅电荷补偿块802；多层P型电荷补偿块802层数可随N型碳化硅外延层801纵向厚度的增大依次增加；P型电荷补偿块802的横向宽度从P型基区7到N+型衬底803呈现依次减小的趋势，其最大横向宽度不超过P型基区7的横向宽度；P型电荷补偿块802的掺杂浓度从P型基区7到N+型衬底803则呈现依次增大的趋势；多层P型电荷补偿块802横向宽度依次递减10％～40％；多层P型电荷补偿块802中最大的横向宽度为P型基区7横向宽度的70％～90％；最小的横向宽度为P型基区7横向宽度的10％～40％；横向宽度最大(即最靠近P型基区)的P型电荷补偿块802与P型基区7之间的纵向距离为N型碳化硅外延层纵向厚度的5％～20％；横向宽度最小(即最接近N+型衬底)的P型电荷补偿块802与N+型衬底803之间纵向距离为N型碳化硅外延层801纵向厚度的5％～20％；相邻两层P型电荷补偿块802之间的纵向距离相等，且为N型碳化硅外延层801纵向厚度的5％～20％；所述多层P型电荷补偿块802纵向厚度之和为N型碳化硅外延层801纵向厚度的40％～80％；
在N型碳化硅外延层801上表面异质外延生长或利用键合技术形成的N型硅外延层；若记N型碳化硅外延层为第一N型外延层，则可记该N型硅外延层为第二N型外延层；
基于N型硅外延层(第二N型外延层)形成的两处P型基区7；P型基区7的纵向边界延伸到N型碳化硅外延层801内，即P型基区与N型碳化硅外延层801形成的PN结位于N型碳化硅外延层801内，沟道仍主要位于N型硅外延层中；
在每一处P型基区7中形成的沟道以及N+型源区6和P+沟道衬底接触5，其中N+型源区6与沟道邻接，P+沟道衬底接触5相对于N+型源区6位于沟道远端；
栅氧化层2，位于N型硅外延层上表面，覆盖两处P型基区7之间的部分以及相应的两处沟道；
栅极3，位于栅氧化层2上表面；
源极1、4，覆盖P+沟道衬底接触5与N+型源区6相接区域的上表面；两处源极1、4共接；
漏极9，位于N+型衬底803下表面。
该器件具体可以通过以下步骤进行制备：
在碳化硅半导体材料的N+型衬底的上表面形成N型碳化硅外延层；在形成N型碳化硅外延层的同时，形成多层P型碳化硅电荷补偿块；N型碳化硅外延层的掺杂浓度比N+型衬底的掺杂浓度低4-6个数量级，P型碳化硅电荷补偿块的掺杂浓度比N+型衬底的掺杂浓度低3-5个数量级；
在N+型衬底下表面形成金属化漏极；
通过异质外延生长N型硅外延层；
在N型硅外延层上采用离子注入分别形成两处P型基区及N+型源区和P+沟道衬底接触，并采用双扩散技术形成相应的沟道；确保P型基区的纵向边界延伸到N型碳化硅外延层内，即P型基区与N型碳化硅外延层形成的PN结位于N型碳化硅外延层内，且沟道仍主要位于N型硅外延层中；
在整个N型硅外延层(或键合层)上表面形成栅氧化层，并淀积多晶硅，然后刻蚀多晶硅以及栅氧化层(去除位于源极上表面的部分)，形成多晶硅栅极；
在器件表面淀积钝化层，并在对应于源极的位置刻蚀接触孔；
在接触孔内淀积金属并刻蚀(去除周边其余的钝化层)形成源极，并将两处源极共接。
经ISE TCAD仿真表明，该器件较之传统碳化硅/硅异质结垂直双扩散金属氧化物半导体场效应管，器件性能得到有效改善，在两种器件漂移区长度和浓度相同的情况下，该器件的击穿电压提高了40％以上。
本发明中的VDMOS当然也可以为P型沟道，其结构与N沟道VDMOS等同，也应当视为属于本申请权利要求的保护范围，在此不再赘述。
本实施例中的VDMOS采用的碳化硅半导体材料，当然也可以为氮化镓、金刚石等其他宽带隙半导体材料，硅半导体材料，当然也可以为锗等其他元素半导体材料；其结构与碳化硅/硅半导体材料异质结VDMOS等同，也应当视为属于本申请权利要求的保护范围，在此不再赘述。
Claims (10)
1.具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，包括：
半导体材料的N+型衬底(803)，兼作漏区；
在所述N+型衬底(803)上表面形成的相同半导体材料的N型外延层，记为第一N型外延层(801)；
在所述第一N型外延层(801)上表面异质外延生长或利用键合技术形成的元素半导体材料的N型外延层，记为第二N型外延层；
基于所述第二N型外延层在其两侧区域形成的两处P型基区(7)；所述P型基区(7)的纵向边界延伸到第一N型外延层(801)内，即P型基区(7)与第一N型外延层(801)形成的PN结位于第一N型外延层(801)内，沟道仍主要位于第二N型外延层中；
在每一处P型基区(7)中形成的沟道以及N+型源区(6)和P+沟道衬底接触(5)；其中N+型源区(6)与沟道邻接，P+沟道衬底接触(5)相对于N+型源区(6)位于沟道远端；
栅氧化层(2)，位于所述第二N型外延层上表面，覆盖两处P型基区(7)之间的部分以及相应的两处沟道；
栅极(3)，位于栅氧化层(2)上表面；
源极(1、4)，覆盖于P+沟道衬底接触(5)与N+型源区(6)相接区域的上表面；两处源极(1、4)共接；
漏极(9)，位于所述N+型衬底(803)下表面；
其特征在于：
所述N+型衬底(803)和第一N型外延层(801)均为宽带隙半导体材料；
在所述第一N型外延层(801)中，对应于两处P型基区(7)，分别沿纵向间隔分布有多层宽带隙半导体材料的P型电荷补偿块(802)；
P型电荷补偿块(802)的横向宽度从P型基区(7)到N+型衬底(803)呈现依次减小的趋势，其最大横向宽度不超过P型基区(7)的横向宽度；P型电荷补偿块(802)的掺杂浓度从P型基区(7)到N+型衬底(803)则呈现依次增大的趋势；
第一N型外延层(801)的掺杂浓度比N+型衬底(803)的掺杂浓度低4-6个数量级，P型电荷补偿块(802)的掺杂浓度比N+型衬底(803)的掺杂浓度低3-5个数量级。
2.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：所述宽带隙半导体材料为氮化镓、碳化硅或金刚石；所述元素半导体材料为硅或锗。
3.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：所述P型基区(7)、N+型源区(6)、P+沟道衬底接触(5)以及沟道，是基于第二N型外延层采用离子注入以及双扩散技术形成的。
4.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：P型基区(7)以及多层P型电荷补偿块(802)整体呈左右对称结构。
5.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：多层P型电荷补偿块(802)横向宽度依次递减10％～40％。
6.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：多层P型电荷补偿块(802)中最大的横向宽度为P型基区(7)横向宽度的70％～90％；最小的横向宽度为P型基区(7)横向宽度的10％～40％。
7.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：最接近P型基区的P型电荷补偿块(802)与P型基区(7)之间的纵向距离为第一N型外延层(801)纵向厚度的5％～20％；最接近N+型衬底的P型电荷补偿块(802)与N+型衬底(803)之间纵向距离为第一N型外延层(801)纵向厚度的5％～20％。
8.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：相邻两层P型电荷补偿块(802)之间的纵向距离相等，且为第一N型外延层(801)纵向厚度的5％～20％；所述多层P型电荷补偿块(802)纵向厚度之和为第一N型外延层(801)纵向厚度的40％～80％。
9.根据权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管，其特征在于：所述的栅极(3)为多晶硅栅极，所述的源极(1、4)和漏极(9)为金属化电极。
10.一种制作权利要求1所述的具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管的方法，包括以下步骤：
在宽带隙半导体材料的N+型衬底的上表面形成宽带隙半导体材料的N型外延层和P型电荷补偿块；其中宽带隙半导体材料的N型外延层记为第一N型外延层；
在N+型衬底下表面形成金属化漏极；
在宽带隙半导体材料的N型外延层上表面异质外延生长或利用键合技术形成元素半导体材料的N型外延层，记为第二N型外延层；
基于第二N型外延层采用离子注入分别形成两处P型基区及N+型源区和P+沟道衬底接触，并采用双扩散技术形成相应的沟道，确保P型基区的纵向边界延伸到第一N型外延层内，即P型基区与第一N型外延层形成的PN结位于第一N型外延层内，沟道仍主要位于第二N型外延层中；
在整个第二N型外延层上表面形成栅氧化层，并淀积多晶硅，然后刻蚀多晶硅以及栅氧化层，形成多晶硅栅极；
在器件表面淀积钝化层，并在对应于源极的位置刻蚀接触孔；
在接触孔内淀积金属并刻蚀形成源极，并将两处源极共接。
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Application publication date: 20180914 |