CN114999922B - 一种具有耐压结构的碳化硅mosfet的制造方法 - Google Patents

一种具有耐压结构的碳化硅mosfet的制造方法 Download PDF

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CN114999922B
CN114999922B CN202210941206.9A CN202210941206A CN114999922B CN 114999922 B CN114999922 B CN 114999922B CN 202210941206 A CN202210941206 A CN 202210941206A CN 114999922 B CN114999922 B CN 114999922B
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张长沙
周海
李佳帅
单体玮
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Global Power Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66053Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors

Abstract

本发明提供了一种具有耐压结构的碳化硅MOSFET的制造方法,包括:在具有漂移层的碳化硅衬底上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成至少两个P型的耐压夹断区、至少一个N型的耐压区以及N+低阻导电区;重新形成阻挡层,并对阻挡层蚀刻形成通孔进行离子注入,形成N+源区;重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔氧化形成栅极绝缘层;重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积金属形成源极金属层;重新形成阻挡层,并对阻挡层蚀刻栅极金属淀积区,淀积形成栅极金属层;清除所有阻挡层,在碳化硅衬底上淀积形成漏极金属层,使得其耐压特性显著提高,满足特高压输电的需求。

Description

一种具有耐压结构的碳化硅MOSFET的制造方法
技术领域
本发明涉及一种具有耐压结构的碳化硅MOSFET的制造方法。
背景技术
SiC器件碳化硅(SiC)材料因其优越的物理特性,广泛受到人们的关注和研究。其高温大功率电子器件具备输入阻抗高、开关速度快、工作频率高、耐高温高压等优点,在开关稳压电源、高频加热、汽车电子以及功率放大器等方面取得了广泛应用。
特高压输电由于其电流很小,其对于器件的电流特性要求很低,对耐压特性要求很高。在国家电网的特高压输电等领域对于器件的耐压特性有非常高的要求,同时其电流很小,对器件的电流能力要求很小,这就出现了对于高耐压小电流特性器件的需求。
发明内容
本发明要解决的技术问题,在于提供一种具有耐压结构的碳化硅MOSFET的制造方法,使得其耐压特性显著提高,满足特高压输电的需求。
本发明是这样实现的:一种具有耐压结构的碳化硅MOSFET的制造方法,包括:
步骤1、在具有漂移层的碳化硅衬底上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成至少两个P型的耐压夹断区;
步骤2、在漂移层上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成至少一个N型的耐压区;
步骤3、在漂移层上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成N+低阻导电区;
步骤4、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔进行离子注入,以形成N+源区;
步骤5、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔氧化形成栅极绝缘层;
步骤6、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积金属形成源极金属层;
步骤7、重新形成阻挡层,并对阻挡层蚀刻栅极金属淀积区,淀积形成栅极金属层;
步骤8、清除所有阻挡层,在碳化硅衬底上淀积形成漏极金属层。
进一步地,所述漂移层为N-型。
本发明的优点在于:
在器件纵向结构中有低阻的导电通道,该通道将漏极的电位引到N+低阻导电区;器件的N+低阻导电区和第一P型耐压夹断层形成第一个横向PN结,将纵向器件的纵向耐压结构转变为横向;第一N型耐压区和第二P型耐压夹断层和形成第二个横向PN结,提高器件的横向耐压特性;以此进行叠加多个横向PN结,提高器件的横向耐压特性;
由于半导体工艺的限制,器件制备过程中难以制造厚的外延层,故纵向MOSFET的耐压一般限制在2KV左右,而本发明将纵向耐压结构转化为横向的超结结构,可以将器件的耐压提高到5KV以上,只要横向继续延展,器件耐压可以一直提升。与此同时,器件器件有低阻的纵向导电沟道,可以实现低阻导通,其导通电阻不会增加。
附图说明
下面参照附图结合实施例对本发明作进一步的说明。
图1是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图一。
图2是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图二。
图3是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图三。
图4是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图四。
图5是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图五。
图6是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图六。
图7是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图七。
图8是本发明一种具有耐压结构的碳化硅MOSFET的制造方法流程图八。
图9是本发明一种具有耐压结构的碳化硅MOSFET的原理示意图。
具体实施方式
如图1至9所示,本发明一种具有耐压结构的碳化硅MOSFET的制造方法,(MOSFET为Metal-Oxide-Semiconductor Field-Effect-Transistor,金属-氧化物-半导体场效应晶体管)包括:
步骤1、在具有漂移层的碳化硅衬底上形成阻挡层a,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成至少两个P型的耐压夹断区,形成第一P型耐压夹断区105和第二P型耐压夹断区1061,所述漂移层102为N-型;
步骤2、在漂移层上形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成至少一个N型的耐压区1062;
步骤3、在漂移层上形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成N+低阻导电区104;漂移层最终被N+低阻导电区104分割为第一N-型漂移层102和第二N-型漂移层103;
步骤4、重新形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔进行离子注入,以形成N+源区107;
步骤5、重新形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔氧化形成栅极绝缘层109;
步骤6、重新形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔淀积金属形成源极金属层108;
步骤7、重新形成阻挡层a,并对阻挡层a蚀刻栅极金属淀积区,淀积形成栅极金属层110;
步骤8、清除所有阻挡层a,在碳化硅衬底101上淀积形成漏极金属层111。
如图9所示,通过上述方法得到了耐压碳化硅MOSFET,包括:
碳化硅衬底101,
第一N-型漂移层102,所述第一N-型漂移层102设于所述碳化硅衬底101的上侧面;
第二N-型漂移层103,所述第二N-型漂移层103设于所述碳化硅衬底101的上侧面,所述第二N-型漂移层103的宽度不小于500纳米;
N+低阻导电区104,所述N+低阻导电区104底部连接至所述碳化硅衬底101的上侧面,且所述N+低阻导电区104设于所述第一N-型漂移层102以及第二N-型漂移层103之间;
第一P型耐压夹断区105,所述第一P型耐压夹断区105设于所述第一N-型漂移层102上,且所述第一P型耐压夹断区105侧面连接至所述N+低阻导电区104侧面;
至少一个横向PN模块106,所述横向PN模块106设于所述第一N-型漂移层102上,且所述横向PN模块106侧面连接至所述第一P型耐压夹断区105侧面,所述横向PN模块106的侧面连接至另一个横向PN模块106的侧面;
N+源区107,所述N+源区107设于所述第一横向PN模块106上;
源极金属层108,所述源极金属层108分别连接所述N+源区107,也可以与横向PN模块106连接;
栅极绝缘层109,所述栅极绝缘层109连接至所述第二N-型漂移层103、N+低阻导电区104、第一P型耐压夹断区105以及横向PN模块106;
栅极金属层110,所述栅极金属层110连接至所述栅极绝缘层109;
以及,漏极金属层111,所述漏极金属层111连接至碳化硅衬底101的下侧面。
所述横向PN模块106包括第二P型耐压夹断区1061以及第一N型耐压区1062,所述第一N型耐压区1062以及第二P型耐压夹断区1061均设于所述第一N-型漂移层102上方,且所述第一N型耐压区1062左侧面连接至所述第一P型耐压夹断区105,所述第二P型耐压夹断区1061右侧面连接至所述第一N型耐压区1062的左侧面;所述第二P型耐压夹断区1061的右侧面连接另一个横向PN模块的左侧面;所述N+源区107设于最左侧的第二P型耐压夹断区。
在器件纵向结构中有低阻的导电通道,该通道将漏极金属层111的电位引到N+低阻导电区;器件的N+低阻导电区和第一P型耐压夹断层形成第一个横向PN结,将纵向器件的纵向耐压结构转变为横向;第一N型耐压区和第二P型耐压夹断层和形成第二个横向PN结,提高器件的横向耐压特性;以此进行叠加多个横向PN结,提高器件的横向耐压特性;
当存在一个横向PN模块106时,第一P型耐压夹断层105、第一N型耐压区1062均位于栅极金属层下方,源极金属层108和N+低阻导电区104之间,形成栅控特性;栅极金属层110控制的沟道中主要包括对第一P型耐压夹断层105进行反型形成N型沟道,第一N型耐压区1061不需要反型,降低了栅电荷,对于器件的开关速度有正向优化特性。
当存在两个横向PN模块106时,第一P型耐压夹断层105、一个第二P型耐压夹断层1061、两个第一N型耐压区1062均位于栅极金属层下方,源极金属层108和N+低阻导电区104之间,形成栅控特性;栅极金属层110控制的沟道中主要包括对第一P型耐压夹断层105和第二P型耐压夹断层1061(即位于栅极金属层110下方的第二P型耐压夹断层1061)进行反型形成N型沟道,两个第一N型耐压区1062不需要反型,降低了栅电荷,对于器件的开关速度有正向优化特性。
虽然以上描述了本发明的具体实施方式,但是熟悉本技术领域的技术人员应当理解,我们所描述的具体的实施例只是说明性的,而不是用于对本发明的范围的限定,熟悉本领域的技术人员在依照本发明的精神所作的等效的修饰以及变化,都应当涵盖在本发明的权利要求所保护的范围内。

Claims (2)

1.一种具有耐压结构的碳化硅MOSFET的制造方法,其特征在于,包括:
步骤1、在具有漂移层的碳化硅衬底上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成至少两个P型的耐压夹断区;
步骤2、在漂移层上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成至少一个N型的耐压区;
步骤3、在漂移层上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,以形成N+低阻导电区,所述N+低阻导电区底部连接至所述碳化硅衬底的上侧面;
步骤4、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔进行离子注入,以形成N+源区;
步骤5、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔氧化形成栅极绝缘层;
步骤6、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积金属形成源极金属层;
步骤7、重新形成阻挡层,并对阻挡层蚀刻栅极金属淀积区,淀积形成栅极金属层;
步骤8、清除所有阻挡层,在碳化硅衬底上淀积形成漏极金属层。
2.如权利要求1所述的一种具有耐压结构的碳化硅MOSFET的制造方法,其特征在于,所述漂移层为N-型。
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