JP6809071B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6809071B2 JP6809071B2 JP2016180032A JP2016180032A JP6809071B2 JP 6809071 B2 JP6809071 B2 JP 6809071B2 JP 2016180032 A JP2016180032 A JP 2016180032A JP 2016180032 A JP2016180032 A JP 2016180032A JP 6809071 B2 JP6809071 B2 JP 6809071B2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Description
実施の形態1にかかる半導体装置の構造について、プレーナゲート構造の超接合MOSFET(以下、SJ−MOSFETとする)を例に説明する。図1は、実施の形態1にかかる半導体装置の要部を示す説明図である。図1(a)には、SJ−MOSFETの断面構造を示す。図1(b)には、半導体基体(半導体チップ)10の要部の深さ方向(縦方向)の不純物濃度プロファイルを示す。図1(b)において、実線はp型不純物濃度プロファイルであり、破線はn型不純物濃度プロファイルである(図9〜11,12(a)、13〜15においても同様)。図1(c)には、図1(b)の不純物濃度プロファイルに対応する電界強度分布を示す。
次に、実施の形態2にかかる半導体装置について説明する。図9は、実施の形態2にかかる半導体装置の要部の深さ方向の不純物濃度プロファイルを示す特性図である。実施の形態2にかかる半導体装置の断面構造は、実施の形態1(図1(a)参照)と同様である。図9には、図1(a)の半導体基体10の要部の深さ方向の不純物濃度プロファイルを示す。実施の形態2にかかる半導体装置は、n型ドリフト領域3のドレイン側の部分3Hおよびp型仕切り領域4のドレイン側の部分4Hの不純物濃度プロファイルが実施の形態1にかかる半導体装置と異なる。
次に、実施の形態3にかかる半導体装置について説明する。図12は、実施の形態3にかかる半導体装置の要部を示す説明図である。実施の形態3にかかる半導体装置の断面構造は、実施の形態1(図1(a)参照)と同様である。図12(a)には、図1(a)の半導体基体10の要部の深さ方向の不純物濃度プロファイルを示す。図12(b)には、図12(a)の不純物濃度プロファイルに対する電界強度分布L11を示す。実施の形態3にかかる半導体装置は、p型仕切り領域4の最も不純物濃度Cp3の低い部分4Lの不純物濃度プロファイルが実施の形態1にかかる半導体装置と異なる。
次に、実施の形態4にかかる半導体装置について説明する。図13は、実施の形態4にかかる半導体装置の要部の深さ方向の不純物濃度プロファイルを示す特性図である。実施の形態4にかかる半導体装置の断面構造は、実施の形態1(図1(a)参照)と同様である。図13には、図1(a)の半導体基体10の要部の深さ方向の不純物濃度プロファイルを示す。実施の形態4かかる半導体装置は、実施の形態2に実施の形態3を適用したSJ−MOSFETである。
次に、オン抵抗と耐圧との関係について検証した。図16は、実施例にかかる半導体装置のオン抵抗を示す特性図である。図17は、実施例にかかる半導体装置の耐圧を示す特性図である。上述した実施の形態1にかかる半導体装置の不純物濃度プロファイルを有するSJ−MOSFET(以下、実施例とする)のオン抵抗および耐圧を測定した結果をそれぞれ図16,17に示す。
2a n-型バッファ層
2b 並列pn層
3 n型ドリフト領域
3A n型ドリフト領域のソース側の部分
3B 表面n型ドリフト領域
3H n型ドリフト領域のドレイン側の部分
4 p型仕切り領域
4A p型仕切り領域のソース側の部分
4H p型仕切り領域のドレイン側の部分
4L p型仕切り領域のソース側の部分の深さ方向の中央付近の部分
5 p型ベース領域
6 n+型ソース領域
7 ゲート絶縁膜
8 ゲート電極
9 層間絶縁膜
10 半導体基体
11 ソース電極
12 ドレイン電極
20 エピタキシャル基板
21 n-型半導体層
21a,21b n-型エピタキシャル層
22,24,26,28 レジストマスク
23,25,27,29 イオン注入
31,33 n型領域
32,34 p型領域
Cn1 n型ドリフト領域のドレイン側の部分の不純物濃度
Cn2 n型ドリフト領域のソース側の部分の不純物濃度
Cn3 n+型半導体基板の不純物濃度
Cn4 n-型バッファ層の不純物濃度
Cp1 p型仕切り領域のドレイン側の部分の不純物濃度
Cp2 p型仕切り領域のソース側の部分の不純物濃度
Cp3 p型仕切り領域のソース側の部分の深さ方向の中央付近の部分の不純物濃度
L1,L2,L11 電界強度分布
Claims (12)
- 第1導電型半導体層上に、前記第1導電型半導体層の表面に平行な方向に第1導電型半導体領域と第2導電型半導体領域とを交互に繰り返し配置した並列pn層と、
前記並列pn層の、前記第1導電型半導体層側に対して反対側に設けられた素子構造と、
前記素子構造を構成する半導体部に電気的に接続された第1電極と、
前記第1導電型半導体層に電気的に接続された第2電極と、
を備え、
前記第1導電型半導体領域の幅は深さ方向にわたって一定であり、
前記第2導電型半導体領域の幅は深さ方向にわたって一定であり、
前記第1導電型半導体領域は、前記第2電極側の部分の不純物濃度を前記第1電極側の部分の不純物濃度よりも高くした不純物濃度プロファイルを有し、
前記第2導電型半導体領域は、前記第2電極側の部分の不純物濃度を前記第1電極側の部分の不純物濃度よりも高くし、かつ前記第1電極側の部分の所定厚さの1箇所の不純物濃度を当該第1電極側の部分の他の部分よりも相対的に低くした不純物濃度プロファイルを有し、
前記第2導電型半導体領域の前記第2電極側の部分の不純物濃度は、前記第1導電型半導体領域の前記第2電極側の部分の不純物濃度よりも高く、
前記第1導電型半導体領域の前記第1電極側の部分の不純物濃度は深さ方向に一様であり、
前記第2導電型半導体領域の前記第1電極側の部分うち、相対的に不純物濃度の低い前記1箇所の低濃度部分を除く基本構成部分の不純物濃度は深さ方向に一様であり、
前記第2導電型半導体領域において前記低濃度部分の前記第1電極側および前記第2電極側にそれぞれ前記基本構成部分が隣接し、
前記第2導電型半導体領域の前記低濃度部分の中心の深さ位置は、前記並列pn層の厚さの半分よりも前記第2電極側に位置することを特徴とする半導体装置。 - 前記第2導電型半導体領域の前記第2電極側の部分と前記第1電極側の部分との境界は、前記第1導電型半導体領域の前記第2電極側の部分と前記第1電極側の部分との境界よりも前記第1電極側に位置することを特徴とする請求項1に記載の半導体装置。
- 前記第1導電型半導体領域と前記第2導電型半導体領域との総不純物量は同じであることを特徴とする請求項1または2に記載の半導体装置。
- 前記第2導電型半導体領域の前記第1電極側の部分の不純物濃度は、前記第1導電型半導体領域の前記第1電極側の部分の不純物濃度と同じであることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- 前記第1導電型半導体領域の前記第2電極側の部分の不純物濃度は、前記第2電極側へ向かうにしたがって所定の割合で高くなっていることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。
- 前記第2導電型半導体領域の前記第2電極側の部分の不純物濃度は、前記第2電極側へ向かうにしたがって所定の割合で高くなっていることを特徴とする請求項1〜5のいずれか一つに記載の半導体装置。
- 前記第2導電型半導体領域の前記低濃度部分の不純物濃度は、当該低濃度部分の深さ方向の中央付近で最も低くなっていることを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。
- 前記素子構造は、
前記第2導電型半導体領域の、前記第1導電型半導体層側に対して反対側の表面層に、前記第1導電型半導体領域に接して設けられ前記半導体部をなす第2導電型の第1半導体領域と、
前記第1半導体領域の内部に選択的に設けられ前記半導体部をなす第1導電型の第2半導体領域と、
前記第1半導体領域の、前記第1導電型半導体領域と前記第2半導体領域との間の領域に接して設けられたゲート絶縁膜と、
前記ゲート絶縁膜を挟んで前記第1半導体領域の反対側に設けられたゲート電極と、を有することを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。 - 前記第1導電型半導体層と前記並列pn層との間に、前記第1導電型半導体領域よりも不純物濃度の低い第1導電型低濃度半導体層をさらに備えることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。
- 第1導電型半導体層上に、前記第1導電型半導体層の表面に平行な方向に第1導電型半導体領域と第2導電型半導体領域とを交互に繰り返し配置した並列pn層を備え、
前記第1導電型半導体領域は、前記第1導電型半導体層側の部分の不純物濃度を前記第1導電型半導体層側に対して反対の側の部分の不純物濃度よりも高くした不純物濃度プロファイルを有し、
前記第2導電型半導体領域は、前記第1導電型半導体層側の部分の不純物濃度を前記第1導電型半導体層側に対して反対の側の部分の不純物濃度よりも高くし、かつ前記第1導電型半導体層側に対して反対の側の部分の一部の不純物濃度を当該第1導電型半導体層側に対して反対の側の部分の他の部分よりも相対的に低くした不純物濃度プロファイルを有し、
前記第2導電型半導体領域の前記第1導電型半導体層側の部分の不純物濃度は、前記第1導電型半導体領域の前記第1導電型半導体層側の部分の不純物濃度よりも高い半導体装置の製造方法であって、
前記第1導電型半導体層上に第1導電型のエピタキシャル成長層を堆積する第1工程と、前記エピタキシャル成長層の表面の、前記第1導電型半導体領域の形成領域に第1導電型不純物を第1イオン注入する第2工程と、前記エピタキシャル成長層の表面の、前記第2導電型半導体領域の形成領域に第2導電型不純物を第2イオン注入する第3工程と、を一組とする工程を繰り返し行うことを含み、
1回目の前記第2工程では、異なる加速電圧で前記第1イオン注入を複数回行い、
2回目以降の前記第2工程では、1回目の前記第2工程よりも少ない回数で前記第1イオン注入を行い、
1回目の前記第3工程では、前記第1イオン注入と同じドーズ量で、1回目の前記第2工程よりも多い回数分、それぞれ異なる加速電圧での前記第2イオン注入を行い、
2回目以降の前記第3工程では、前記第1イオン注入と同じドーズ量で、1回目の前記第3工程よりも少ない回数分の前記第2イオン注入を行い、
2回目以降の前記第3工程のうち、連続する前記一組の工程の前記第3工程では、他の前記第3工程よりも前記第2イオン注入のドーズ量を低くすることを特徴とする半導体装置の製造方法。 - 前記一組の工程の後、前記第1導電型半導体領域および前記第2導電型半導体領域の形成領域をイオン注入した前記エピタキシャル成長層上にさらに第1導電型のエピタキシャル成長層を堆積する第4工程と、
前記第4工程後、熱処理により、前記第1導電型不純物および前記第2導電型不純物を拡散させる熱処理工程と、
をさらに含み、
前記熱処理工程では、
前記第1導電型不純物を拡散させて、積層された複数の前記エピタキシャル成長層にわたって連続する前記第1導電型半導体領域を形成し、
前記第2導電型不純物を拡散させて、積層された複数の前記エピタキシャル成長層にわたって連続する前記第2導電型半導体領域を形成することを特徴とする請求項10に記載の半導体装置の製造方法。 - 最初の前記第1工程の前に、前記第1導電型半導体層上に、前記第1導電型半導体領域よりも不純物濃度の低い第1導電型低濃度半導体層を形成する工程をさらに含み、
最初の前記第1工程では、前記第1導電型低濃度半導体層上に、前記エピタキシャル成長層を堆積することを特徴とする請求項10または11に記載の半導体装置の製造方法。
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