CN115632031B - 集成栅保护机制的平面栅碳化硅mosfet的制造方法 - Google Patents
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Abstract
本发明提供了一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法,包括在碳化硅衬底的漂移层上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,形成基区;在漂移层上重新形成阻挡层,蚀刻、离子注入,形成源区;在漂移层上重新形成阻挡层,蚀刻、淀积金属,形成源极金属;重新形成阻挡层,蚀刻、淀积形成第二栅极保护区;重新形成阻挡层,蚀刻、氧化形成栅隔离层;重新形成阻挡层,蚀刻、淀积金属,形成栅极金属层;重新形成阻挡层,蚀刻、淀积形成第一栅极保护区;清除所有阻挡层,在碳化硅衬底上进行淀积金属,形成漏极金属层,在栅极附近构建了齐纳二极管,使得器件可恢复性。
Description
技术领域
本发明涉及一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法。
背景技术
碳化硅器件的碳化硅(SiC)材料因其优越的物理特性,广泛受到人们的关注和研究。其高温大功率电子器件具备输入阻抗高、开关速度快、工作频率高、耐高温高压等优点,在开关稳压电源、高频加热、汽车电子以及功率放大器等方面取得了广泛应用。
然而SiC器件由于其栅氧的质量问题,其栅极耐压特性要远低于Si基器件,在此情况下,需要针对碳化硅功率MOSFET的栅极可靠性做针对性设计,使得其可靠性提高。
发明内容
本发明要解决的技术问题,在于提供一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法,在栅极附近构建了齐纳二极管,使得器件可恢复性。
本发明是这样实现的:一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法,包括如下步骤:
步骤1、在碳化硅衬底的漂移层上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,形成基区;
步骤2、在漂移层上重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对基区进行离子注入,形成源区;
步骤3、在漂移层上重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔在源区上淀积金属,形成源极金属;
步骤4、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积形成第二栅极保护区;
步骤5、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔氧化形成栅隔离层;
步骤6、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积金属,形成栅极金属层;
步骤7、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积形成第一栅极保护区;
步骤8、清除所有阻挡层,在碳化硅衬底上进行淀积金属,形成漏极金属层。
进一步地,所述基区为P型。
进一步地,所述第一栅极保护区为N型,所述第二栅极保护区为P型。
本发明的优点在于:
该MOSFET是一种平面栅结构MOSFET,其栅极结构分布在器件的上表面;集成栅保护机制的平面栅碳化硅MOSFET,在栅极附近构建了齐纳二极管;该齐纳二极管为齐纳特性,主要靠反向pn结耐压,耐压可调整;该齐纳二极管为可恢复性,在MOSFET栅击穿之前该齐纳二极管先被击穿;使得器件新增了可恢复性。
附图说明
下面参照附图结合实施例对本发明作进一步的说明。
图1是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图一。
图2是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图二。
图3是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图三。
图4是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图四。
图5是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图五。
图6是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图六。
图7是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图七。
图8是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法流程图八。
图9是本发明一种集成栅保护机制的平面栅碳化硅MOSFET的原理示意图。
具体实施方式
请参阅图1至9所示,一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法,包括如下步骤:
步骤1、在碳化硅衬底1的漂移层2上形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔对漂移层2进行离子注入,形成基区21,所述基区21为P型;
步骤2、在漂移层2上重新形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔对基区21进行离子注入,形成源区211;
步骤3、在漂移层2上重新形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔在源区211上淀积金属,形成源极金属4;
步骤4、重新形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔淀积形成第二栅极保护区7,所述第二栅极保护区7为P型;
步骤5、重新形成阻挡a层,并对阻挡层a蚀刻形成通孔,通过通孔氧化形成栅隔离层3;
步骤6、重新形成阻挡层a,并对阻挡层a蚀刻形成通孔,通过通孔淀积金属,形成栅极金属层5;
步骤7、重新形成阻挡层a,并对阻挡层蚀a刻形成通孔,通过通孔淀积形成第一栅极保护区6,所述第一栅极保护区6为N型;
步骤8、清除所有阻挡层a,在碳化硅衬底1上进行淀积金属,形成漏极金属层8。
请参阅图9所示,上述方法得到的MOSFET,包括:
碳化硅衬底1,
漂移层2,所述漂移层2设于所述碳化硅衬底1上侧面,所述漂移层2上设有基区21,所述基区21为P型,所述基区21上设有源区211;
栅隔离层3,所述栅隔离层3设于所述漂移层2上;
源极金属层4,所述源极金属层4连接至所述源区211;
栅极金属层5,所述栅极金属层5连接至所述栅隔离层3;
第一栅极保护区6,所述第一栅极保护区6为倒凹字形,所述第一栅极保护区6连接至栅隔离层3,所述栅极金属层5设于所述第一栅极保护区6以及栅隔离层3之间,所述第一栅极保护区6为N型;
第二栅极保护区7,所述第二栅极保护区7底部连接至所述源区211,所述第二栅极保护区7两侧分别连接所述源极金属层4以及第一栅极保护区6,所述第二栅极保护区7为P型;
以及,漏极金属层8,所述漏极金属层8设于所述碳化硅衬底1下侧面。
该碳化硅MOSFET为传统的纵向平面栅功率器件,栅极保护结构在器件上表面,集成栅保护机制的平面栅碳化硅MOSFET,在栅极金属层5附近构建了齐纳二极管,第一栅极保护型区6和第二栅极保护区7共同构成了PN结,该齐纳二极管为齐纳特性,主要靠反向pn结耐压,耐压可调整,该耐压调整是通过控制第一栅极保护区6和第二栅极保护区7的大小调整的,该齐纳二极管为可恢复性,在MOSFET栅击穿之前齐纳二极管先被击穿,根据pn结二极管的特性可知,该器件为可恢复性的,那么器件在面对栅压突变的情况击穿之后可以恢复,增加了器件的可靠性。
虽然以上描述了本发明的具体实施方式,但是熟悉本技术领域的技术人员应当理解,我们所描述的具体的实施例只是说明性的,而不是用于对本发明的范围的限定,熟悉本领域的技术人员在依照本发明的精神所作的等效的修饰以及变化,都应当涵盖在本发明的权利要求所保护的范围内。
Claims (3)
1.一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法,其特征在于,包括如下步骤:
步骤1、在碳化硅衬底的漂移层上形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对漂移层进行离子注入,形成基区;
步骤2、在漂移层上重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔对基区进行离子注入,形成源区;
步骤3、在漂移层上重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔在源区上淀积金属,形成源极金属;
步骤4、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积形成第二栅极保护区;
步骤5、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔氧化形成栅隔离层;
步骤6、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积金属,形成栅极金属层;
步骤7、重新形成阻挡层,并对阻挡层蚀刻形成通孔,通过通孔淀积形成第一栅极保护区;
步骤8、清除所有阻挡层,在碳化硅衬底上进行淀积金属,形成漏极金属层;
所述第一栅极保护区为倒凹字形,所述第一栅极保护区连接至栅隔离层,所述栅极金属层设于所述第一栅极保护区以及栅隔离层之间;所述第二栅极保护区底部连接至所述源区,所述第二栅极保护区两侧分别连接所述源极金属层以及第一栅极保护区;
所述第一栅极保护型区和第二栅极保护区共同构成了PN结,在所述栅极金属层附近构建了齐纳二极管。
2.如权利要求1所述的一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法,其特征在于,所述基区为P型。
3.如权利要求1所述的一种集成栅保护机制的平面栅碳化硅MOSFET的制造方法,其特征在于,所述第一栅极保护区为N型,所述第二栅极保护区为P型。
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