CN110518069B - 具有部分碳化硅/硅半导体材料异质结的vdmos及其制作方法 - Google Patents
具有部分碳化硅/硅半导体材料异质结的vdmos及其制作方法 Download PDFInfo
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Abstract
本发明提出了一种具有部分碳化硅/硅半导体材料异质结的VDMOS及其制作方法,该异质结VDMOS器件主要特点是在外延层上形成部分具有碳化硅材料与硅材料相结合的异质结,采用硅成熟工艺形成VDMOS器件的有源区,相比于碳化硅材料,热生长氧化层与硅表面的界面质量更高,使得反型层迁移率高,也不会在栅氧化层产生很高的电场引起烧毁,而利用碳化硅半导体材料的高临界击穿电场,抬高了器件的纵向电场峰,器件可承担更高的击穿电压,同时碳化硅半导体材料的热导率高,更有利于器件散热。
Description
技术领域
本发明涉及功率半导体器件领域,尤其涉及一种垂直双扩散金属氧化物场效应管及其制作方法。
背景技术
全球能源需求的不断增长以及环境保护意识的逐步提升使得高效、节能产品成为市场发展的新趋势。电子产品的发展由于功率半导体器件的出现进入到了一个新的阶段。功率半导体器件,具有开关速度快、输入阻抗高、易驱动、不存在二次击穿的优点,垂直双扩散金属-氧化物半导体场效应晶体管(VDMOS)兼有双极晶体管和普通MOS器件的优点,无论是开关应用还是线形应用,VDMOS都是理想的功率器件,VDMOS主要应用于电机调速、逆变器、不间断电源、电子开关、高保真音响、汽车电器和电子镇流器等。
发明内容
本发明提出了一种具有部分碳化硅/硅半导体材料异质结的VDMOS及其制作方法,旨在进一步提高VDMOS的击穿电压,改善器件性能。
本发明的技术方案如下:
该具有部分碳化硅/硅半导体材料异质结的VDMOS,包括:
N+型衬底;
位于N+型衬底上表面的N型外延层;
在N型外延层上部左、右两端区域分别形成的P型基区;P型基区中形成N+型源区和P+沟道衬底接触以及相应的沟道,其中N+型源区与沟道邻接,P+沟道衬底接触相对于N+型源区位于远离沟道的一侧;
栅氧化层,位于N型外延层上表面中间区域,覆盖两处P型基区的沟道及其之间的区域;
栅极,位于栅氧化层上表面;
源极,覆盖P+沟道衬底接触与N+型源区相接区域的上表面;两处源极共接;
漏极,位于所述N+型衬底下表面;
其特殊之处在于:
所述N+型衬底采用碳化硅材料;
所述N型外延层由两部分构成:一部分为两处N型碳化硅外延层,分别位于所述N+型衬底上表面左、右两端区域;另一部分为N型硅外延层,为T字型结构,基于所述N+型衬底上表面中间区域和两处N型碳化硅外延层的上表面,并邻接所述两处N型碳化硅外延层的内侧面;两处P型基区相应形成于所述N型硅外延层上部的左、右两端区域,P型基区的纵向边界延伸入相应的N型碳化硅外延层内,即P型基区与N型碳化硅外延层形成的PN结位于N型碳化硅外延层内,沟道仍位于N型硅外延层中;
所述N型碳化硅外延层的厚度和掺杂浓度由器件的耐压要求决定,N型碳化硅外延层的掺杂浓度低于N+型衬底的掺杂浓度。
在以上方案的基础上,本发明还进一步作了如下优化:
N型碳化硅外延层的掺杂浓度比N+型衬底的掺杂浓度小4-6个数量级。
N型硅外延层的掺杂浓度为1×1015~5×1015cm-3,N型碳化硅外延层的掺杂浓度为1×1014~5×1014cm-3。
P型基区及其N+型源区和P+沟道衬底接触是采用离子注入技术形成的,相应的沟道是利用双扩散技术形成的。
两处N型碳化硅外延层是通过对外延生长的碳化硅进行中间区域刻蚀形成的,刻蚀延伸到N+型衬底上表面。
栅极为多晶硅栅极,源极为金属化源极,漏极为金属化漏极。
P型基区的纵向边界延伸入相应的N型碳化硅外延层2~4μm。
N型硅外延层T字型结构的下部宽度L2为1~4μm;每一处N型碳化硅外延层的宽度L1为6~7.5μm;N型碳化硅外延层到器件表面的距离L3为0.5~3μm。
一种制作上述具有部分碳化硅/硅半导体材料异质结的VDMOS的方法,包括以下步骤:
1)用N+型碳化硅半导体材料作为衬底;
2)在N+型碳化硅上表面形成碳化硅材料的N型外延层,刻蚀掉中间一部分之后,形成沟槽,沟槽向下到达衬底顶部,余下的记为N型碳化硅外延层;
3)利用键合技术或者异质外延生长技术形成N型硅外延层;
4)在N+型衬底下表面形成金属化漏极;
5)在N型硅外延层上部的左、右两端区域采用离子注入形成P型基区及其N+型源区和P+沟道衬底接触,并采用双扩散技术形成相应的沟道,确保P型基区的纵向边界延伸入碳化硅N型外延层内,即P型基区与N型碳化硅外延层形成的PN结位于N型碳化硅外延层内,沟道仍位于硅外延层中;
6)在整个N型硅外延层上表面生长栅氧化层之后淀积多晶硅形成多晶硅栅极;
7)在器件表面淀积钝化层,并在对应于源极的位置刻蚀接触孔;
8)在接触孔内淀积金属并刻蚀形成源极,并将两处源极共接。
本发明技术方案的有益效果如下:
VDMOS器件的衬底采用碳化硅材料,将掺杂浓度较小的N型碳化硅外延层在碳化硅N+型衬底材料上表面形成,利用刻蚀去掉中间一部分的N型碳化硅,形成沟槽,再通过异质外延技术(或键合技术)形成N型硅外延层。硅基沟道更有利于电流流过,避免了碳化硅沟道电阻大,采用硅成熟工艺形成VDMOS器件的有源区,相比于碳化硅材料,热生长氧化层与硅表面的界面质量更高,使得反型层迁移率高,也不会在栅氧化层产生很高的电场引起烧毁。利用碳化硅半导体材料的高临界击穿电场,抬高了器件的纵向电场峰,使得器件的击穿电压提高,改善了传统VDMOS中击穿电压与比导通电阻的极限关系。优化了电场分布,使器件的耐压性达到最好。同时碳化硅半导体材料的热导率高,更有利于器件散热,有效改善了器件性能。
附图说明
图1是本发明的结构示意图。
其中,1-源极;2-栅氧化层;3-栅极;4-源极;5-P+沟道衬底接触(P+型体区);6-N+型源区;7-P型基区;801-N+型衬底;802-N型碳化硅外延层;803-N型硅外延层;9-漏极。
具体实施方式
下面结合附图以N沟道VDMOS为例介绍本发明。
如图1所示,本例包括:
碳化硅材料的N+型衬底801;
在N+型衬底801上表面形成的N型碳化硅外延层802;
在N型碳化硅外延层802表面通过键合技术或者异质外延生长技术形成的N型硅外延层803;
在N型硅外延层上部的左、右两端区域分别形成两处P型基区7;
在每一处P型基区7中,利用离子注入形成N+型源区6和P+沟道衬底接触5,并与沟道接触,其中N+型源区6与沟道邻接,P+沟道衬底接触5相对于N+型源区6位于距离沟道远的一侧;
在P型基区中,纵向边界延伸入碳化硅N型外延层内,即P型基区与N型碳化硅外延层形成的PN结位于N型碳化硅外延层内,沟道仍位于硅外延层中;
覆盖N型硅外延层,在两处P型基区7之间以及相应的两处沟道上形成栅氧化层2;
在栅氧化层上表面上形成栅极3;
覆盖P+沟道衬底接触5与N+型源区6相接区域的上表面形成源极1、4;两处源极1、4共接;
在N+型衬底801下表面形成漏极9;
其中,N型碳化硅外延层的掺杂浓度比N+型衬底的掺杂浓度小4-6个数量级。N型硅外延层的掺杂浓度为1×1015~5×1015cm-3,N型碳化硅外延层的掺杂浓度为1×1014~5×1014cm-3。
P型基区的纵向边界延伸入相应的N型碳化硅外延层2~4μm。N型硅外延层T字型结构的下部宽度L2为1~4μm;每一处N型碳化硅外延层的宽度L1为6~7.5μm;N型碳化硅外延层到器件表面的距离L3为0.5~3μm。
以N沟道VDMOS为例,具体可以通过以下步骤进行制备:
1)用N+型碳化硅半导体材料作为衬底801;
2)在N+型碳化硅801上表面形成碳化硅材料的N型外延层,刻蚀掉中间一部分之后,形成沟槽,沟槽向下到达衬底顶部,余下的记为N型碳化硅外延层802;
N型碳化硅外延层802的1×1014~5×1014cm-3,N型碳化硅外延层802的掺杂浓度比N+型衬底801的掺杂浓度小4-6个数量级;
3)利用键合技术或者异质外延生长技术形成N型硅外延层803;
4)在N+型衬底801下表面形成金属化漏极;
5)在N型硅外延层上部的左、右两端区域采用离子注入形成P型基区7及其N+型源区6和P+沟道衬底接触5,并采用双扩散技术形成相应的沟道,确保P型基区的纵向边界延伸入碳化硅N型外延层内,即P型基区与N型碳化硅外延层形成的PN结位于N型碳化硅外延层内,沟道仍位于硅外延层中;
6)在整个N型硅外延层上表面形成栅氧化层,并淀积多晶硅,然后刻蚀多晶硅以及栅氧化层去除位于左、右两端区域的部分,形成多晶硅栅极;
7)在器件表面淀积钝化层,并在对应于源极的位置刻蚀接触孔;
8)在接触孔内淀积金属并刻蚀去除周边其余的钝化层形成源极,并将两处源极共接。
该异质结VDMOS器件主要特点是在外延层上形成部分具有碳化硅材料与硅材料相结合的异质结,利用外延生长技术,在碳化硅N+型衬底上形成掺杂浓度较低的N型碳化硅半导体材料外延层,利用刻蚀去掉中间一部分的N型碳化硅,形成沟槽,再以该N型碳化硅半导体外延层为基础异质外延生长(或利用键合技术)形成N型硅半导体材料外延层。采用硅成熟工艺形成VDMOS器件的有源区,相比于碳化硅材料,热生长氧化层与硅表面的界面质量更高,使得反型层迁移率高,也不会在栅氧化层产生很高的电场引起烧毁,而利用碳化硅半导体材料的高临界击穿电场,抬高了器件的纵向电场峰,器件可承担更高的击穿电压,同时碳化硅半导体材料的热导率高,更有利于器件散热。
经ISE TCAD仿真表明,该器件较之传统硅基VDMOS的性能改善,在两种器件漂移区长度相同,漂移区掺杂浓度相同的情况下,该器件的击穿电压相比于传统硅基VDMOS提高了3-4倍。例如,漂移区长度为15微米,每一处N型碳化硅外延层的宽度L1为7.5微米,N型硅外延层T字型结构的下部宽度L2为1微米,N型碳化硅外延层到器件表面的距离L3为1微米,器件的耐压可达到400V。
本发明中的VDMOS也可以为P型沟道,其结构与N沟道VDMOS等同,也应视为属于本申请权利要求的保护范围,在此不再赘述。
本发明的VDMOS中,802与803可以同型,也可以不同型,即:802为N型碳化硅外延层,803也可以为P型硅外延层;也可以802为P型碳化硅外延层,803为N型硅外延层;也可以802为P型碳化硅外延层,803为P型硅外延层。其结构与本发明等同,也应将其视为属于本申请权利要求的保护范围,在此不再赘述。
Claims (10)
1.具有部分碳化硅/硅半导体材料异质结的VDMOS,包括:
N+型衬底(801);
位于N+型衬底(801)上表面的N型外延层;
在N型外延层上部左、右两端区域分别形成的P型基区(7);P型基区(7)中形成N+型源区(6)和P+沟道衬底接触(5)以及相应的沟道,其中N+型源区(6)与沟道邻接,P+沟道衬底接触(5)相对于N+型源区(6)位于远离沟道的一侧;
栅氧化层(2),位于N型外延层上表面中间区域,覆盖两处P型基区(7)的沟道及其之间的区域;
栅极(3),位于栅氧化层(2)上表面;
源极,覆盖P+沟道衬底接触(5)与N+型源区(6)相接区域的上表面;两处源极(1、4)共接;
漏极(9),位于所述N+型衬底(801)下表面;
其特征在于:
所述N+型衬底(801)采用碳化硅材料;
所述N型外延层由两部分构成:一部分为两处N型碳化硅外延层(802),分别位于所述N+型衬底(801)上表面左、右两端区域;另一部分为N型硅外延层(803),为T字型结构,位于所述N+型衬底(801)上表面中间区域和两处N型碳化硅外延层(802)的上表面,并邻接所述两处N型碳化硅外延层(802)的内侧面;两处P型基区(7)相应形成于所述N型硅外延层(803)上部的左、右两端区域,P型基区(7)的纵向边界延伸入相应的N型碳化硅外延层(802)内,即P型基区与N型碳化硅外延层形成的PN结位于N型碳化硅外延层内,沟道仍位于N型硅外延层(803)中;
所述N型碳化硅外延层(802)的厚度和掺杂浓度由器件的耐压要求决定,N型碳化硅外延层(802)的掺杂浓度低于N+型衬底(801)的掺杂浓度。
2.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:N型碳化硅外延层(802)的掺杂浓度比N+型衬底(801)的掺杂浓度小4-6个数量级。
3.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:所述N型硅外延层(803)的掺杂浓度为1×1015~5×1015cm-3,所述N型碳化硅外延层(802)的掺杂浓度为1×1014~5×1014cm-3。
4.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:所述P型基区(7)及其N+型源区(6)和P+沟道衬底接触(5)是采用离子注入技术形成的,相应的沟道是利用双扩散技术形成的。
5.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:所述两处N型碳化硅外延层(802)是通过对外延生长的碳化硅进行中间区域刻蚀形成的,刻蚀延伸到N+型衬底(801)上表面。
6.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:栅极(3)为多晶硅栅极,源极(1、4)为金属化源极,漏极(9)为金属化漏极。
7.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:P型基区(7)的纵向边界延伸入相应的N型碳化硅外延层(802)2~4μm。
8.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:N型硅外延层(803)T字型结构的下部宽度(L2)为1~4μm;每一处N型碳化硅外延层(802)的宽度(L1)为6~7.5μm;N型碳化硅外延层(802)到器件表面的距离(L3)为0.5~3μm。
9.根据权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS,其特征在于:漂移区长度为15微米,器件的耐压要求为400V,则每一处N型碳化硅外延层的宽度(L1)为7.5微米,N型硅外延层T字型结构的下部宽度(L2)为1微米,N型碳化硅外延层到器件表面的距离(L3)为1微米。
10.一种制作权利要求1所述的具有部分碳化硅/硅半导体材料异质结的VDMOS的方法,包括以下步骤:
1)用N+型碳化硅半导体材料作为衬底(801);
2)在N+型碳化硅上表面形成碳化硅材料的N型外延层,刻蚀掉中间一部分之后,形成沟槽,沟槽向下到达衬底顶部,余下的记为N型碳化硅外延层(802);
3)利用键合技术或者异质外延生长技术形成N型硅外延层(803);
4)在N+型衬底(801)下表面形成金属化漏极;
5)在N型硅外延层(803)上部的左、右两端区域采用离子注入形成P型基区(7)及其N+型源区(6)和P+沟道衬底接触(5),并采用双扩散技术形成相应的沟道,确保P型基区的纵向边界延伸入碳化硅N型外延层内,即P型基区与N型碳化硅外延层形成的PN结位于N型碳化硅外延层内,沟道仍位于硅外延层中;
6)在整个N型硅外延层(803)上表面生长栅氧化层之后淀积多晶硅形成多晶硅栅极;
7)在器件表面淀积钝化层,并在对应于源极的位置刻蚀接触孔;
8)在接触孔内淀积金属并刻蚀形成源极,并将两处源极共接。
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