CN114207836B - 碳化硅晶体管器件 - Google Patents

碳化硅晶体管器件 Download PDF

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CN114207836B
CN114207836B CN202080055783.7A CN202080055783A CN114207836B CN 114207836 B CN114207836 B CN 114207836B CN 202080055783 A CN202080055783 A CN 202080055783A CN 114207836 B CN114207836 B CN 114207836B
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CN114207836A (zh
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M·贝利尼
L·克诺尔
S·沃思
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Hitachi Energy Co ltd
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Abstract

一种碳化硅(SiC)晶体管器件包括：具有顶表面的SiC半导体衬底(1)；形成在SiC半导体衬底(1)的顶表面上的SiC外延层(2)，该SiC外延层(2)具有顶表面；形成在SiC外延层的顶表面中的源极结构，该源极结构具有顶表面，并且包括p阱区(3)、n型源极区(4)和p型接触区(5)；沟道区(10)；和形成在源极结构的顶表面之上并且电连接至该顶表面的源极接触结构(9)，其中该源极接触结构(9)包括碳化钛(TiC)、碳化钨(WC)和碳化镍(NiC3)中的一者；包括栅极电介质(7)和栅极流道(6)的栅极结构；其中栅极电介质(7)覆盖沟道区(10)、源极结构的至少部分和源极接触结构(9)的至少部分；以及通过栅极电介质(7)而与沟道区(10)、源极结构和源极接触结构(9)电绝缘的栅极流道(6)与源极接触结构(9)的至少部分和沟道区(10)重叠。

Description

碳化硅晶体管器件
技术领域
本发明涉及根据独立权利要求的前序部分的碳化硅(SiC)晶体管器件和用于制造碳化硅(SiC)晶体管器件的方法。
背景技术
功率晶体管器件广泛地用于切换高电流和承受高电压。金属氧化物半导体场效应晶体管(MOSFET)和绝缘栅双极型晶体管(IGBT)是用于大规模或超大规模的集成电路的最重要的功率电子器件。低导通电阻和大负载电流使其非常适合用作开关器件。在功率晶体管中，控制信号被供应至与半导体衬底电绝缘的栅电极，并且通过传输电荷载流子来传导电流。功率晶体管采用类似于当今的VLSI电路的半导体处理技术，尽管器件的几何形状、电压和电流水平与在VLSI器件中所使用的设计有显著不同。大多数的晶体管，特别是用于在存储技术中储存数据的晶体管，仍然由硅(Si)制成。然而，随着电子技术的发展，高温、高频等对半导体器件和电路的要求越来越高。由于Si的材料特性，Si无法满足这些要求——特别是对于功率开关的要求，并且因此SiC材料已被开发用于在高功率、高温和高频下操作的半导体器件。对于功率开关应用，绝缘栅双极型晶体管(IGBT)和金属氧化物半导体场效应晶体管(MOSFET)被广泛使用。这些元件具有栅电极部分与元件本体电绝缘的结构。由于只需要对由栅电极和元件本体构成的电容器进行充电和放电，因此栅极控制电流显著小于例如栅极可关断晶体管的电流。
US 2013/043490 A1公开了一种半导体器件，该半导体器件包括：半导体层，该半导体层布置在衬底的主表面上并且由宽带隙半导体制成；沟槽，该沟槽布置在半导体层中，并且具有底部和侧表面；绝缘区，该绝缘区布置在沟槽的底部和侧表面上；和导电层，该导电层布置在沟槽中并且通过绝缘区而与半导体层绝缘。绝缘区包括栅极绝缘膜和间隙，该栅极绝缘膜布置在沟槽的底部和侧表面上；该间隙在沟槽的底部处布置在栅极绝缘膜与导电层之间。栅极绝缘膜在沟槽的侧表面的一部分上与导电层接触，但在沟槽的底部处不与导电层接触。从沟槽的底部贯穿到导电层的下表面测量的绝缘区的厚度在沟槽的中心周围比在沟槽的侧表面附近更大。
从EP 2 922 094 A2已知一种半导体器件，该半导体器件包括：n型SiC层；SiC区，该SiC区设置在n型SiC层上并且含有1×1018cm-3或更多且1×1022cm-3或更少的量的H(氢)或D(氘)；和金属层，该金属层设置在SiC区上。此外，在EP 2 922 094 A2中公开了一种用于生产其的方法。
US 5,455,432 A1公开了一种具有碳化物夹层的金刚石半导体器件，该金刚石半导体器件包括金刚石层和绝缘栅极结构，该金刚石层在其中具有第一传导类型的半导体金刚石区，该绝缘栅极结构在金刚石层的面上。相对薄的碳化物界面层设置在绝缘栅极结构与金刚石层之间，以便抑制诸如面处的界面态之类的电活性缺陷的形成。通过抑制面处的界面态的形成，碳化物界面层抑制了电荷载流子从金刚石层到绝缘栅极结构的寄生泄漏。碳化物界面层可以是本征碳化硅或本征难熔金属碳化物(例如，TiC或WC)，或者该层可以具有相反的传导类型，从而与金刚石层形成P-N异质结。碳化物界面层和绝缘栅极结构可以用于各种不同的金刚石电子器件中，诸如MIS电容器、增强型和埋沟道的绝缘栅极场效应晶体管(IGFET)、表面沟道的和埋沟道的电荷耦合器件(CCD)、探测器、异质结器件和其他相关的场效应器件。还公开了相关的制造方法。
US 9,224,858 A1公开了一种场效应晶体管(FET)(例如，横向双扩散金属氧化物半导体场效应晶体管(LDMOSFET))和形成该FET的方法。在FET中，蚀刻终止垫在半导体衬底(例如，P型硅衬底)上。半导体层(例如，硅层)也在该衬底上，并且在蚀刻终止垫上横向延伸。第一阱区(例如，N阱区)延伸穿过半导体层进入衬底中，使得该第一阱区含有蚀刻终止垫。第二阱区(例如，P阱区)在第一阱区中，在蚀刻终止垫上方对齐。源极区(例如，N型源极区)在第二阱区中。埋绝缘区(例如，埋气隙绝缘区)在第一阱区内，在蚀刻终止垫下方对齐，以便限制竖直电容器的形成。
WO 1997/33308公开了SiC上的金属锇(Os)，Os形成了保持牢固附接到SiC表面的接触部，并且形成了抵抗从导电金属扩散的有效势垒。在n型SiC上，Os形成了陡峭的肖特基(Schottky)整流结和肖特基二极管，该肖特基整流结具有达到至少1050℃时基本上不变的工作特性，该肖特基二极管达到1175℃仍维持可工作，并且势垒高度超过1.5eV。在p型SiC上，Os形成具有10-4ohmcm2的比接触电阻的欧姆接触部。通过在TiC层上沉积WC层，然后沉积金属W层，可以形成到SiC衬底上的TiC层的欧姆和整流接触部。这种接触部至少在1150℃下是稳定的。电极或直接地或经由保护性结合层(诸如，Pt或PtAu合金)连接到接触部。
通过使用碳化硅作为元件的基础材料，并且通过将源极区和栅极区所在的平面位置在空间上分离，并且使用具有与源电极和第二半导体层电接触的优良晶体匹配的碳化钛，从而获得能够双面压焊的元件结构，JPH 0730111 A公开了在包括漏极电极层和碳化钛的衬底上，第一半导体层、第二半导体层和第三半导体层包括一个叠置在另一顶部上的p型和n型掺杂碳化硅的外延层和源极电极层。在从第三半导体层延伸到第一半导体层的凹陷部分上形成栅极绝缘膜，并且在顶部上形成栅电极。由于栅电极设置在凹陷部分处，因此源极电极和栅电极的平面位置在空间上分离开。由与碳化硅具有优良晶体匹配的碳化钛层形成源极电极17与第二半导体层之间的接触部，从而能够得到双面压焊，从而实现具有优良的碳化硅放热特性的大电流性质。
理想的功率晶体管将具有非常短的转换时间、接近零的开关导通电阻RDS(on)和无限的功率处理能力。这些特性在很大程度上取决于器件物理和技术。当功率开关的高侧导通时，可能会导致开关节点上的高的dV/dt转换。由于米勒电容(＝栅极-漏极电容)反馈，电压的这种急剧上升可能会在低侧的MOSFET栅极上造成电压脉冲。如果栅极阈值电压是低的，则这种情况的发生可能比具有高栅极阈值的MOSFET更频繁。由跨电容建立电压变化所需的时间来确定开关器件的开关性能。RG是栅极的分布电阻，并且与有源面积近似成反比。LS和LD是源极引线电感和漏极引线电感，并且大约为几个时态的nH。在数据表中给出的输入电容(CiSS)、输出电容(CoSS)和反向传输电容(CrSS)的典型值被电路设计人员用作确定电路部件值的起点。
发明内容
因此，本发明的目的是改善射穿(shoot-through)承受能力以保护例如在图1A和图1B中示出的MOS基SiC的平面型器件和沟槽型器件，图1A示出了现有技术的沟槽型器件，并且图1B示出了现有技术的平面型器件。图1A和图1B中的两种现有技术的器件是的竖直开关，该竖直开关将竖直流动的电流从n型源极4切换到由栅极6控制的n型漏极11。在SiC衬底1上提供n型外延漂移层2。图1A和图1B中的两种器件包括p阱区3、n型源极区4、p型接触区5、栅极电介质7和栅极6。同时在图1A所示的器件中，栅极6和栅极电介质7形成在延伸穿过p阱3的沟槽内，图1B中的栅极结构6、7在器件的顶部上是平面的。根据图1B的平面型器件进一步详细示出了沟道区8。
根据本发明的一个实施例的碳化硅(SiC)晶体管器件包括：SiC半导体衬底，所述SiC半导体衬底具有顶表面；SiC外延层，所述SiC外延层形成在所述SiC半导体衬底的顶表面上，所述SiC外延层具有顶表面；源极结构，所述源极结构形成在所述SiC外延层的顶表面中，所述源极结构具有顶表面，并且包括p阱区、n型源极区和p型接触区；源极接触结构，所述源极接触结构形成在所述源极结构的顶表面上并且电连接至所述源极结构的顶表面，其中所述接触结构包含碳化钛(TiC)、碳化钨(WC)和碳化镍(NiC3)中的一者；栅极结构，所述栅极结构包括栅极电介质和栅极流道；以及p型沟道区；其中所述栅极电介质覆盖所述沟道区、所述源极结构的至少部分和所述源极接触结构的至少部分，并且其中所述栅极流道通过所述栅极电介质而与所述沟道区、所述源极结构和所述源极接触结构电绝缘，并且所述栅极流道与所述源极接触结构的至少部分和所述沟道区重叠，其中所述栅极结构是平面结构。
在另一实施例中，所述源极接触结构具有2nm至200nm范围内的厚度。
在另一实施例中，所述SiC半导体衬底是4H-SiC衬底。
在另一实施例中，所述碳化硅(SiC)晶体管器件是绝缘栅双极型晶体管(IGBT)。
在另一实施例中，所述碳化硅(SiC)晶体管器件是金属氧化物半导体场效应晶体管(MOSFET)。
本发明的另一实施例涉及一种用于制造碳化硅(SiC)晶体管器件的方法，该方法包括如下步骤：在SiC半导体衬底的顶表面上外延地形成SiC外延层，所述SiC外延层具有顶表面；在所述SiC外延层的顶表面中形成源极结构，所述源极结构具有顶表面，并且包括p阱区、n型源极区和p型接触区；在所述源极结构的顶表面上形成源极接触结构，并且所述源极接触结构电连接到所述源极结构的顶表面，其中所述接触结构包含碳化钛(TiC)、碳化钨(WC)和碳化镍(NiC3)中的一者；以及在形成所述源极接触结构之后，形成包括栅极电介质和栅极流道的栅极结构，使得所述栅极电介质覆盖所述源极结构的至少部分和所述源极接触结构的至少部分，并且使得通过所述栅极电介质而与所述源极结构和所述源极接触结构电绝缘的所述栅极流道与所述源极接触结构的至少部分重叠，其中所述器件包括p型沟道，并且其中所述栅极结构是平面结构。
在用于制造碳化硅(SiC)晶体管器件的方法的另一实施例中，在600℃至1300℃的范围内的温度下形成所述源极接触结构。
通过参考附图进行的本发明的示例性实施例的以下详细描述，本发明的前述和其他目的、特征和优点将变得更加明显。
附图说明
图1A和图1B示出了现有技术的MOS基竖直SiC的沟槽型器件(图1A)和平面型器件(图1B)。
图2A、图2B、图2C示出了根据实施例的用于制造竖直碳化硅(SiC)平面型晶体管器件的过程中的集成次序。
图2D示出了作为对比示例的具有沟槽栅极结构的竖直功率MOSFET，该对比示例不构成所要求保护的发明的一部分但用于更好地理解本发明。
具体实施方式
通过在低侧MOSFET和高侧MOSFET的组合中控制上述反馈机制(Cgd和Cgs)中所涉及的电容的比率，可以由如下方程限定VGS脉冲：
Figure BDA0003495627450000051
为了改善开关晶体管的射穿(shoot-through)能力，所期望的是低的CrSS/CiSS电容比率(典型地小于0.4)。为了降低CrSS/CiSS电容比率，可以降低反向传输电容(CrSS)、和/或可以增加输入电容(CiSS)。
为了增加CiSS，提出由碳化钛(TiC)源极接触部替代通常使用的镍硅化物接触部。例如与镍硅化物相比，一个优势是TiC更稳定并且可以承受更高的温度。镍硅化物不能承受栅极氧化和聚合沉积(poly deposition)的温度，也不能实现所描述的集成次序。为了甚至在低阈值电压器件中进一步防止射穿，进一步提出了通过将栅电极和TiC源极接触部重叠来调节CiSS。通过将栅电极和TiC源极接触部重叠，可以增加CiSS，并且可以减轻射穿。例如在图2C中示出的，根据本发明的一个实施例的碳化硅(SiC)晶体管器件包括：具有顶表面和底表面的SiC半导体衬底1；在SiC半导体衬底1的底表面上的漏极区11；形成在SiC半导体衬底1的顶表面上的SiC外延层2，该SiC外延层2具有顶表面；形成在SiC外延层2的顶表面中的源极结构3、4、5，该源极结构3、4、5具有顶表面；形成在源极结构3、4、5的顶表面之上并且电连接到该源极结构3、4、5的顶表面的源极接触结构9，其中该源极接触结构9包含碳化钛(TiC)、碳化钨(WC)和碳化镍(N1C3)中的一者；包括栅极电介质7和栅极流道6的栅极结构6、7；和p型沟道区10，其中该栅极电介质7覆盖该沟道区10、该源极结构3、4、5的至少部分和该源极接触结构9的至少部分，并且其中该栅极流道6通过该栅极电介质7而与沟道区10、源极结构3、4、5和源极接触结构9电绝缘，并且该栅极流道6与源极接触结构9的至少部分和沟道区10重叠。源极结构3、4、5包括p阱区3、n型源极区4、和p型接触区5。
例如，SiC半导体衬底1可以是例如3C-SiC、4H-SiC衬底或6H-SiC衬底。例如，在3C-SiC外延层的情况下，SiC半导体衬底1可以由硅(Si)衬底替代。
例如，源极接触结构9可以具有2nm至200nm范围内的厚度。在示例性实施例中，厚度为70nm。
例如，碳化硅(SiC)晶体管可以是绝缘栅双极型晶体管(Insulated Gate BipolarTransistor，IGBT)或金属氧化物半导体场效应晶体管(Metal-Oxide-SemiconductorField-Effect Transistor，MOSFET)、碳化硅结型场效应晶体管(SiC junction Field-Effect transistor，SiC-JFET)或碳化硅双极结型晶体管(SiC bipolar junctiontransistor，SiC-BJT)。
由于TiC与n型SiC形成电欧姆接触结，并且TiC在高于1000℃的温度下在表面粗糙度和电性能方面非常稳定，因此可以在氧化物沉积/氧化过程之前制造碳化钛(TiC)源极接触部。这种氧化物沉积/氧化过程是必要的，例如，对于栅极电介质形成、栅极绝缘或钝化是必要的，以及对于(例如，用于栅极流道的)多晶硅层沉积和高温暴露/活化步骤是必要的。对于常规的镍硅化物源极接触部，由于镍硅化物接触部的温度敏感性，必须在源极接触部沉积之前执行氧化物沉积/氧化过程。因此，TiC源极接触部的使用允许集成需要高热预算的全新的过程步骤。在图2A至图2C中示出用于制造平面型竖直功率MOSFET的典型的集成次序。
从图2A中的平面型MOS基器件开始，其中在SiC衬底1上提供n型外延漂移层2。图2A至图2C中的器件还包括p阱区3、n型源极区4、p型接触区5、和p型沟道区10。如上面已经提到的，与现有技术的制造过程相反，根据本发明的制造过程的实施例，在形成栅极结构(该栅极结构由栅极6和可以是栅极电介质的栅极绝缘体7构成)之前，按照过程步骤的顺序，形成用于接触该源极区4的TiC接触结构9。需要强调的是，根据本发明的制造过程的实施例，在TiC源极接触结构9之后形成栅极结构6、7。因为TiC承受高温的能力，(改变制造过程步骤的顺序的)这种集成方案是可能的。
作为对比示例，在图2D中示出了具有沟槽栅极结构的竖直功率MOSFET。在该对比示例中，栅极结构不是平面地形成在SiC半导体衬底1的顶表面上，而是在p阱区3内且在n型源极区4之间竖直地形成沟槽中。在该对比示例中，栅电极6形成在沟槽内并且被栅极电介质7绝缘。
本发明的另一实施例涉及一种用于制造碳化硅(SiC)晶体管器件的方法，该方法包括如下步骤：在SiC半导体衬底1的顶表面上外延地形成SiC外延层2，该SiC外延层2具有顶表面；在SiC外延层2的顶表面中形成源极结构3、4、5，该源极结构3、4、5具有顶表面；在源极结构3、4、5的顶表面之上形成源极接触结构9，并且该源极接触结构9电连接该源极结构3、4、5的顶表面，其中接触结构9包含碳化钛(TiC)、碳化钨(WC)和碳化镍(NiC3)中的一者；在形成源极接触结构9之后形成包括栅极电介质7和栅极流道6的栅极结构6、7，使得该栅极电介质7覆盖该源极结构3、4、5的至少部分和源极接触结构9的至少部分，并且通过栅极电介质7而与源极结构3、4、5和源极接触结构9电绝缘的栅极流道6与源极接触结构9的至少部分重叠。
在用于制造碳化硅(SiC)晶体管器件的方法的另一实施例中，在600℃至1300℃的范围内的温度下形成源极接触结构9。
在另一实施例中，例如，可以使用四氯化钛作为Ti源并且使用乙烯作为碳源，在稀释氢中，在1200℃至1300℃的范围内，通过化学气相沉积(Chemical Vapor Deposition，CVD)过程，来形成具有70nm厚度的TiC接触层。该温度在TiC形成时对TiC进行退火。在一实施例中，例如，TiC厚度可以小于约180nm，以避免SiC层中的应变。

Claims (7)

1.一种碳化硅(SiC)晶体管器件，包括：
SiC半导体衬底(1)，所述SiC半导体衬底(1)具有顶表面；
SiC外延层(2)，所述SiC外延层(2)形成在所述SiC半导体衬底(1)的顶表面上，所述SiC外延层(2)具有顶表面；
源极结构(3、4、5)，所述源极结构(3、4、5)形成在所述SiC外延层(2)的顶表面中，所述源极结构(3、4、5)具有顶表面，并且包括p阱区(3)、n型源极区(4)和p型接触区(5)；
源极接触结构(9)，所述源极接触结构(9)形成在所述源极结构(3、4、5)的顶表面之上并且电连接至所述源极结构(3、4、5)的顶表面；
栅极结构(6、7)，所述栅极结构(6、7)包括栅极电介质(7)和栅极流道(6)；和
p型沟道区(10)；
其中，
所述栅极电介质(7)覆盖所述沟道区(10)、所述源极结构(3、4、5)的至少部分和所述源极接触结构(9)的至少部分；以及
通过所述栅极电介质(7)而与所述沟道区(10)、所述源极结构(3、4、5)和所述源极接触结构(9)电绝缘的所述栅极流道(6)与所述源极接触结构(9)的至少部分和所述沟道区(10)重叠，
其特征在于，
所述源极接触结构(9)包括碳化钛(TiC)、碳化钨(WC)和碳化镍(NiC3)中的一者；以及
所述栅极结构(6、7)是平面结构。
2.根据权利要求1所述的碳化硅(SiC)晶体管器件，其中，所述源极接触结构(9)具有2nm至200nm范围内的厚度。
3.根据权利要求1至2中任一项所述的碳化硅(SiC)晶体管器件，其中，所述SiC半导体衬底(1)是4H-SiC衬底。
4.根据权利要求1至3中任一项所述的碳化硅(SiC)晶体管器件，其中，所述碳化硅(SiC)晶体管器件是绝缘栅双极型晶体管(IGBT)。
5.根据权利要求1至3中任一项所述的碳化硅(SiC)晶体管器件，其中，所述碳化硅(SiC)晶体管器件是金属氧化物半导体场效应晶体管(MOSFET)。
6.一种用于制造碳化硅(SiC)晶体管器件的方法，包括：
在SiC半导体衬底(1)的顶表面上外延地形成SiC外延层(2)，所述SiC外延层(2)具有顶表面；
在所述SiC外延层(2)的顶表面中形成源极结构(3、4、5)，所述源极结构(3、4、5)具有顶表面，并且包括p阱区(3)、n型源极区(4)和p型接触区(5)；
在所述源极结构(3、4、5)的顶表面之上形成源极接触结构(9)，并且所述源极接触结构(9)电连接到所述源极结构(3、4、5)的顶表面，其中所述接触结构(9)包括碳化钛(TiC)、碳化钨(WC)和碳化镍(NiC3)中的一者；以及
在形成所述源极接触结构(9)之后，形成包括栅极电介质(7)和栅极流道(6)的栅极结构(6、7)，使得所述栅极电介质(7)覆盖所述源极结构(3、4、5)的至少部分和所述源极接触结构(9)的至少部分，并且使得通过所述栅极电介质(7)而与所述源极结构(3、4、5)和所述源极接触结构(9)电绝缘的所述栅极流道(6)与所述源极接触结构(9)的至少部分重叠，
其中，所述器件包括p型沟道(10)，
其中，所述栅极结构(6、7)是平面结构。
7.根据权利要求6所述的用于制造碳化硅(SiC)晶体管器件的方法，其中，在600℃至1300℃的范围内的温度下形成所述源极接触结构(9)。
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