CN107403835A - 半导体装置及其制作工艺 - Google Patents

半导体装置及其制作工艺 Download PDF

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CN107403835A
CN107403835A CN201610340188.3A CN201610340188A CN107403835A CN 107403835 A CN107403835 A CN 107403835A CN 201610340188 A CN201610340188 A CN 201610340188A CN 107403835 A CN107403835 A CN 107403835A
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substrate
semiconductor device
clearance wall
groove
device described
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CN107403835B (zh
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刘升旭
李镇全
吕水烟
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United Semiconductor Xiamen Co Ltd
United Microelectronics Corp
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United Semiconductor Xiamen Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体装置以及该半导体装置的制作工艺，该半导体装置包含栅极以及外延结构。其中，栅极是设置在基底上。外延结构则是设置在基底内并介于两栅极结构之间，且基底的一凸部在一投影方向上是延伸至外延结构内。

Description

半导体装置及其制作工艺
技术领域
本发明涉及一种半导体装置及其制作工艺，特别是涉及一种具有外延结构的半导体装置及其制作工艺。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selective epitaxial growth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同的外延结构，例如硅锗(silicon germanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(lattice constant)大于该硅基底晶格的特点，对P型金属氧化物半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carrier mobility)，并用于增加金属氧化物半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(siliconcarbide,SiC)外延结构，对栅极通道区产生伸张应力。
前述方法虽然可以有效提升通道区的载流子迁移率，却导致整体制作工艺的复杂度以及制作工艺控制的难度，尤其是在半导体元件尺寸持续缩小的趋势下。举例来说，现有技术往往先于硅基底中定义一凹槽，然后于凹槽中形成一缓冲层(buffer layer)后再形成一外延层。然而，现行制作工艺仍有许多待改进的缺点，例如该缓冲层的厚度不均，而可能导致短通道效应(short channel effect)或漏极引发能带降低(drain induce barrierlowering,DIBL)等负面影响，造成漏电流增加并损及元件的品质及效能。
发明内容
本发明提供一种半导体装置，其具有优化的缓冲层，因而能达到较佳的元件效能。
本发明另提供一种半导体装置的制作工艺，其可形成优化的缓冲层，而可避免前述因缓冲层的缺陷而引发的负面影响。
本发明的目的在于提供一种半导体装置，其包含二栅极以及外延结构。其中，栅极是设置在一基底上。外延结构则是设置在基底内并介于二栅极之间，且基底的一凸部在一投影方向上是延伸至外延结构内。
本发明的目的在于提供一种半导体装置的制作工艺，包含以下步骤。首先，在一基底上形成二栅极。接着，形成一间隙壁环绕各该栅极。然后，利用该间隙壁为一掩模，于该基底内形成一沟槽，该沟槽介于该二栅极之间。并且，于该沟槽形成后，部分移除该间隙壁以暴露该基底的一凸部的顶表面。最后，于该沟槽内选择性形成一外延结构。
本发明的半导体装置及其制作工艺主要是利用两次或两次以上的干蚀刻制作工艺以在基底中形成具有略呈圆形或呈正圆形的沟槽，由此，邻接沟槽两侧的鳍状结构(基底)则会因沟槽形状的影响而形成凸部，该凸部具有朝向该沟槽的锐角或是钝角。接着利用部分移除作为前述两次或两次以上干蚀刻制作工艺的蚀刻掩模的间隙壁，而暴露该凸部。由此，在后续形成外延结构时，缓冲层可均匀且共形地形成在该沟槽以及该凸部的表面，因而可形成具有单一厚度的优化缓冲层。由此，本发明的半导体装置可有效改善缓冲层的品质，进而避免因缓冲层的缺陷而引发的负面影响，如短通道效应等。
附图说明
图1至图7为本发明第一实施例中半导体装置的步骤示意图；其中：
图1为本发明一半导体装置于制作工艺初始时的示意图；
图2为本发明一半导体装置于形成一侧壁材料层后的示意图；
图3为本发明一半导体装置于形成一间隙壁后的示意图；
图4为本发明一半导体装置于形成一初始沟槽后的示意图；
图5为本发明一半导体装置于形成一沟槽后的示意图；
图6为本发明一半导体装置于移除一间隙壁后的示意图；
图7为本发明一半导体装置于形成一外延结构后的示意图。
图8至图11绘示本发明第二实施例中半导体装置的步骤示意图，其中：
图8为本发明一半导体装置于形成另一侧壁材料层后的示意图；
图9为本发明一半导体装置于形成另一间隙壁后的示意图；
图10为本发明一半导体装置于形成一沟槽后的示意图；
图11为本发明一半导体装置于形成一外延结构后的示意图。
主要元件符号说明
300 基底
320 鳍状结构 321 凸部
321a 顶表面 323 凸部
323a 顶表面
340 栅极结构 341 栅极介电层
342 虚置栅极 343 帽盖层
344 间隙壁 345 轻掺杂源极/漏极
346 间隙壁 346a 第二侧壁材料层
348 间隙壁 348a 第三侧壁材料层
360 沟槽 362 沟槽
364 沟槽
365 外延结构 366 第一外延层
367 第二外延层
370 外延结构 368 第一外延层
369 第二外延层
θ1、θ2 锐角
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个较佳实施例，并配合所附附图，详细说明本发明的构成内容及所欲达成的功效。
请参照图1至图7，所绘示者为本发明第一实施例中形成半导体装置的制作工艺示意图。首先，如图1所示，提供一基底300，例如一硅基底(silicon substrate)、外延硅(epitaxial silicon substrate)或硅覆绝缘(silicon on insulation,SOI)基板，并且在基底300上形成至少一栅极结构340。在本实施例中，可选择先在基底300上形成至少一鳍状结构320及一绝缘层(未绘示)，再于鳍状结构320上形成横跨于其上的栅极结构340。在一实施例中，鳍状结构320的形成方式例如是利用间隙壁自对准双图案法(spacer self-aligned double-patterning,SADP)，于基底300上形成一图案化掩模(未绘示)，再经过一蚀刻制作工艺，将该图案化掩模的图案转移至基底300中，再移除该图案化掩模，即可在基底300中形成多个沟槽(未绘示)，后续在该些沟槽中填入绝缘层(未绘示)，使得突出于该绝缘层的基底300形成鳍状结构320，该绝缘层则可形成浅沟隔离。在其他实施例中，若形成的晶体管为平面晶体管(planar transistor)，也可省略该鳍状结构，直接在平面基底(未绘示)上形成该栅极结构。
栅极结构340包含一栅极介电层(gate dielectric layer)341、一虚置栅极(dummy gate)342、一帽盖层(capping layer)343以及一间隙壁(spacer)344。其中，栅极介电层341例如可包含氧化硅(SiO2)或氮化硅(SiN)；虚置栅极342例如是多晶硅(polysilicon)，包含不具有任何掺质(undoped)多晶硅材料、具有掺质的多晶硅材料、或非晶硅材料等，但也可以是由上述材料的组合。帽盖层343可选择为一复合膜层结构，或者是如图1所示的一单一膜层结构，例如包含氮化硅、碳化硅(SiC)、碳氮化硅(SiCN)或上述材料的组合等。间隙壁344同样可选择为一单层或复合膜层的结构，例如其可包含高温氧化硅层(high temperature oxide,HTO)、氮化硅、氧化硅、氮氧化硅或使用六氯二硅烷(hexachlorodisilane,Si2Cl6)形成的氮化硅(HCD-SiN)等耐蚀刻且覆盖能力好的材质，如氮化硅。在一实施例中，栅极结构340形成步骤，例如先在基底300上全面形成一栅极介电材料层(未绘示)、一虚置栅极材料层(未绘示)以及一帽盖材料层(未绘示)后，然后再图案化该些堆叠材料层，以形成了一栅极堆叠结构(未绘示)。接着，再于该栅极堆叠结构两侧的鳍状结构320(基底300)中形成二轻掺杂源极/漏极345(light doped drain region,LDD)，最后再于该栅极堆叠结构的侧壁上形成一第一侧壁材料层(未绘示)，而后再经一蚀刻制作工艺而形成间隙壁344。然而，本领域者应可轻易了解，本发明的栅极结构也可能以其他方式形成，并不限于前述的制作步骤。举例来说，在另一实施例中，也可选择直接于基底300上形成一金属栅极结构(未绘示)，该金属栅极结构至少包含一功函数金属层(work functionlayer)及一金属栅极。
接着，形成环绕间隙壁344的一间隙壁346。在一实施例中，间隙壁346的形成方式例如是与间隙壁344的形成方式相近，包含先行成一第二侧壁材料层346a，例如是包含氧化硅等与间隙壁344具蚀刻选择且较易于蚀刻的材质，覆盖在鳍状结构320(基底300)以及间隙壁344上，如图2所示，然后进行一蚀刻制作工艺，例如是一干蚀刻制作工艺，以形成环绕栅极结构的间隙壁346，如图3所示。
如图4所示，利用栅极结构340与间隙壁344、346作为蚀刻掩模进行一第一蚀刻制作工艺，例如是一干蚀刻制作工艺，以在分别在栅极结构340两侧的鳍状结构320(基底300)上形成一沟槽360。也就是说，该蚀刻制作工艺例如是沿着间隙壁344、346向下垂直蚀刻(vertical etch)鳍状结构320(基底300)，而于各栅极结构340两侧的鳍状结构320(基底300)中形成沟槽360，其侧壁是与间隙壁346垂直切齐，而其底部则约略呈现圆弧状，如图4所示。
而后，如图5所示，接着进行一第二蚀刻制作工艺，例如同样是一干蚀刻制作工艺，以进一步蚀刻该第一蚀刻制作工艺所蚀刻出的沟槽360，特别是蚀刻沟槽360的侧壁，较佳是横向蚀刻位于间隙壁346下方的鳍状结构320(基底300)，并进一步扩大沟槽360的面积，最后形成沟槽362。详细来说，该第二蚀刻制作工艺例如是调整制作工艺机台的偏压，例如可稍微降低所施加的偏压功率(bias power)，使该第二干蚀刻制作工艺可以侧向蚀刻(lateral etch)方式扩展沟槽360，而不会出现一般湿蚀刻制作工艺沿特定结晶面蚀刻速率较快形成钻石、六角等多边形(hexagon,又可称为sigmaΣ)沟槽结构的现象。另外经由该第二次干蚀刻制作工艺以侧向蚀刻方式扩展沟槽360的面积后，可在栅极结构340旁的鳍状结构320(基底300)中形成一约略呈圆形，或呈正圆形的沟槽362，如图5所示。另一方面，邻接沟槽362两侧的鳍状结构320(基底300)则因沟槽362的而形成朝向沟槽362延伸的一尖端，其具有朝向沟槽362延伸的一锐角θ1，约为15度至45度，如图5所示。
需注意的是，本实施例虽进行两次干蚀刻制作工艺来蚀刻出略呈圆形或呈正圆形的沟槽362，但所进行的干蚀刻制作工艺数量并不局限于两次，本发明可依据制作工艺需求或蚀刻的结果随时调整干蚀刻制作工艺的次数，或者是不限于干蚀刻，而是以一此以上的干蚀刻搭配湿蚀刻制作工艺，通过是当的蚀刻剂，使沟槽362由一开始约略矩形而一直扩展到呈现完美的圆形为止，此变化型也属本发明所涵盖的范围。
然后，移除间隙壁346，以暴露出下方的鳍状结构320(基底300)，而形成一凸部321，如图6所示。具体来说，凸部321即是由前述鳍状结构320(基底300)该尖端中未被间隙壁344覆盖的部分形成，因而同样具有朝向沟槽362延伸的锐角θ1，如图6所示。
在沟槽362形成后，则可选择性进行一预清洗(pre-clean)步骤，利用稀释氢氟酸水溶液(diluted hydrofluoric acid)或一含有硫酸、过氧化氢、与去离子水的SPM混合溶液等清洗液来去除沟槽362表面的原生氧化物或其他不纯物质。然后，在沟槽362内形成填满沟槽362的一外延结构365，如图7所示。
外延结构365具有高于鳍状结构320(基底300)的顶表面的一顶表面，且该顶表面的长度大于沟槽362开口的宽度，如图7所示。具体来说，外延结构365例如包含一第一外延层366以及一第二外延层367。其中，第一外延层366例如是做为一缓冲层(buffer layer)，其是共形地(conformally)形成在沟槽362以及凸部321的顶表面321a以覆盖并直接接触沟槽362的表面以及凸部321的顶表面321a，因此，第一外延层366较佳是具有一均一厚度，并且是完全环绕凸部321，如图7所示。接着可进行一选择性外延成长制作工艺，以在第一外延层366上形成第二外延层367，其可填满沟槽362至高于鳍状结构320(基底300)的该顶表面。由此，鳍状结构320(基底300)凸部321在垂直鳍状结构320(基底300)投影方向上即是延伸至外延结构365内，而可完全被外延结构365环绕。
第一外延层366可选择包含纯硅(pure silicon)或仅含10％以下掺质(dopant)的硅。而第二外延层367可根据后续形成的金属氧化物半导体(MOS)晶体管类型而可以具有不同的材质。举例来说，若该金属氧化物半导体晶体管为一P型晶体管(PMOS)时，第二外延层367可选择包含硅化锗(SiGe)、硅化锗硼(SiGeB)或硅化锗锡(SiGeSn)；若该金属氧化物半导体晶体管为一N型晶体管(NMOS)时，则第二外延层367则可选择包含碳化硅(SiC)、碳磷化硅(SiCP)或磷化硅(SiP)。在本实施例中，第一外延层366(即缓冲层)及第二外延层367例如皆可包含硅化锗，其中，第一外延层366的锗浓度低于第二外延层367的锗浓度且仅包含10％以下的锗，以缓冲沟槽362、凸部321的表面与后续形成于第一外延层366上具较高锗浓度的第二外延层367，如此可减少外延结构365的差排缺陷。此外，选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如锗原子)也可以浓度梯度的方式改变，以利后续的制作工艺。
由此，即完成本发明第一较佳实施例中形成半导体装置的方法。后续，还可进行一离子注入制作工艺，例如较佳是与第二外延层367形成时一并进行一原位掺杂(in situdoping)，以在外延结构365的至少一部分形成一源极/漏极(未绘示)；一金属栅极置换(replacement metal gate)制作工艺，将虚置栅极342转换为一金属栅极；一金属硅化物制作工艺，例如可先在该源极/漏极(外延结构365)的顶表面形成一硅盖层(silicon cap)，再于该源极/漏极的至少部分表面形成一金属硅化物层；及/或一接触插塞制作工艺，形成电连接该源极/漏极及/或该金属栅极的接触插塞。
本实施例的制作工艺主要是利用两次或两次以上的干蚀刻制作工艺以在基底中形成具有略呈圆形或呈正圆形的沟槽，由此，邻接沟槽两侧的鳍状结构(基底)则会因沟槽形状的影响而形成一尖端，该尖端具有朝向该沟槽(及外延结构)的锐角。接着利用部分移除作为前述两次或两次以上干蚀刻制作工艺的蚀刻掩模的间隙壁，而暴露出该尖端的一部分而呈现一凸部。由此，在后续形成外延结构时，缓冲层可均匀且共形地形成在该沟槽以及该凸部的表面，因而可形成具有单一厚度的缓冲层。由此，本发明的半导体装置可有效改善缓冲层的品质，进而避免因缓冲层的缺陷而引发的负面影响，如短通道效应等。
下文将针对本发明半导体装置制作工艺的其他实施例进行说明。且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
请参照图8至图11所示，所绘示者为本发明第二较佳实施例中形成半导体装置的步骤示意图。本实施例的半导体装置的部分制作工艺大体上和前述第一实施例的图1至图4相同，在此不再赘述。本实施例与前述实施例的主要差异在于，在形成如图4所示的半导体结构后，额外形成环绕间隙壁346的一间隙壁348。在一实施例中，间隙壁348的形成方式例如是与间隙壁344、346的形成方式相近，包含先行成一第三侧壁材料层348a，例如是包含氮氧化硅(silicon oxynitride,SiON)等与间隙壁344具蚀刻选择且较易于蚀刻的材质，覆盖在鳍状结构320(基底300)以及间隙壁346上，如图8所示，然后进行一蚀刻制作工艺，例如是一干蚀刻制作工艺，以形成环绕栅极结构的间隙壁348，其中，间隙壁348还进一步延伸至沟槽360的侧壁上，如图9所示。
如图10所示，接着利用栅极结构340与间隙壁348作为蚀刻掩模进行进行一第三蚀刻制作工艺，例如是一干蚀刻制作工艺，以进一步蚀刻该第一蚀刻制作工艺所蚀刻出的沟槽360。其中，蚀刻沟槽360的侧壁因已被间隙壁348覆盖，因此，该第三蚀刻制作工艺仅会横向蚀刻位于间隙壁348下方的鳍状结构320(基底300)，并进一步扩大沟槽360的面积，最后形成沟槽364。详细来说，该第三蚀刻制作工艺在进行时例如同样是调整制作工艺机台的偏压，例如降低所施加的偏压功率，使该第三蚀刻制作工艺主要是以侧向蚀刻方式扩展沟槽360，而可在栅极结构340旁的鳍状结构320(基底300)中形成一约略呈圆形，或呈正圆形的沟槽364，如图10所示。另外，因间隙壁348覆盖部分沟槽360的缘故，相较于前述第一实施例的沟槽362，沟槽364中略呈圆形或呈正圆形的部分会位于鳍状结构320(基底300)较深的部分(其增加的深度即为第一实施例中沟槽362的深度)，而间隙壁348覆盖部分则形成垂直于鳍状结构320(基底300)顶表面的侧壁，如图10所示。也就是说，在本实施例中，经由该第三次干蚀刻制作工艺以侧向蚀刻方式扩展沟槽360的面积后，虽然邻接沟槽362两侧的鳍状结构320(基底300)同样可因沟槽364的而形成一尖端，但该尖端具有朝向沟槽364延伸的一钝角θ2，如图10所示。此外，在另一实施例中，也可选择直接利用该第三侧壁材料层作为蚀刻掩模以进一步扩展沟槽360的面积，即可使第三间隙壁348及沟槽364在同一蚀刻制作工艺中形成(未绘示)。
然后，一并移除间隙壁348及间隙壁346，以暴露出位于间隙壁346下方的鳍状结构320(基底300)，而形成一凸部323，如图10所示。具体来说，凸部323即是由前述鳍状结构320(基底300)该尖端中未被间隙壁344覆盖的部分形成，因而同样具有朝向沟槽364延伸的钝角θ2，如图10所示。
接着，可选择性进行一预清洗步骤，利用稀释氢氟酸水溶液或一含有硫酸、过氧化氢、与去离子水的SPM混合溶液等清洗液来去除沟槽364表面的原生氧化物或其他不纯物质。然后，在沟槽364内形成填满沟槽364的一外延结构370。
外延结构370可具有高于鳍状结构320(基底300)该顶表面的一顶表面。具体来说，外延结构370例如包含一第一外延层368以及一第二外延层369。其中，第一外延层368例如是做为一缓冲层，其是共形地形成在沟槽364以及凸部323的顶表面323a以覆盖沟槽364的所有表面以及凸部323的顶表面323，因此，第一外延层368较佳是具有一均一厚度，并且是完全环绕凸部323，如图11所示。接着，可进行一选择性外延成长制作工艺，以在第一外延层368上形成第二外延层369，其可填满沟槽364至高于鳍状结构320(基底300)的该顶表面。由此，鳍状结构320(基底300)凸部323在垂直鳍状结构320(基底300)投影方向上即是延伸至外延结构370内，而可完全被外延结构370环绕。
第一外延层368可选择包含纯硅或仅含10％以下掺质的硅。而第二外延层369可根据后续形成的金属氧化物半导体晶体管类型而可以具有不同的材质。举例来说，若该金属氧化物半导体晶体管为一P型晶体管时，第二外延层369可选择包含硅化锗、硅化锗硼或硅化锗锡等；若该金属氧化物半导体晶体管为一N型晶体管时，则第二外延层369则可选择包含碳化硅、碳磷化硅或磷化硅等。在本实施例中，第一外延层368(即缓冲层)及第二外延层369例如皆可包含硅化锗，其中第一外延层368的锗浓度低于第二外延层369的锗浓度且仅包含10％以下的锗，以缓冲沟槽364、凸部323的表面与后续形成于第一外延层368上具较高锗浓度的第二外延层369，如此可减少外延结构370的差排缺陷。此外，选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如锗原子)也可以渐层的方式改变，以利后续的制作工艺。
由此，即完成本发明第二较佳实施例中形成半导体装置的方法。后续，还可进行一离子注入制作工艺，例如较佳是与第二外延层369形成时一并进行一原位掺杂，以在外延结构370的至少一部分形成一源极/漏极(未绘示)；一金属栅极置换制作工艺，将虚置栅极342转换为一金属栅极；一金属硅化物制作工艺，例如可先在该源极/漏极(外延结构370)的顶表面形成一硅盖层，再于该源极/漏极的至少部分表面形成一金属硅化物层；及/或一接触插塞制作工艺，形成电连接该源极/漏极及/或该金属栅极的接触插塞。
本实施例的制作工艺则是在第一次干蚀刻已形成一初始沟槽后，额外形成部分覆盖该初始沟槽的间隙壁，再接着利用一次或一次以上的干蚀刻制作工艺，在基底中形成具有略呈圆形或呈正圆形的沟槽，由此，邻接沟槽两侧的鳍状结构(基底)则同样会因沟槽形状的影响而形成尖端，其具有朝向该沟槽(及外延结构)的垂直侧壁以及钝角。接着部分移除作为前述干蚀刻制作工艺的蚀刻掩模的间隙壁，而暴露出该尖端的一部分而呈现一凸部。由此，在后续形成外延结构时，缓冲层可均匀且共形地形成在该沟槽以及该凸部的表面，因而可形成具有单一厚度的缓冲层。由此，本发明的半导体装置可有效改善缓冲层的品质，进而避免因缓冲层的缺陷而引发的负面影响，如短通道效应等。
另外，前述各实施例虽皆以鳍状场效晶体管(Fin-FET)等非平面晶体管(non-planar transistor)的制作方法为实施样态进行说明，但本领域技术人员应可理解本发明也可应用于其他平面晶体管(planar transistor)，该些实施例仍应属本发明所涵盖的范围。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种半导体装置，其特征在于包含：
二栅极，设置在一基底上；以及
外延结构，设置在该基底内并介于该二栅极之间，其中该基底的一凸部在一投影方向上是延伸至该外延结构内。
2.依据权利要求1所述的半导体装置，其特征在于还包含第一间隙壁，该基底该凸部的一顶表面未被该第一间隙壁覆盖。
3.依据权利要求1所述的半导体装置，其特征在于，该基底该凸部的一顶表面直接接触该外延结构。
4.依据权利要求1所述的半导体装置，其特征在于，该基底的该凸部包含朝向该外延结构的一锐角。
5.依据权利要求1所述的半导体装置，其特征在于，该基底的该凸部包含朝向该外延结构的一钝角。
6.依据权利要求1所述的半导体装置，其特征在于，该基底的该凸部包含一侧壁，该侧壁垂直于该基底的一顶表面。
7.依据权利要求1所述的半导体装置，其特征在于，该外延结构的一顶表面高于该基底的一顶表面。
8.依据权利要求1所述的半导体装置，其特征在于，该外延结构包含：
第一外延层；以及
第二外延层，设置在该第一外延层上。
9.依据权利要求1所述的半导体装置，其特征在于，该第一外延层围绕该基底的该凸部。
10.依据权利要求1所述的半导体装置，其特征在于还包含：
鳍状结构，设置在该基底内，且该二栅极横跨该鳍状结构。
11.一种半导体装置的制作工艺，其特征在于包含下列步骤：
在一基底上形成二栅极；
形成一间隙壁环绕各该栅极；
利用该间隙壁为一掩模，在该基底内形成一沟槽，该沟槽介于该二栅极之间；
在该沟槽形成后，部分移除该间隙壁以暴露该基底的一凸部的顶表面；以及
在该沟槽内形成一外延结构。
12.依据权利要求11所述的半导体装置的制作工艺，其特征在于，该基底的该凸部在一投影方向上延伸至该外延结构内。
13.依据权利要求11所述的半导体装置的制作工艺，其特征在于，该基底该凸部的该顶表面接触该外延结构。
14.依据权利要求11所述的半导体装置的制作工艺，其特征在于，该间隙壁包含第一间隙壁及第二间隙壁，该第二间隙壁是在部分移除该间隙壁时被移除。
15.依据权利要求14所述的半导体装置的制作工艺，其特征在于该间隙壁形成步骤包含：
在该基底上形成一第一材料层，覆盖各该栅极；
操作一第一蚀刻制作工艺，以形成该第一间隙壁；
在该基底上形成一第二材料层，覆盖各该栅极；以及
操作一第二蚀刻制作工艺，以形成该第二间隙壁。
16.依据权利要求15所述的半导体装置的制作工艺，其特征在于该第二材料层是在该第一间隙壁形成后形成。
17.依据权利要求14所述的半导体装置的制作工艺，其特征在于该沟槽形成步骤包含：
垂直蚀刻该基底以形成一初始沟槽，该初始沟槽与该第二间隙壁垂直切齐；
形成一材料层，覆盖该第二间隙壁、第一间隙壁及该二栅极；
形成一第三间隙壁，环绕该第二间隙壁及该第一间隙壁；以及
进一步蚀刻该初始沟槽以形成该沟槽。
18.依据权利要求17所述的半导体装置的制作工艺，其特征在于还包含：
该第三间隙壁是在部分移除该间隙壁时被移除。
19.依据权利要求17所述的半导体装置的制作工艺，其特征在于该第三间隙壁与该沟槽是同时形成。
20.依据权利要求11所述的半导体装置的制作工艺，其特征在于该外延结构的形成包含：
在该基底的该凸部及该沟槽的表面形成一第一外延层；以及
形成一第二外延层，填满该沟槽。
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