CN107039278A - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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- CN107039278A CN107039278A CN201611021412.9A CN201611021412A CN107039278A CN 107039278 A CN107039278 A CN 107039278A CN 201611021412 A CN201611021412 A CN 201611021412A CN 107039278 A CN107039278 A CN 107039278A
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Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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Abstract
本发明的实施例提供了一种形成半导体器件的方法,包括形成从衬底延伸的鳍。鳍具有源极/漏极(S/D)区和沟道区。鳍包括第一半导体层和第一半导体层上的第二半导体层。第一半导体层具有第一组分,且第二半导体层具有不同于第一组分的第二组分。该方法还包括从鳍的S/D区去除第一半导体层,从而使得第二半导体层的在S/D区中的第一部分悬置在间隔中。该方法还包括在S/D区中外延生长第三半导体层,第三半导体层围绕在第二半导体层的第一部分周围。本发明的实施例还提供了一种半导体器件。
Description
技术领域
本发明的实施例涉及半导体领域,更具体地涉及半导体器件及其形成方法。
背景技术
半导体集成电路(IC)产业经历了指数增长。IC材料和设计的技术进步产生了多个IC世代,其中,每个世代都具有比先前世代更小且更复杂的电路。在IC发展过程中,功能密度(即每芯片面积上互连器件的数量)通常增大了而几何尺寸(即,使用制造工艺可以做出的最小的元件(或线))减小了。这种规模缩小工艺通常也具增加产量效率和降低相关成本的益处。这种比例缩小却也增加了处理和制造IC的复杂程度,并且为了实现这些进步,需要在IC处理和制造中有类似的发展。
例如,已经引入多栅极(multi-gate)器件以通过增加栅极-沟道耦合,致力于提高栅极控制以减小截止电流和降低短沟道效应(SCE)。一种这样的多栅极器件是水平全环栅(HGAA)晶体管,其栅极结构在提供栅极控制于水平沟道区周围延伸,以允许它们在元件积极地按比例缩小的同时保持栅极控制和缓解SCE。HGAA晶体管与传统的互补金属氧化物半导体(CMOS)工艺兼容,然而,HGAA晶体管的制造可能存在挑战。例如,现有用于HGAA晶体管的源极和漏极(S/D)形成的方法不能在各个方面满足需求,尤其是当器件间距较小时,诸如40纳米(nm)或更小。
发明内容
本发明的实施例提供了一种形成半导体器件的方法,所述方法包括:形成从衬底延伸的鳍,所述鳍具有源极/漏极区和沟道区,其中,所述鳍包括第一半导体层和所述第一半导体层上的第二半导体层,所述第一半导体层具有第一组分,以及所述第二半导体层具有与所述第一组分不同的第二组分;从所述鳍的所述源极/漏极区去除所述第一半导体层,从而使得所述第二半导体层的在所述源极/漏极区中的第一部分悬置在间隔中;以及在所述源极/漏极区中外延生长第三半导体层,所述第三半导体层围绕在所述第二半导体层的所述第一部分周围。
本发明的实施例还提供了一种形成半导体器件的方法,所述方法包括:形成从衬底延伸的鳍,所述鳍具有多个第一半导体层和多个第二半导体层,所述第一半导体层和所述第二半导体层交替堆叠;在所述鳍的沟道区上方形成伪栅极堆叠件;从所述鳍的源极/漏极区去除所述第一半导体层的部分,从而使得所述第二半导体层的在所述源极/漏极区中的第一部分悬置在各自间隔中;在所述源极/漏极区中外延生长第三半导体层,其中,所述第三半导体层围绕在所述第二半导体层的所述第一部分的每个的周围;去除所述伪栅极堆叠件,从而暴露所述鳍的所述沟道区;从所述鳍的所述沟道区去除所述第一半导体层的部分,从而使得所述第二半导体层的在所述沟道区中的第二部分悬置在各自间隔中;以及在所述鳍的所述沟道区上方形成栅极堆叠件,其中,所述栅极堆叠件围绕在所述第二半导体层的所述第二部分的每个的周围。
本发明的实施例还提供了一种半导体器件,包括:衬底;鳍元件,从所述衬底延伸,其中:所述鳍元件包括沟道区以及所述沟道区的相对侧上的两个源极和漏极区,所述沟道区包括彼此间隔开的沟道半导体层,和所述源极和漏极区的每个都包括彼此间隔开的第一半导体层以及围绕在所述第一半导体层的每个的周围的第二半导体层;以及栅极堆叠件,设置在所述鳍元件的所述沟道区上方并且围绕所述沟道半导体层的每个。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或缩小。
图1A和图1B是根据本发明的各个实施例的形成半导体器件的方法的流程图。
图2是根据图1A和图1B中方法的实施例的在制造的中间阶段中的半导体器件的部分的立体图。
图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A和图12A是根据一些实施例的图2的半导体器件的部分的沿图2的“A—A”线的截面图。
图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B、图11B和图12B是根据一些实施例的图2的半导体器件的部分的沿图2的“B—B”线的截面图。
图3C、图4C、图5C、图6C、图7C、图8C、图9C、图10C、图11C和图12C是根据一些实施例的图2的半导体器件的部分的沿图2的“C—C”线的截面图。
图8D、图8E、图8F、和图8G示出了根据本发明的各个实施例的半导体器件的一些源极和漏极部件。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以便于描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而在此使用的空间相对描述符可以同样地作相应的解释。
本发明通常涉及半导体器件及其形成方法。更具体地,本发明涉及全环栅(GAA)器件。GAA器件包括具有在沟道区(例如,围绕沟道区的部分)的四边上形成的它的栅极结构或其部分的任何器件。GAA器件的沟道区可以包括纳米线沟道、条形沟道和/或其他合适的沟道配置。在实施例中,GAA器件的沟道区可具有垂直分隔开的多个水平纳米线或水平条,使GAA器件为堆叠的水平GAA(S-HGAA)器件。在本文中出现的GAA器件可以包括p型金属氧化物半导体GAA器件或n型金属氧化物半导体GAA器件。此外,GAA器件可以具有与单一、连续的栅极结构或多栅极结构相关联的一个或多个沟道区(例如,纳米线)。受益于本发明的各方面,本领域普通技术人员可以认识到半导体器件的其他实例。
图1A和图1B示出了根据本发明的各个实施例的形成半导体器件100的方法10的流程图。方法10仅为实例,并且不旨在限制本发明超出权利要求中明确列举的那些。可以在方法10之前、期间和之后提供附加的操作,并且对于方法的附加的实施例,可以代替、消除或移动描述的一些操作。结合图2至图12C在下面描述方法10。图2是制造的中间阶段中的半导体器件100的部分的立体图。图3A至图12A、图3B至图12B和图3C至图12C是分别沿图2的“A—A”线、“B—B”线和“C—C”线截取的半导体器件100在制造工艺的各个阶段中的截面图。
为说明目的提供半导体器件100且不必要限制本发明的实施例为任意数量的器件、任意数量的区域、或任意配置的结构或区域。此外,如图2至图12C所示的半导体器件100可为在IC的加工期间制造的中间器件或其部分,其可包括静态随机存取存储器(SRAM)和/或逻辑电路、诸如电阻器、电容器和电感器的无源组件以及诸如p型场效应晶体管(PFET)、n型FET(NFET)、诸如FinFET的多鳍FET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他存储单元及其组合的有源组件。
在操作12中,方法10(图1A)形成从衬底102延伸的一个或多个鳍104且每个鳍104都包括半导体层108和半导体层110的堆叠件。参照图2,在本实施例中,器件100包括两个鳍104,且每个鳍104都包括两个半导体层108和两个半导体层110。两个鳍104沿着“y”方向纵向定向且沿着“x”方向并排地布置。鳍104的下部部分由隔离结构106分隔开。半导体层108和半导体层110以交替的方式(例如,第一层110设置在第一层108上方,第二层108设置在第一层110上方,以及第二层110设置在第二层108上方等)垂直地堆叠(沿着“z”方向)。在各个实施例中,器件100可以包括任何数量的鳍104且鳍104可以包括任何数量的可选堆叠的半导体层108和半导体层110。
仍然参照图2,鳍104每个都包括两个源极/漏极(S/D)区104a和两个S/D区104a之间的沟道区104b。“A—A”线是跨S/D区104a中的一个截取的,“B—B”线是跨沟道区104b截取的,以及“C—C”线是跨鳍104中的一个纵向截取的。共同地参照图2、3A、3B和3C进行下面的讨论。
在实施例中,衬底102可以是诸如硅衬底的半导体衬底。衬底102可以包括各种层,包括形成在半导体衬底上的导电或绝缘层。衬底102可包括各种掺杂配置。例如,可以在为不同器件类型(例如,n型场效应晶体管(NFET)、p型场效应晶体管(PFET))设计的区域中的衬底102上形成不同的掺杂轮廓(例如,n阱、p阱)。衬底102还可以包括其他的半导体,诸如锗、碳化硅(SiC)、硅锗(SiGe)或金刚石。可选地,衬底102可以包括化合物半导体和/或合金半导体。此外,衬底102可以可选地包括外延层,可以被应变以增强性能,可以包括绝缘体上硅结构和/或具有其他合适的增强部件。
两个鳍104由间隔S(图3A和图3B)(沿着“x”方向)间隔。在实施例中,间隔S设计为小于50nm,诸如在从约10nm至约30nm的范围内,以用于严格的器件集成。隔离结构106可以由氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃、低k介电材料和/或其他合适的绝缘材料形成。隔离结构106可以是浅沟槽隔离(STI)部件。
半导体层108和半导体层110可以具有不同的厚度。半导体层108彼此可以具有不同的厚度。半导体层110彼此可以具有不同的厚度。半导体层108和半导体层110的每个的厚度的范围可以从几纳米至几十纳米。108的第一层(部分地掩埋在隔离结构106中)可以比其它的半导体层108和半导体层110厚得多。在实施例中,在隔离结构106之上延伸的每个半导体层108都具有从约5nm至约20nm的范围内的厚度,且每个半导体层110都具有从约5nm至约20nm的范围内的厚度。
两个半导体层108和110可以具有不同的成分。在各个实施例中,两个半导体层108和110提供不同的氧化速率和/或不同的蚀刻选择性。在实施例中,半导体层108包括硅锗(SiGe),且半导体层110包括硅(Si)。为了进一步进行本实施例,Si层110可以是未掺杂的或基本不含掺杂剂(即,具有从约0cm-3至约1x1017cm-3的非本征掺杂剂浓度),其中,例如,当形成Si层110时,不实施故意掺杂。可选地,Si层110可以被故意地掺杂。例如,Si层110可以掺杂有诸如用于p型沟道的硼(B)、铝(Al)、铟(In)、镓(Ga)的p型掺杂剂,或诸如用于形成n型沟道的磷(P)、砷(As)、锑(Sb)的n型掺杂剂。此外,SiGe层108按照摩尔比可以包括大于25%的Ge。例如,Ge按照摩尔比可以包括SiGe层108的约25%至50%。此外,半导体层108可以包括它们中的不同组分,且半导体层110可以包括它们中的不同组分。
在各个实施例中,半导体层108或半导体层110可以包括:诸如锗的其他材料;化合物半导体,诸如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,诸如GaAsP、AlInAs、AlGaAs、InGaAs、GaInP和/或GaInAsP或它们的组合。可以根据提供不同氧化速率和/或蚀刻选择性选择半导体层108和半导体层110的材料。如上所述,半导体层108或半导体层110可以掺杂的或未掺杂。
操作12可以包括诸如沉积、外延、光刻和蚀刻的各种工艺。此外,操作12可以以不同的顺序形成隔离结构106和鳍104。在实施例中,操作12在其形成鳍104之前形成隔离结构106(先隔离方案)。在另一实施例中,操作12在其形成隔离结构106之前形成鳍104(先鳍方案)。在下面通过实例进一步讨论这两个实施例。
在先隔离方案中,首先,操作12通过光刻工艺在衬底102上方形成掩蔽元件。光刻工艺可以包括:在衬底102上方形成光刻胶(或抗蚀剂),将光刻胶曝光成限定各种几何形状的图案,实施曝光后烘烤工艺,以及显影光刻胶以形成掩蔽元件。
随后地,操作12穿过掩蔽元件蚀刻衬底102以在其中形成第一沟槽。蚀刻工艺可以包括一个或多个干蚀刻工艺、湿蚀刻、和其他合适的蚀刻技术。例如,干蚀刻工艺可实施含氧气体、含氟气体(例如,CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如,HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。例如,湿蚀刻工艺可包括在以下蚀刻剂中的蚀刻:稀释的氢氟酸(DHF);氢氧化钾(KOH)溶液;氨水;包含氢氟酸(HF)、硝酸(HNO3)和/或醋酸(CH3COOH)的溶液;或其他合适的湿蚀刻剂。一次或多次蚀刻工艺在衬底102中形成第一沟槽。
随后地,操作12用诸如氧化硅的介电材料填充第一沟槽且实施化学机械抛光(CMP)工艺以平坦化介电材料和衬底102的顶面。可以通过化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、物理汽相沉积(PVD)、热氧化、或其它技术形成介电材料。该介电材料层称为隔离衬底102的各个部分的介电层106。
接下来,操作12蚀刻衬底102而介电层106通过选择性蚀刻工艺基本上保持不变,从而在介电层106的各个部分之间形成第二沟槽。第二沟槽被蚀刻至期望的深度以用于在其中生长鳍104。蚀刻工艺可以干蚀刻工艺、湿蚀刻工艺或另一合适的蚀刻技术。
随后地,操作12在第二沟槽中外延地生长半导体层108和半导体层110。例如,半导体层108和半导体层110的每个可以通过分子束外延(MBE)工艺、诸如金属有机CVD(MOCVD)工艺的化学汽相沉积(CVD)工艺、和/或其它合适的外延生长工艺生长。在一些实施例中,诸如层108的外延生长层包括与衬底102相同的材料。在一些实施例中,外延生长层108和外延生长层110包括与衬底102不同的材料。此外,已经在上面讨论了层108和110的材料的实施例。可以实施化学机械抛光(CMP)工艺以平坦化器件100的顶面。
随后地,如图2和图3A至图3C所示,操作12开槽介电层106以提供在介电层106的顶面106'之上延伸的鳍104。在一些实施例中,控制开槽深度(例如,通过控制蚀刻时间),从而获得鳍104的暴露的上部的期望的高度。介电层106的剩余部分成为隔离结构106。
在先鳍方案中,操作12可以包括如上所述的基本上相同或相似的工艺,尽管以不同的顺序。因此,简短地描述。首先,操作12在衬底102上方外延生长半导体层。然后,操作12通过光刻工艺在半导体层上方形成掩蔽元件。随后地,操作12通过掩蔽元件蚀刻半导体层以在其中形成沟槽。半导体层的剩余部分变成包括半导体层108和半导体层110的鳍104。随后地,操作12沉积诸如氧化硅的介电材料至沟槽内。可以实施化学机械抛光(CMP)工艺以平坦化器件100的顶面。此后,开槽介电材料以形成隔离结构106。
在操作14处,方法10(图1A)在鳍104和隔离结构106上方形成栅极堆叠件111。在本实施例中,在稍后栅极替换工艺中将去除栅极堆叠件111。因此,其称为伪栅极堆叠件111。参照图4A至图4C,伪栅极堆叠件111在沟道区104b处接合鳍104。伪栅极堆叠件111可以包括材料的单层或多层。在本实施例中,伪栅极堆叠件111包括多晶体硅(或多晶硅)层112、介电蚀刻停止(或CMP停止)层114以及介电硬掩模层116。在实施例中,伪栅极堆叠件111还包括多晶硅层112下面的界面层(例如,氧化硅)。蚀刻停止层114可以包括氧化硅、氮化硅、氮氧化硅或其他介电材料。硬掩模层116可以包括诸如氧化硅和/或氮化硅的一种或多种材料层。可以通过诸如低压化学汽相沉积(LPCVD)和PECVD的合适的沉积工艺形成多晶硅层112。蚀刻停止层114和硬掩模层116可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD、和/或其他合适的方法形成。在实施例中,伪栅极堆叠件111的各个层首先可以沉积为毯式层,并且然后通过一种或多种光刻和蚀刻工艺图案化以形成伪栅极堆叠件111。
在操作16处,方法10(图1A)在伪栅极堆叠件111的侧壁上形成栅极间隔件118。在实施例中,操作16包括分别在图5A至图5C和图6A至图6C中示出的沉积工艺和蚀刻工艺。参照图5A至图5C,在器件100上方沉积间隔件层118,覆盖其上的各种部件。间隔件层118可以包括诸如氮化硅、氧化硅、碳化硅、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN)、其它材料、或它们的组合的一种或多种介电材料。间隔件层118可以包括单层或多层结构。在本实施例中,间隔件层118具有几纳米的厚度。可以通过化学氧化、热氧化、ALD、CVD、和/或其它合适的方法形成间隔件层118。参照图6A至图6C,通过各向异性蚀刻工艺蚀刻间隔件层118以从伪栅极堆叠件111的顶面以及从鳍104的顶面和侧壁表面去除间隔件层118的部分。间隔件层118的位于伪栅极堆叠件111的侧壁表面上的部分基本保留且变成栅极间隔件118。在实施例中,各向异性蚀刻工艺是干(例如,等离子体)蚀刻工艺。
在操作18处,方法10(图1A)从S/D区104a去除半导体层108或其部分以形成间隔120。参照图7A至图7C,稍微地蚀刻或不蚀刻半导体层108的被伪栅极堆叠件111覆盖或掩埋在隔离结构106中的部分。此外,通过操作18稍微蚀刻或不蚀刻半导体层110。结果,S/D区104a中的半导体层110的部分变成悬置在间隔120中(见图7A和图7C)。在下面的讨论中,半导体层110的悬置在间隔120中的部分也称为S/D半导体层110。
在实施例中,通过调节选择性湿蚀刻工艺来蚀刻半导体层108以去除半导体层108而半导体层110基本上保持不变。在一些实施例中,选择性湿蚀刻工艺可以包括氢氟酸(HF)或NH4OH蚀刻剂。在半导体层108包括SiGe和半导体层110包括Si的实施例中,SiGe层108的选择性去除可以包括SiGe氧化工艺和接下来的SiGeOx去除。例如,SiGe氧化工艺可以包括形成和图案化各个掩蔽层,从而对SiGe层108控制氧化。在其它实施例中,由于半导体层108和半导体层110的组分不同,SiGe氧化工艺是选择性氧化。在一些实例中,可以通过将器件100暴露于湿氧化工艺、干氧化工艺或它们的组合来实施SiGe氧化工艺。之后,包括SiGeOx的被氧化的半导体层108通过诸如NH4OH或稀释的HF的蚀刻剂去除。
在各个实施例中,半导体层108和半导体层110提供能够通过操作18选择性去除半导体层108的不同的氧化速率和/或不同的蚀刻选择性。在实施例中,通过操作108稍微蚀刻半导体层110以在S/D区104a中获得期望的尺寸和形状。例如,所得到的S/D半导体层110可具有条状形(如图7A和图7C中示出)、棒状形(未示出)或其它形状。
在操作20处,方法10(图1A)在S/D区104a中外延生长半导体层122。参照图8A至图8C,半导体层122围绕在S/D半导体层110的每个周围且直接接触其所有四个边上的S/D半导体层110。在图8A中示出的实施例中,半导体层122和半导体层110共同地形成竖直的(沿“z”方向)条形形状。在如图8D中所示的另一实施例中,半导体层122可包括多个部分且每个部分都围绕在相应的S/D半导体层110周围。此外,半导体层122的每个部分可以具有菱形或另一形状。在如图8E所示的另一实施例中,半导体层122的多个部分可以合并成一个大工件。在一些实施例中,半导体层122的宽度(沿着“x”方向)在从约几纳米至约30nm的范围内。
在实施例中,半导体层122包括与S/D半导体层110相同的材料。例如,它们都包括硅。在可选实施例中,半导体层122和110可以包括不同材料或成分。在各个实施例中,半导体层122可以包括诸如硅或锗的半导体材料;诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟的化合物半导体;诸如GaAsP、AlInAs、AlGaAs、InGaAs、GaInP、和/或GaInAsP的合金半导体;或它们的组合。
在实施例中,通过分子束外延(MBE)工艺、化学汽相沉积工艺和/或其他合适的外延生长工艺来生长半导体层122。在又一实施例中,半导体层122原位掺杂或非原位掺杂有n型掺杂剂或p型掺杂剂。例如,在一些实施例中,半导体层122包括掺杂有用于形成PFET的S/D部件的硼的硅锗(SiGe)。在一些实施例中,半导体层122包括掺杂有用于形成NFET的S/D部件的磷的硅。进一步关于这些实施例,SiGe层122可以包括按照摩尔比在从约10%至约70%的范围内的Ge。在实施例中,半导体层122是高掺杂的从而形成与稍后在器件100中形成的S/D接触件金属的欧姆接触。
在本实施例中,半导体层122和半导体层110共同地用作器件100的S/D部件。在实施例中,半导体层122和半导体层110包括相同类型的掺杂剂(例如,均为n型掺杂或均为p型掺杂),但是在半导体层122中的掺杂剂浓度高于在S/D半导体层110中的掺杂剂浓度。在另一实施例中,半导体层122和半导体层110可以包括相同类型的掺杂剂,但是可具有不同掺杂剂物质。
本发明的实施例提供的益处好于形成HGAA器件的S/D部件的其它方法。在如图8F所示的方法中,在鳍204各自的S/D区中完全地蚀刻鳍204(与鳍104相类似)且半导体层206随后在各自的S/D区中生长作为用于HGAA器件200的S/D部件。由于在不同晶向处的生长速率不同,半导体层206的每个都具有菱形,这是半导体层206中的材料的固有的属性。因此,两个鳍204之间的最小间隔S1是有限的从而使得S/D部件206足够大同时防止邻近的S/D部件206合并在一起。相反地,本发明的实施例使用S/D半导体层110作为基础生长半导体层122(S/D部件),这限制了半导体层122的横向生长。这示出在具有其中鳍104包括五个S/D半导体层110的实施例的图8G中。参照图8G,在中间的外延生长阶段中,每个半导体层122'都生长远离各自的S/D半导体层110。半导体层122'的横向生长受到各自的S/D半导体层110的尺寸和形状的限制。随着半导体层122'生长,它们合并为具有垂直的条状形状的一个更大的半导体层122。半导体层122'的有限制的横向生长的结果,两个邻近的鳍104之间的最小间隔S2可以比S1更小,这有利地增加了半导体器件的集成。
在操作22处,方法10(图1B)在半导体层122和隔离结构106上方形成层间介电(ILD)层126。参照图9A至图9C,在本实施例中,在ILD层126的形成之前,在半导体层122和隔离结构106上方形成接触蚀刻停止(CES)层124。CES层124可以包括诸如氮化硅、氧化硅、氮氧化硅、和/或其他材料的介电材料。可以通过ALD、PECVD、或其它合适的沉积或氧化工艺形成CES层124。ILD层126可以包括诸如原硅酸四乙酯氧化物、未掺杂的硅酸盐玻璃、或掺杂的氧化硅(诸如硼磷硅硅酸盐玻璃、熔融石英玻璃、磷硅酸盐玻璃、硼掺杂的硅玻璃)、和/或其他合适的介电材料的材料。可以通过PECVD工艺、可流动CVD(FCVD)工艺或其它合适的沉积技术沉积ILD层126。在实施例中,在沉积CES层124和ILD层126之后,实施CMP工艺以平坦化器件100的顶面,这还去除了硬掩模层116和蚀刻停止层114(图8B和图8C)。结果,从器件100的顶面暴露多晶硅层112。
在操作24处,方法10(图1B)去除了伪栅极堆叠件111以暴露鳍104的沟道区104b。参照图10A至图10C,包括多晶硅层112和其下方的任何其它层的伪栅极堆叠件111(见图9B和图9C)被去除以形成开口128。在开口128中暴露出鳍104的沟道区104b。在实施例中,操作24包括一种或多种蚀刻工艺,诸如湿蚀刻、干蚀刻、或其它蚀刻技术。
在操作26处,方法10(图1B)通过开口128去除半导体层108的部分。参照图11A和图11C,去除在沟道区104b中的半导体层108或其部分。结果,沟道区104b中的半导体层110的部分悬置在开口128中。在下面的讨论中,半导体层110的悬置在开口128中的部分也称为沟道半导体层110。通过操作26稍微蚀刻或不蚀刻沟道半导体层110。在本实施例中,稍微蚀刻沟道半导体层110以形成棒状形状(例如,纳米线)(见图11B)。在各个实施例中,沟道半导体层110(图11B)和S/D半导体层110(图11A)可以具有相同或不同的截面轮廓。例如,它们中的任意一个或两个可以具有矩形、圆形、或“x-z”平面中的其它几何形状。
在实施例中,通过操作26的半导体层108的选择性去除可以使用参照操作18的上述相同的技术。在实施例中,氧化半导体层108的剩余部分被氧化以变成用于隔离目的的氧化物层108'。进一步关于本实施例,氧化工艺可以包括湿氧化工艺、干氧化工艺、或它们的组合。在一个实例中,使用水蒸气或蒸汽作为氧化剂暴露器件100于湿氧化工艺。在半导体层108包括硅锗的一个实例中,氧化物层108'包括硅或硅锗氧化物。
在操作28处,方法10(图1B)在鳍104的沟道区104b上方形成栅极堆叠件129。参照图12A和图12C,栅极堆叠件129填充开口128(图11B和图11C)且围绕在沟道半导体层110的每个(例如,纳米线)周围。在本实施例中,栅极堆叠件129包括可以由在开口128的内表面上且直接围绕在沟道半导体层110的每个上的一层或多层的介电材料组成的介电层130。栅极堆叠件129还包括可以由介电层130上方的一层或多层组成的栅极金属堆叠件132,并且金属填充层134位于栅极金属堆叠件132上方。如图12B所示,层130和层132围绕在每个沟道半导体层110(例如,纳米线)周围以形成其晶体管沟道。控制层130和层132的厚度从而来自邻近的晶体管沟道的层132彼此不接触。参照图12B和图12C,栅极堆叠件129围绕在垂直堆叠的横向取向的沟道半导体层110周围。因此,器件100是堆叠的水平全环栅(S-HGAA)器件。参照图12A,器件100的S/D区包括彼此间隔开的多个S/D半导体层110,并且还包括围绕在每个半导体层110周围的半导体层122。
在实施例中,介电层130可以包括诸如氧化硅层或氮氧化硅的介电材料并且可以通过化学氧化、热氧化、ALD、CVD和/或其它合适的方法形成。介电层130还可包括诸如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇、钛酸锶、其它合适的金属氧化物、或它们的组合的高k介电层;且可以通过ALD和/或其它合适的方法形成。在实施例中,栅极金属堆叠件132可包括功函数金属层。功函数金属层可以是p型功函数金属层或n型功函数金属层。p型功函数金属层包括选自但不限于氮化钛、氮化钽、钌、钼、钨、铂或者它们的组合的组的金属。n型功函数金属层包括选自但不限于钛、铝、碳化钽、碳氮化钽、氮硅化钽或它们的组合的组的金属。p型或n型功函数金属层可以包括多个层并且可以通过CVD、PVD和/或其他合适的工艺沉积。金属填充层134可以包括铝、钨、钴、铜、和/或其它合适的材料,并且可以由CVD、PVD、镀敷、和/或其它合适的工艺形成。在实施例中,在沉积各个层130、132和134之后,实施CMP工艺以平坦化器件100的顶面。
在操作30处,方法10(图1B)实施进一步处理以完成S-HGAA器件100的制造。例如,其可以在衬底102上方形成配置为连接各个部件以形成可以包括一个或多个多栅极器件的功能电路的接触开口、接触金属以及各种接触件、通孔、引线和多层互连部件(如,金属层和层间电介质)。更具体地,其可以形成贯穿ILD层126并且接触半导体层122的接触金属。
尽管不旨在限制,但本发明的一个或多个实施例提供了半导体器件及其形成工艺的许多益处。例如,本发明的实施例形成用于堆叠的水平全环栅(S-HGAA)器件的源极和漏极(S/D)部件。S/D部件可以被形成以具有较窄的轮廓以适应紧凑的鳍-鳍间隔。这有利地增加了用于S-HGAA器件的集成度。此外,本发明的实施例可以用于形成具有任何数量的堆叠的沟道的S-HGAA器件,以提供更大的灵活性和可缩放性。进一步地,本发明的实施例可以被集成至现有的CMOS制造流程中,以提供改善的工艺窗口。
在一个示例性实施例中,本发明涉及一种形成半导体器件的方法。该方法包括形成从衬底延伸的鳍。鳍具有源极/漏极(S/D)区和沟道区。鳍包括第一半导体层和第一半导体层上的第二半导体层。第一半导体层具有第一组分,且第二半导体层具有不同于第一组分和第二组分。该方法还包括从鳍的S/D区去除第一半导体层,从而第二半导体层的在S/D区中的第一部分悬置在间隔中。该方法还包括在S/D区中外延生长第三半导体层,第三半导体层围绕在第二半导体层的第一部分周围。
在另一示例性实施例中,本发明涉及一种形成半导体器件的方法。该方法包括形成从衬底延伸的鳍。鳍包括多个第一半导体层和多个第二半导体层,其中,第一半导体层和第二半导体层交替堆叠。该方法还包括在鳍的沟道区上方形成伪栅极堆叠件,并且从鳍的S/D区去除第一半导体层的部分,从而第二半导体层的在S/D区中的第一部分的每个都在各自的间隔中悬置。该方法还包括在S/D区中外延生长第三半导体层,其中,第三半导体层围绕在第二半导体层的第一部分的每个的周围。该方法还包括去除伪栅极堆叠件,从而暴露鳍的沟道区。该方法还包括从鳍的沟道区去除第一半导体层的部分,从而第二半导体层的在沟道区中的第二部分的每个都悬置在各自间隔中。该方法还包括在鳍的沟道区上方形成栅极堆叠件,其中,栅极堆叠件围绕在第二半导体层的第二部分的每个的周围。
在又一示例性实施例中,本发明涉及一种半导体器件。半导体器件包括衬底和从衬底延伸的鳍元件。鳍元件包括沟道区以及在沟道区的相对两侧上的两个源极和漏极(S/D)区。沟道区包括彼此间隔开的沟道半导体层。S/D区的每个都包括彼此间隔开的第一半导体层和围绕在第一半导体层的每个的周围的第二半导体层。该半导体器件还包括设置在鳍元件的沟道区上方且围绕每个沟道半导体层的栅极堆叠件。
本发明的实施例提供了一种形成半导体器件的方法,所述方法包括:形成从衬底延伸的鳍,所述鳍具有源极/漏极区和沟道区,其中,所述鳍包括第一半导体层和所述第一半导体层上的第二半导体层,所述第一半导体层具有第一组分,以及所述第二半导体层具有与所述第一组分不同的第二组分;从所述鳍的所述源极/漏极区去除所述第一半导体层,从而使得所述第二半导体层的在所述源极/漏极区中的第一部分悬置在间隔中;以及在所述源极/漏极区中外延生长第三半导体层,所述第三半导体层围绕在所述第二半导体层的所述第一部分周围。
根据本发明的一个实施例,其中,所述第三半导体层掺杂有比所述第二半导体层更高的掺杂剂浓度。
根据本发明的一个实施例,其中,所述第二半导体层和所述第三半导体层的每个都包括硅。
根据本发明的一个实施例,方法还包括:从所述鳍的所述沟道区去除所述第一半导体层,从而使得所述第二半导体层的第二部分悬置在间隔中;以及在所述鳍的所述沟道区上方形成栅极堆叠件,其中,所述栅极堆叠件的部分围绕在所述第二半导体层的所述第二部分周围。
根据本发明的一个实施例,其中,所述第二半导体层的所述第一部分和所述第二部分具有不同的截面轮廓。
根据本发明的一个实施例,方法还包括:在从所述鳍的所述源极/漏极区去除所述第一半导体层之前,形成覆盖所述鳍的所述沟道区的伪栅极堆叠件。
根据本发明的一个实施例,方法还包括:在外延生长所述第三半导体层之后,在所述第三半导体层上方形成层间介电层;去除所述伪栅极堆叠件以暴露所述鳍的所述沟道区;从所述鳍的所述沟道区去除所述第一半导体层,从而使得所述第二半导体层的第二部分悬置在间隔中;以及在所述鳍的所述沟道区上方形成栅极堆叠件,其中,所述栅极堆叠件的部分围绕在所述第二半导体层的所述第二部分周围。
根据本发明的一个实施例,其中,所述第一半导体层包括硅锗并且所述第二半导体层包括硅。
根据本发明的一个实施例,其中,所述第二半导体层的所述第一部分和所述第三半导体层共同地形成垂直的条状形状。
本发明的实施例还提供了一种形成半导体器件的方法,所述方法包括:形成从衬底延伸的鳍,所述鳍具有多个第一半导体层和多个第二半导体层,所述第一半导体层和所述第二半导体层交替堆叠;在所述鳍的沟道区上方形成伪栅极堆叠件;从所述鳍的源极/漏极区去除所述第一半导体层的部分,从而使得所述第二半导体层的在所述源极/漏极区中的第一部分悬置在各自间隔中;在所述源极/漏极区中外延生长第三半导体层,其中,所述第三半导体层围绕在所述第二半导体层的所述第一部分的每个的周围;去除所述伪栅极堆叠件,从而暴露所述鳍的所述沟道区;从所述鳍的所述沟道区去除所述第一半导体层的部分,从而使得所述第二半导体层的在所述沟道区中的第二部分悬置在各自间隔中;以及在所述鳍的所述沟道区上方形成栅极堆叠件,其中,所述栅极堆叠件围绕在所述第二半导体层的所述第二部分的每个的周围。
根据本发明的一个实施例,方法还包括:在去除所述伪栅极堆叠件之前,在所述第三半导体层上方形成层间介电层。
根据本发明的一个实施例,其中,所述第一半导体层的每个都包括硅锗,并且所述第二半导体层的每个都包括硅。
根据本发明的一个实施例,方法还包括:在从所述鳍的所述源极/漏极区去除所述第一半导体层的所述部分之前,在所述伪栅极堆叠件的侧壁上形成栅极间隔件。
根据本发明的一个实施例,其中,所述第三半导体层具有比所述第二半导体层的所述第一部分的每个更高的掺杂剂浓度。
根据本发明的一个实施例,其中,从所述鳍的所述源极/漏极区去除所述第一半导体层的所述部分包括:调节的蚀刻工艺以选择性地去除所述第一半导体层的所述部分,而所述第二半导体层的在所述源极/漏极区中的所述第一部分保持不变。
本发明的实施例还提供了一种半导体器件,包括:衬底;鳍元件,从所述衬底延伸,其中:所述鳍元件包括沟道区以及所述沟道区的相对侧上的两个源极和漏极区,所述沟道区包括彼此间隔开的沟道半导体层,和所述源极和漏极区的每个都包括彼此间隔开的第一半导体层以及围绕在所述第一半导体层的每个的周围的第二半导体层;以及栅极堆叠件,设置在所述鳍元件的所述沟道区上方并且围绕所述沟道半导体层的每个。
根据本发明的一个实施例,其中:所述第一半导体层的每个都包括第一半导体材料并且不含掺杂剂;以及所述第二半导体层包括所述第一半导体材料并且掺杂有n型掺杂剂和p型掺杂剂中的一种。
根据本发明的一个实施例,其中:所述第二半导体层和所述第一半导体层掺杂有相同类型的掺杂剂;以及所述第二半导体层具有比所述第一半导体层的每个更高的掺杂剂浓度。
根据本发明的一个实施例,其中,所述第二半导体层和所述第一半导体层掺杂有不同的掺杂剂物质。
根据本发明的一个实施例,其中,所述鳍元件的所述源极和漏极区的每个都具有垂直的条状形状。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的实施例。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成半导体器件的方法,所述方法包括:
形成从衬底延伸的鳍,所述鳍具有源极/漏极区和沟道区,其中,所述鳍包括第一半导体层和所述第一半导体层上的第二半导体层,所述第一半导体层具有第一组分,以及所述第二半导体层具有与所述第一组分不同的第二组分;
从所述鳍的所述源极/漏极区去除所述第一半导体层,从而使得所述第二半导体层在所述源极/漏极区中的第一部分悬置在间隔中;以及
在所述源极/漏极区中外延生长第三半导体层,所述第三半导体层围绕在所述第二半导体层的所述第一部分周围。
2.根据权利要求1所述的方法,其中,所述第三半导体层掺杂有比所述第二半导体层更高的掺杂剂浓度。
3.根据权利要求2所述的方法,其中,所述第二半导体层和所述第三半导体层的每个都包括硅。
4.根据权利要求1所述的方法,还包括:
从所述鳍的所述沟道区去除所述第一半导体层,从而使得所述第二半导体层的第二部分悬置在间隔中;以及
在所述鳍的所述沟道区上方形成栅极堆叠件,其中,所述栅极堆叠件的部分围绕在所述第二半导体层的所述第二部分周围。
5.根据权利要求4所述的方法,其中,所述第二半导体层的所述第一部分和所述第二部分具有不同的截面轮廓。
6.根据权利要求1所述的方法,还包括:在从所述鳍的所述源极/漏极区去除所述第一半导体层之前,
形成覆盖所述鳍的所述沟道区的伪栅极堆叠件。
7.根据权利要求6所述的方法,还包括:在外延生长所述第三半导体层之后,
在所述第三半导体层上方形成层间介电层;
去除所述伪栅极堆叠件以暴露所述鳍的所述沟道区;
从所述鳍的所述沟道区去除所述第一半导体层,从而使得所述第二半导体层的第二部分悬置在间隔中;以及
在所述鳍的所述沟道区上方形成栅极堆叠件,其中,所述栅极堆叠件的部分围绕在所述第二半导体层的所述第二部分周围。
8.根据权利要求1所述的方法,其中,所述第一半导体层包括硅锗并且所述第二半导体层包括硅。
9.一种形成半导体器件的方法,所述方法包括:
形成从衬底延伸的鳍,所述鳍具有多个第一半导体层和多个第二半导体层,所述第一半导体层和所述第二半导体层交替堆叠;
在所述鳍的沟道区上方形成伪栅极堆叠件;
从所述鳍的源极/漏极区去除所述第一半导体层的部分,从而使得所述第二半导体层的在所述源极/漏极区中的第一部分悬置在各自间隔中;
在所述源极/漏极区中外延生长第三半导体层,其中,所述第三半导体层围绕在所述第二半导体层的所述第一部分的每个的周围;
去除所述伪栅极堆叠件,从而暴露所述鳍的所述沟道区;
从所述鳍的所述沟道区去除所述第一半导体层的部分,从而使得所述第二半导体层的在所述沟道区中的第二部分悬置在各自间隔中;以及
在所述鳍的所述沟道区上方形成栅极堆叠件,其中,所述栅极堆叠件围绕在所述第二半导体层的所述第二部分的每个的周围。
10.一种半导体器件,包括:
衬底;
鳍元件,从所述衬底延伸,其中:
所述鳍元件包括沟道区以及所述沟道区的相对侧上的两个源极和漏极区,
所述沟道区包括彼此间隔开的沟道半导体层,和
所述源极和漏极区的每个都包括彼此间隔开的第一半导体层以及围绕在所述第一半导体层的每个的周围的第二半导体层;以及
栅极堆叠件,设置在所述鳍元件的所述沟道区上方并且围绕所述沟道半导体层的每个。
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US20200365712A1 (en) | 2020-11-19 |
US10109721B2 (en) | 2018-10-23 |
CN107039278B (zh) | 2020-05-22 |
TWI623061B (zh) | 2018-05-01 |
US20170140996A1 (en) | 2017-05-18 |
US9754840B2 (en) | 2017-09-05 |
US11239341B2 (en) | 2022-02-01 |
US20190051734A1 (en) | 2019-02-14 |
US10734500B2 (en) | 2020-08-04 |
TW201729348A (zh) | 2017-08-16 |
US20170358500A1 (en) | 2017-12-14 |
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