CN108122774A - 用于全环栅半导体结构的阈值电压调整 - Google Patents

用于全环栅半导体结构的阈值电压调整 Download PDF

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CN108122774A
CN108122774A CN201710950405.5A CN201710950405A CN108122774A CN 108122774 A CN108122774 A CN 108122774A CN 201710950405 A CN201710950405 A CN 201710950405A CN 108122774 A CN108122774 A CN 108122774A
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semiconductor layer
semiconductor
layer
etch process
gate
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CN108122774B (zh
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江宏礼
黄思维
魏焕昇
何炯煦
叶致锴
谢文兴
吴忠政
杨育佳
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Electrodes Of Semiconductors (AREA)

Abstract

半导体结构包括与多个第二半导体层交错的多个第一半导体层。第一半导体层和第二半导体层具有不同的材料组分。在最上第一半导体层上方形成伪栅极堆叠件。实施第一蚀刻工艺以去除未设置在伪栅极堆叠件下面的第二半导体层的部分，从而形成多个空隙。第一蚀刻工艺在第一半导体层和第二半导体层之间具有蚀刻选择性。之后，实施第二蚀刻工艺以扩大空隙。本发明的实施例还涉及用于全环栅半导体结构的阈值电压调整。

Description

用于全环栅半导体结构的阈值电压调整
技术领域
本发明的实施例涉及用于全环栅半导体结构的阈值电压调整。
背景技术
半导体集成电路(IC)工业已经经历了指数增长。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代都比上一代具有更小和更复杂的电路。在IC演化过程中，功能密度(即，每芯片面积的互连器件的数量)已经普遍增大，而几何尺寸(即，可以使用制造工艺产生的最小组件(或线))已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小已经增加了处理和制造IC的复杂性，为了实现这些进步，需要IC处理和制造中的类似发展。
例如，已经引入多栅极器件以通过增加栅极-沟道耦合致力于改进栅极控制、减小截止电流和降低短沟道效应(SCE)。一种这样的多栅极器件是水平全环栅(HGAA)晶体管，它的栅极结构围绕它的水平沟道区域延伸，提供从所有侧进入沟道区域。HGAA晶体管与传统的互补金属氧化物半导体(CMOS)工艺兼容，允许它们在保持栅极控制和缓解SCE的同时急剧地按比例缩小。然而，由于诸如较小的耗尽区域和较小的沟道体积以及由重掺杂引起的迁移率降低的问题，因此传统的HGAA器件难以控制它的阈值电压(Vt)。
因此，虽然传统的HGAA器件对于它们的预期目的通常已经足够，但是它们不是在所有方面都已令人满意。
发明内容
本发明的实施例提供了一种形成半导体器件的方法，包括：提供半导体结构，所述半导体结构包括与多个第二半导体层交错的多个第一半导体层，所述第一半导体层和所述第二半导体层具有不同的材料组分；在最上第一半导体层上方形成伪栅极堆叠件；实施第一蚀刻工艺以去除未设置在所述伪栅极堆叠件下面的所述第二半导体层的部分，从而形成多个空隙，其中，所述第一蚀刻工艺在所述第一半导体层和所述第二半导体层之间具有蚀刻选择性；以及实施第二蚀刻工艺以扩大所述空隙。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：提供半导体结构，所述半导体结构包括多个第一半导体层和多个第二半导体层，所述第一半导体层和所述第二半导体层具有不同的材料组分并且在垂直方向上彼此交替设置；在最上第一半导体层上方形成多个伪栅极堆叠件；去除所述半导体结构的第一区域中的所述第二半导体层的部分，从而在所述第一区域中的所述第二半导体层的去除部分的位置形成多个第一间隔；经由横向蚀刻工艺水平地延伸所述第一间隔；以及之后，去除所述半导体结构的第二区域中的所述第二半导体层的部分，从而在所述第二区域中的所述第二半导体层的去除部分的位置形成多个第二间隔，其中，所述第一区域中的所述第二半导体层的剩余部分与所述第二区域中的所述第二半导体层的剩余部分具有不同的水平尺寸。
本发明的又一实施例提供了一种半导体结构，包括：多个纳米线，每个均在第一方向上延伸，其中，所述纳米线在垂直于所述第一方向的第二方向上彼此堆叠；以及多个第一栅极结构和第二栅极结构，每个均包裹所述纳米线的相应的一个纳米线，其中，所述第一栅极结构的每个均具有在所述第一方向上测量的第一尺寸，并且其中，所述第二栅极结构的每个均具有在所述第一方向上测量的第二尺寸，所述第一尺寸大于或小于所述第二尺寸。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图5A是根据本发明的各个方面的处于制造的各个阶段的半导体结构的截面侧视图。
图1B至图5B是根据本发明的各个方面的处于制造的各个阶段的半导体结构的截面侧视图。
图6至图11是根据本发明的各个方面的处于制造的各个阶段的半导体结构的截面侧视图。
图12是根据本发明的各个方面的示出制造半导体结构的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明通常涉及半导体器件及其形成方法。更具体地，本发明涉及全环栅(GAA)器件。GAA器件包括具有在沟道区域的四个侧上(例如，围绕沟道区域的部分)形成的栅极结构的任何器件或其部分。GAA器件的沟道区域可以包括纳米线沟道、条形沟道和/或其它合适的沟道配置。在实施例中，GAA器件的沟道区域可以具有垂直间隔开的多个水平纳米线或水平条，使GAA器件成为堆叠的水平GAA(S-HGAA)器件。本文呈现的GAA器件可以包括p型金属氧化物半导体GAA器件或n型金属氧化物半导体GAA器件。此外，GAA器件可以具有与单个连续的栅极结构或多个栅极结构相关的一个或多个沟道区域(例如，纳米线)。本领域技术人员可以意识到半导体器件的其它实例可能受益于本发明的方面。
图1A至图5A和图1B至图5B示出了根据本发明的实施例的处于制造的各个阶段的半导体器件100的不同的截面侧视图。具体地，图1A至图5A示出了沿着半导体结构100的Y方向截取的截面图，并且图1B至图5B示出了沿着半导体结构100的X方向截取的截面图，其中，Y方向与X方向正交或垂直。可以说，图1A至图5A示出了Y切割的半导体结构100，而图1B至图5B示出了X切割的半导体结构100。
在示出的实施例中，半导体结构100包括GAA器件(例如，HGAA器件)。GAA器件可以在IC或其部分的处理期间制造，IC或其部分可以包括静态随机存取存储器(SRAM)和/或逻辑电路、无源组件(诸如电阻器、电容器和电感器)以及有源组件(诸如p型场效应晶体管(PFET)、n型FET(NFET)、多栅极FET(诸如FinFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频率晶体管)、其它存储器单元以及它们的组合。
参照图1A至图1B，半导体结构100包括在Z方向上垂直向上突出的鳍式结构104(为了简单起见，在下文中称为“鳍”)，其中，Z方向与由Y方向和X方向限定的水平面正交。鳍104包括交替设置的半导体层108和110的堆叠件。
半导体层108和110是以交错或交替的方式(例如，层110设置在层108上方，之后另一层108设置在层110上方等等)垂直堆叠的(沿着“Z”方向)。在各个实施例中，结构100可以包括任何数量的鳍104，并且鳍104可以包括任何数量的交替堆叠的半导体层108和110。配置半导体层108和110的材料组分，从而使得它们可以在下面更详细地讨论的随后的蚀刻工艺中具有蚀刻选择性。例如，在一些实施例中，半导体层108包含硅(Si)，而半导体层110包含硅锗(SiGe)。在一些其它实施例中，半导体层108包含SiGe，而半导体层110包含Si。应该理解，虽然图1A示出了一个鳍104，但是半导体结构100可以包括与鳍104类似的多个其它的鳍。
如图1A所示，鳍104的下部由隔离结构106围绕。在一些实施例中，隔离结构106包括浅沟槽隔离(STI)。隔离结构106可以包含诸如氧化硅的电绝缘材料。同样如图1A所示，间隔件112和间隔件114也设置为围绕鳍结构104的底部，例如，围绕半导体层108的一个。间隔件可以包含合适的介电材料，例如，氮化硅、氧化硅、氮氧化硅或它们的组合。
在半导体层108的最上一个上方形成伪栅极堆叠件105。伪栅极堆叠件105包括介电层120。在一些实施例中，介电层120包含氧化硅。在其它实施例中，介电层120包含高k介电材料。高k介电材料是介电常数大于SiO2的介电常数(为约4)的材料。例如，高k栅极电介质包括氧化铪(HfO2)，其具有在从约18至约40的范围内的介电常数。如各个其它实例，高k栅极电介质可以包括ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO或SrTiO。伪栅极堆叠件105也包括在介电层120上方形成的多晶硅层130。伪栅极堆叠件105可以经受栅极置换工艺以形成高k金属栅极，如下面更详细地讨论的。
在介电层120和多晶硅层130的侧壁上形成栅极间隔件140。栅极间隔件140包含介电材料，例如，氮化硅、氧化硅、碳化硅、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN)、其它材料或它们的组合。栅极间隔件140可以包括单层或多层结构。在一些实施例中，栅极间隔件140具有几纳米(nm)的范围内的厚度。在一些实施例中，可以通过在伪栅极堆叠件105上方沉积间隔件层(包含介电材料)，随后是各向异性蚀刻工艺以从伪栅极堆叠件105的顶面去除间隔件层140的部分来形成栅极间隔件140。在蚀刻之后，间隔件层的部分基本保留在伪栅极堆叠件105的侧壁表面上并且变成栅极间隔件140。在一些实施例中，各向异性蚀刻工艺是干(例如，等离子体)蚀刻工艺。应该理解，栅极间隔件140的形成也可以涉及化学氧化、热氧化、ALD、CVD和/或其它合适的方法。栅极间隔件140以及伪栅极堆叠件105将用于帮助限定半导体结构100的沟道的物理和/或电长度。在一些实施例中，栅极间隔件140可以被认为是伪栅极堆叠件105的一部分，即使在下面讨论的栅极置换工艺中将不会去除栅极间隔件140。
开口150由邻近的间隔件140之间的间隔限定。开口150可以通过蚀刻工艺(蚀刻穿过栅极间隔件材料)形成并且暴露下面的导体层108。开口150的每个均具有在X方向上测量的水平尺寸160。同时，伪栅极堆叠件(例如，多晶硅层130)的每个均具有在X方向上测量的水平尺寸170，并且栅极间隔件140的每个均具有在X方向上测量的水平尺寸180。在一些实施例中，水平尺寸160在从约8nm至约12nm的范围内(例如，约10nm)，水平尺寸170在从约10nm至约14nm的范围内(例如，约12nm)，并且水平尺寸180在从约5nm至约8nm的范围内(例如，约6.5nm)。应该理解，尺寸170有助于限定HGAA晶体管的物理栅极长度。
现在参照图2A至图2B，对半导体结构100实施蚀刻工艺200。在蚀刻工艺200期间，间隔件140和伪栅极堆叠件105保护它们下面的层免受蚀刻。蚀刻工艺200选择性地去除半导体层110的与开口150垂直对准的部分，而留下基本未蚀刻的半导体层108。由于蚀刻工艺200，在半导体层110的蚀刻掉的部分的位置形成间隔或空隙210。最终将用外延生长的掺杂的半导体材料填充间隔/空隙210，使得它们可以用作HGAA晶体管的源极/漏极。这将在下面更详细地讨论。
仍参照图2B，间隔或空隙210的每个均具有基本等于水平尺寸160(限定每个开口150的宽度)的水平尺寸(在X方向上测量的)230。同时，半导体层110具有水平尺寸250。在一些实施例中，水平尺寸250在从约20nm和约30nm之间的范围内。
在一些实施例中，蚀刻工艺200可以包括选择性湿蚀刻工艺。选择性湿蚀刻工艺可以包括氢氟酸(HF)蚀刻剂或NH4OH蚀刻剂。在半导体层110包括SiGe并且半导体层108包括Si的实施例中，SiGe层110的选择性去除可以包括SiGe氧化工艺(以将SiGe转变为SiGeOx)以及随后的SiGeOx的去除。SiGe氧化工艺可以包括形成并且图案化各个掩模层，从而使得SiGe层110的氧化是可控的。在其它实施例中，由于半导体层110和108的不同的组分，因此，SiGe氧化工艺是选择性氧化。在一些实例中，可以通过将结构100暴露于湿氧化工艺、干氧化工艺或它们的组合来实施SiGe氧化工艺。之后，通过诸如NH4OH或稀释的HF的蚀刻剂来去除氧化的半导体层(包括SiGeOx)。在各个实施例中，半导体层110和108提供不同的氧化速率和/或不同的蚀刻选择性，这使得半导体层110能够通过蚀刻选择性去除。
现在参照图3A至图3B，在实施蚀刻工艺200之后，对半导体结构100实施横向蚀刻工艺300以横向地(例如，在X方向上水平地)蚀刻半导体层110。该横向蚀刻工艺300也可以称为邻近推进工艺。在一些实施例中，可以通过控制横向蚀刻工艺300的蚀刻时间来配置横向蚀刻的程度(或蚀刻掉的半导体层110的量)。在一些实施例中，蚀刻工艺300是各向同性蚀刻工艺。在一些实施例中，使用具有低垂直偏置电压(例如，＜0.1伏)或没有垂直偏置电压的湿蚀刻或干蚀刻来实施蚀刻工艺300。
由于横向蚀刻工艺300，图2B所示的间隔/空隙210转变(例如，横向地/水平地扩大)成如图3B所示的间隔/空隙210A。横向扩大的间隔/空隙210A的每个均具有水平尺寸(在X方向上测量的)230A。与间隔/空隙210的水平尺寸230相比，扩大的间隔/空隙210A的水平尺寸230A的每侧(左侧和右侧)均宽(在X方向上)距离240。距离240也可以称为邻近推进。在一些实施例中，距离240大于0，但是小于栅极间隔件140的厚度/水平尺寸180。例如，距离240可以在大于约2nm但小于6nm的范围内，例如，约4nm。
由于横向蚀刻工艺300而增加的尺寸230A意味着将半导体层110的尺寸250减小至尺寸250A。然而，伪栅极堆叠件的尺寸170(以上参照图1B讨论的)限定晶体管的物理栅极长度，尺寸250A对应于由半导体结构100形成的HGAA晶体管的沟道的电长度。由于可以经由横向蚀刻工艺300通过控制半导体层110的横向蚀刻的量来调整尺寸250A，因此也可以相应地调整沟道的电长度。本发明的这个方面将在下面更详细地讨论。
现在参照图4A至图4B，对半导体结构100实施蚀刻工艺400。在一些实施例中，蚀刻工艺400配置为具有低蚀刻选择性或没有蚀刻选择性。由于蚀刻工艺400，修整包裹间隔/空隙210A的半导体层108的一些部分。包裹间隔/空隙210A的半导体层108的剩余部分可以称为纳米线108A。与设置在伪栅极堆叠件下面的并且不受蚀刻工艺400影响的半导体层108的部分相比，纳米线108A具有缩小的尺寸(在Z方向上测量的)。因此，蚀刻工艺400可以称为纳米线缩小工艺。纳米线108A可以用作HGAA晶体管的源极/漏极(S/D)的一部分，并且对应于纳米线108A的位置的区域可以称为S/D区域410。同时，半导体层108的剩余部分可以用作HGAA晶体管的沟道。
现在参照图5A至图5B，实施外延生长工艺500以在半导体结构100的S/D区域410中生长半导体元件510。在一些实施例中，外延生长工艺500包括分子束外延(MBE)工艺或化学汽相沉积工艺和/或其它合适的外延生长工艺。在另一些实施例中，半导体元件510原位或非原位掺杂有n型掺杂剂或p型掺杂剂。例如，在一些实施例中，半导体元件510包括掺杂有硼的硅锗(SiGe)以用于形成PFET的S/D部件。在一些实施例中，半导体元件510包括掺杂有磷的硅以用于形成NFET的S/D部件。在各个实施例中，砷和锑也用作S/D部件中的掺杂剂。为了进一步实现这些实施例，半导体元件510可以包括摩尔比率在从约10％至约70％的范围的Ge。在某些实施例中，半导体元件510是重掺杂的以与之后形成的S/D接触金属形成欧姆接触。
由于外延生长工艺500，半导体元件510填充图4B所示的间隔/空隙210A。半导体元件510的每个均包裹(例如，图5A所示的截面图中的360度圆周)相应的一个纳米线108A。例如，半导体元件510可以与纳米线108A的四个侧(在截面侧视图中的纳米线108A的每个均具有类方形形状的示出的实施例中)直接物理接触。在一些实施例中，半导体元件510的厚度520在从约几纳米至几十纳米的范围。
在实施例中，半导体元件510与半导体层108(以及纳米线108A)具有相同的材料组分。例如，半导体元件510和半导体层108都包括硅。在一些可选实施例中，半导体元件510和半导体层108可以具有不同的材料或组分。在各个实施例中，半导体元件510可以包括诸如硅或锗、化合物半导体(诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟)、合金半导体(诸如GaAsP、AlInAs、AlGaAs、InGaAs、GaInP和/或GaInAsP)或它们的组合的半导体材料。
半导体元件510和纳米线108A可以共同用作半导体结构100的S/D部件。在一些实施例中，半导体元件510A和纳米线108A可以包括相同类型的掺杂剂(例如，都是n型掺杂的或都是p型掺杂的)，但是半导体元件510中的掺杂剂浓度高于纳米线108A中的掺杂剂浓度。可选地，半导体元件510和纳米线108A可以包括相同类型的掺杂剂但是可以具有不同的掺杂剂种类。
如以上参照图3B讨论的，可以通过横向蚀刻工艺300调整沟道的电长度(例如，位于栅极堆叠件下面的半导体层110的水平尺寸250A)。根据本发明的各个方面，半导体结构100的不同区域可以配置为具有不同的电长度。这将在下面参照图6至图10详细地讨论，图6至图10示出了处于制造的不同阶段的半导体结构100的实施例的图解局部截面侧视图(在X-Z平面，与图1B至图5B类似)。以上已经参照图1A至图5A和图1B至图5B描述了图6至图10所示的一些制造工艺。因此，为了清楚和一致，在适当的范围内，在图6至图10出现的与图1A至图5A以及图1B至图5B相同的元件标记相同。
参照图6，半导体结构100包括在垂直方向(例如，Z方向)上以交替和交错方式设置的多个半导体层108和110。在最上半导体层108上方形成多个伪栅极堆叠件105。伪栅极堆叠件105的每个均包括介电层120和在介电层120上方形成的多晶硅层130。在介电层120和多晶硅层130的侧壁上形成栅极间隔件140。在一些实施例中，栅极间隔件140也可以被认为是伪栅极堆叠件105的一部分。如以上讨论的，多晶硅层130之后将经受栅极置换工艺以用金属栅极层替换。在一些实施例中，介电层120也将通过栅极置换工艺用高k电介质替换。
伪栅极堆叠件105的一些位于半导体结构100的区域610中，而其它的伪栅极堆叠件105位于半导体结构100的不同的区域620中。在一些实施例中，区域610包括标准阈值电压(SVt)区域，而区域620包括高阈值电压(HVt)区域。与位于SVt区域610中的晶体管相比，位于HVt区域620中的晶体管具有更高的阈值电压(Vt)并且消耗更少的功率。因此，HVt区域中的晶体管可以适用于功率关键应用。
现在参照图7，在区域620中的最上半导体层108上方和伪栅极堆叠件105上方形成图案化的光刻胶层640。图案化的光刻胶层640的形成可以包括诸如光刻胶沉积、曝光、曝光后烘烤以及显影的工艺。图案化的光刻胶层640在区域610中留下暴露区域610中的伪栅极堆叠件105和半导体层108的开口。
用图案化的光刻胶层640作为蚀刻掩模，实施蚀刻工艺650以蚀刻区域610中的半导体层110。例如，蚀刻工艺650包括以上参照图2A和图2B讨论的蚀刻工艺200，此处实施蚀刻工艺200以选择性地去除区域610中的半导体层110的部分，从而在区域610中形成间隔/空隙。蚀刻工艺650也包括以上参照图3A至图3B讨论的横向蚀刻工艺300，此处实施横向蚀刻工艺300以使间隔/空隙横向向内延伸以形成扩大的间隔/空隙210A。
位于区域610中的伪栅极堆叠件105下方的半导体层110的剩余的段110A的每个均具有水平尺寸(在X方向上测量的)660。如以上讨论的，可以通过调整横向蚀刻工艺300的参数(例如，通过控制蚀刻时间)来配置水平尺寸660的值。例如，随着横向蚀刻工艺300的蚀刻时间增加，间隔/空隙210A变得更宽(由于更多的横向蚀刻)，而尺寸660缩小。再者，尺寸660对应于区域610中的HGAA晶体管的沟道的有效电长度。
由于图案化的光刻胶层640在蚀刻工艺650期间用作保护掩模，因此在图7所示的制造的阶段期间，位于区域620中的半导体层110基本未受影响。
现在参照图8，在区域610中的最上半导体层108上方和伪栅极堆叠件105上方形成图案化的光刻胶层670。图案化的光刻胶层670的形成可以包括诸如光刻胶沉积、曝光、曝光后烘烤以及显影的工艺。图案化的光刻胶层670在区域620中留下暴露区域620中的伪栅极堆叠件105和半导体层108的开口。
用图案化的光刻胶层670作为蚀刻掩模，实施蚀刻工艺680以蚀刻区域620中的半导体层110。例如，蚀刻工艺680包括以上参照图2A和图2B讨论的蚀刻工艺200，此处实施蚀刻工艺200以选择性地去除区域620中的半导体层110的部分，从而在区域620中形成间隔/空隙210。
位于区域620中的伪栅极堆叠件105下方的半导体层110的剩余的段110B的每个均具有水平尺寸(在X方向上测量的)690。如以上讨论的，可以通过调整横向蚀刻工艺300的参数(例如，通过控制蚀刻时间)来配置水平尺寸690的值。例如，随着横向蚀刻工艺300的蚀刻时间的增加，间隔/空隙210变得更宽(由于更多的横向蚀刻)，而尺寸690缩小。再者，尺寸690对应于区域620中的HGAA晶体管的沟道的有效电长度。
应该理解，虽然图8所示的实施例中的蚀刻工艺680没有涉及以上参照图3A和图3B讨论的横向蚀刻工艺300(可以实施横向蚀刻工艺300以使间隔/空隙210横向向内延伸)，但是在可选实施例中，如果需要，横向蚀刻工艺300仍可以作为蚀刻工艺680的一部分来实施。例如，横向蚀刻工艺300的可选实施将为尺寸690的值提供较大程度的控制。
现在参照图9，对半导体结构100实施以上参照图5A至图5B讨论的外延生长工艺500以外延生长填充间隔/空隙210/210A的半导体元件510。在一些实施例中，填充间隔210A比间隔210需要更长的时间。因此，在相同的S/D外延工艺用于间隔210A和210的实施例中，间隔210中生长的外延材料将大于间隔210A中生长的外延材料。这种尺寸差异是此处描述的独特工艺流程的结果并且可以是根据本发明的工艺制造的器件的可识别特性。如以上参照图5A至图5B讨论的，半导体元件510的每个均包裹相应的一个半导体层108，例如，360度圆周。再者，半导体元件510(以及被包裹的半导体层108的部分)可以用作半导体结构100的S/D部件。
虽然未在图9中详细地说明，但是应该理解，在实施外延生长工艺500之前，也可以实施以上参照图4A和图4B讨论的蚀刻工艺400以修整或缩小间隔/空隙210/210A之间的半导体层的部分。
现在参照图10，对半导体结构100实施栅极置换工艺700以用高k金属栅极720替换伪栅极堆叠件105和设置在其下面的半导体层110。作为栅极置换工艺700的一部分，例如，通过合适的蚀刻工艺去除多晶硅层130(以及介电层120，如果介电层120是伪栅极氧化物的话)。也去除设置在伪栅极堆叠件105下面的半导体层110和110A的部分。多晶硅层130和介电层120的去除形成了由栅极间隔件140限定的开口。用每个均包括高k栅极电介质和金属栅电极的高k金属栅极720填充这些开口。
图11示出了置换高k金属栅极720的更详细的截面图。该截面图沿着Z-X平面截取。例如，在伪栅极堆叠件的去除之前，围绕栅极间隔件140形成介电隔离结构730。在多晶硅层130和介电层120的去除之后，栅极间隔件140(以及介电隔离结构730)限定将用高k金属栅极720填充的开口。例如，在开口中形成高k介电层740。如以上讨论的，高k介电层740可以包括高k材料(例如，具有大于氧化硅的介电常数)，诸如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇、钛酸锶、其它合适的金属氧化物或它们的组合。
可以在高k介电层740上方形成功函金属层750。功函金属层750可以包括配置为调整晶体管的功函数的功函金属。功函金属层750可以是p型功函金属层或n型功函金属层。p型功函金属层包括选自但不限于氮化钛、氮化钽、钌、钼、钨、铂或它们的组合的组的金属。n型功函金属层包括选自但不限于钛、铝、碳化钽、碳氮化钽、氮化钽硅或它们的组合的组的金属。p型或n型功函金属层可以包括多个层并且可以通过CVD、PVD和/或其它合适的工艺沉积。
在功函金属层750上方形成填充金属760。填充金属760可以用作金属栅电极的主导电部分。填充金属760可以包括铝、钨、钴、铜和/或其它合适的材料，并且可以通过CVD、PVD、镀和/或其它合适的工艺形成。
填充开口(由半导体层110/110A的去除形成)的高k金属栅极也具有高k介电层740、功函金属层750和填充金属760。如图11所示，功函金属层750圆周地包裹填充金属760，并且高k介电层740也圆周地包裹高功函金属层750。同时，半导体层108的部分也由高k金属栅极(包括高k介电层740和金属层750至760)包裹。半导体层108的这些部分用作晶体管的沟道。半导体结构100包括多个这些垂直“堆叠的”高k金属栅极，并且因此半导体结构100是堆叠的水平全环栅(S-HGAA)器件。
现在返回图10，可以看出，在区域610中形成的高k金属栅极结构720A与在区域620中形成的高k金属栅极结构720B具有不同的横向尺寸。具体地，在区域610中形成的高k金属栅极结构720A具有横向尺寸660(在X方向上测量的)，而在区域620中形成的高k金属栅极结构720B具有横向尺寸690(在X方向上测量的)。横向尺寸690大于或小于横向尺寸660。例如，在图10所示的实施例中，在一些实施例中，横向尺寸690可以比横向尺寸660大大约5至10nm。横向尺寸690和横向尺寸660之间存在比率。在一些实施例中，该比率在约1.5和约2之间的范围内。
如以上讨论的，可以通过精确地控制蚀刻工艺650和/或680的工艺参数来配置横向尺寸660和690的差异。由于横向尺寸660对应于区域610中的HGAA晶体管的沟道的有效电长度，并且横向尺寸690对应于区域620中的HGAA晶体管的沟道的有效电长度，因此，可以看出半导体结构100可以具有用于不同区域的不同的有效电长度，即使物理栅极长度(由伪栅极堆叠件的尺寸限定)基本相同。
图12是示出制造例如GAA器件的半导体结构的方法800的流程图。方法800包括提供半导体结构的步骤810，半导体结构包括与多个第二半导体层交错的多个第一半导体层。第一半导体层和第二半导体层具有不同的材料组分。
步骤800包括在最上第一半导体层上方形成伪栅极堆叠件的步骤820。在一些实施例中，形成伪栅极堆叠件包括在半导体结构的第一区域和第二区域中形成多个伪栅极堆叠件。在一些实施例中，第一区域是标准阈值电压(SVt)区域，而第二区域是高阈值电压(HVt)区域。
方法800包括实施第一蚀刻工艺以去除未设置在伪栅极堆叠件下面的第二半导体层的部分，从而形成多个空隙的步骤830。第一蚀刻工艺在第一半导体层和第二半导体层之间具有蚀刻选择性。在一些实施例中，配置第一半导体层和第二半导体层之间的蚀刻选择性，从而使得第一蚀刻工艺去除第二半导体层的部分而没有去除第一半导体层。
方法800包括实施第二蚀刻工艺以扩大空隙的步骤840。在一些实施例中，实施第二蚀刻工艺以扩大每个空隙的水平尺寸。在一些实施例中，实施第一蚀刻工艺和第二蚀刻工艺，从而使得第一区域中的空隙和第二区域中的空隙具有不同的水平尺寸。在一些实施例中，第二蚀刻工艺在第一区域中实施而没有在第二区域中实施。
在一些实施例中，第一半导体层的每个均包括硅层，第二半导体层的每个均包括硅锗层。
应该理解，可以在步骤810至840之前、期间或之后实施额外的工艺。例如，方法800可以包括在扩大的空隙中外延生长第三半导体层的步骤。例如，方法800可以包括用具有高k栅极电介质和金属栅电极的栅极结构替换伪栅极堆叠件的步骤。在一些实施例中，替换伪栅极堆叠件包括用具有高k栅极电介质和金属栅电极的多个栅极结构替换设置在伪栅极下面的第二半导体层的部分。在一些实施例中，对于替换第二半导体层的部分的栅极结构的每个，高k介电层圆周地包裹金属栅电极。例如，方法800可以包括形成接触开口、接触金属以及各个接触件、通孔、布线和多层互连部件(例如，金属层和层间电介质)的步骤以连接各个部件以形成可以包括一个或多个多栅极器件的功能电路。
基于以上讨论的，可以看出，本发明的实施例提供了超越现有半导体器件的优势。然而，应该理解，没有特定优势都是需要的，其它实施例可以提供不同的优势，并且不是所有优势都必须在此处公开。
优势在于，能够为沟道配置不同的有效电长度允许阈值电压Vt的调整具有更大的灵活性。更详细地，由于半导体器件尺寸缩小，用于晶体管的沟道变得越来越短，这引起了各种问题(尤其对于GAA器件)。例如，GAA器件具有比常规的平面器件或常规的FinFET器件更小的耗尽区域。因此，Vt注入的剂量可能需要比常规装置更重。然而，重掺杂可能引起不期望的迁移率降低。此外，由于用于GAA器件的沟道由多个纳米线组成(而不是传统器件的单个阻挡材料)，因此GAA器件具有比传统器件更小的沟道体积。因此，纳米线的掺杂可能导致这些纳米线沟道的一些接收比其它纳米线的一些显著更大量的掺杂剂。这导致GAA器件的更差的随机掺杂波动。由于以上讨论的这些原因，GAA器件难以通过注入/掺杂来调整其Vt。
相比之下，本发明允许通过控制用于晶体管的沟道的有效电长度来调整阈值电压。例如，可以配置以上参照图3B讨论的横向蚀刻工艺调整高k金属栅极堆叠件的横向尺寸(对应于沟道的电长度的调整)。这允许相应地配置阈值电压Vt。
此外，本发明允许对不同的区域提供不同的有效栅极长度。例如，可以对高Vt区域提供一个栅极长度，而可以对标准Vt区域提供不同的栅极长度。这种能力进一步增加了根据本发明制造的半导体结构的通用性。此外，这种能力也意味着不需要在高Vt区域和标准Vt区域之间放置伪多晶硅。进而，这导致单元尺寸减小。其它优势包括GAA器件中的随机掺杂波动缺陷的消除，这是由于本发明不再需要Vt注入。
本发明的一个实施例涉及制造GAA器件的方法。提供半导体结构，半导体结构包括与多个第二半导体层交错的多个第一半导体层。第一半导体层和第二半导体层具有不同的材料组分。在最上第一半导体层上方形成伪栅极堆叠件。实施第一蚀刻工艺以去除未设置在伪栅极堆叠件下面的第二半导体层的部分，从而形成多个空隙。第一蚀刻工艺在第一半导体层和第二半导体层之间具有蚀刻选择性。之后，实施第二蚀刻工艺以扩大空隙。
在上述方法中，其中，配置所述第一半导体层和所述第二半导体层之间的蚀刻选择性，从而使得所述第一蚀刻工艺去除所述第二半导体层的部分而没有去除所述第一半导体层。
在上述方法中，其中，实施所述第二蚀刻工艺以扩大所述空隙的每个的水平尺寸。
在上述方法中，其中：所述第一半导体层的每个均包括硅层；以及所述第二半导体层的每个均包括硅锗层。
在上述方法中，还包括：在扩大的空隙中外延生长第三半导体层。
在上述方法中，还包括：用具有高k栅极电介质和金属栅电极的栅极结构替换所述伪栅极堆叠件。
在上述方法中，还包括：用具有高k栅极电介质和金属栅电极的栅极结构替换所述伪栅极堆叠件，其中，替换所述伪栅极堆叠件包括用具有高k栅极电介质和金属栅电极的多个栅极结构替换设置在所述伪栅极堆叠件下面的所述第二半导体层的部分。
在上述方法中，还包括：用具有高k栅极电介质和金属栅电极的栅极结构替换所述伪栅极堆叠件，其中，替换所述伪栅极堆叠件包括用具有高k栅极电介质和金属栅电极的多个栅极结构替换设置在所述伪栅极堆叠件下面的所述第二半导体层的部分，对于替换所述第二半导体层的部分的所述栅极结构的每个，所述高k栅极电介质圆周地包裹所述金属栅电极。
在上述方法中，其中，形成所述伪栅极堆叠件包括在所述半导体结构的第一区域和第二区域中形成多个伪栅极堆叠件，并且其中，实施所述第一蚀刻工艺和所述第二蚀刻工艺，从而使得所述第一区域中的空隙和所述第二区域中的空隙具有不同的水平尺寸。
在上述方法中，其中，形成所述伪栅极堆叠件包括在所述半导体结构的第一区域和第二区域中形成多个伪栅极堆叠件，并且其中，实施所述第一蚀刻工艺和所述第二蚀刻工艺，从而使得所述第一区域中的空隙和所述第二区域中的空隙具有不同的水平尺寸，所述第二蚀刻工艺在所述第一区域中实施而没有在所述第二区域中实施。
在上述方法中，其中，形成所述伪栅极堆叠件包括在所述半导体结构的第一区域和第二区域中形成多个伪栅极堆叠件，并且其中，实施所述第一蚀刻工艺和所述第二蚀刻工艺，从而使得所述第一区域中的空隙和所述第二区域中的空隙具有不同的水平尺寸，所述第一区域是标准阈值电压(SVt)区域；以及所述第二区域是高阈值电压(HVt)区域。
本发明的另一实施例涉及制造GAA器件的方法。提供包括多个第一半导体层和多个第二半导体层的半导体结构。第一半导体层和第二半导体层具有不同的材料组分并且在垂直方向上彼此交替设置。在最上第一半导体层上方形成多个伪栅极堆叠件。去除半导体结构的第一区域中的第二半导体层的部分，从而在第一区域中的第二半导体层的去除部分的位置形成多个第一间隔。第一间隔经由横向蚀刻工艺水平延伸。之后，去除半导体结构的第二区域中的第二半导体层的部分，从而在第二区域中的第二半导体层的去除部分的位置形成多个第二间隔。第一区域中的第二半导体层的剩余部分与第二区域中的第二半导体层的剩余部分具有不同的水平尺寸。
在上述方法中，还包括：实施栅极置换工艺以用每个均包括高k栅极电介质和金属栅电极的栅极结构替换所述第一区域和所述第二区域中的所述伪栅极堆叠件和所述第二半导体层的剩余部分。
本发明的又另一实施例涉及半导体结构。半导体结构包括每个均在第一方向上延伸的多个纳米线。该纳米线在垂直于第一方向的第二方向上彼此堆叠。半导体结构包括每个均包裹相应的一个纳米线的多个第一栅极结构和第二栅极结构。第一栅极结构的每个均具有在第一方向上测量的第一尺寸。第二栅极结构的每个均具有在第一方向上测量的第二尺寸，第一尺寸大于或小于第二尺寸。
在上述半导体结构中，还包括设置在所述纳米线的最上一个纳米线上方的多个第三栅极结构，其中：所述第一栅极结构的每个均设置在所述第三栅极结构的一个下面；以及所述第二栅极结构的每个均设置在所述第三栅极结构的另一个下面。
在上述半导体结构中，还包括设置在所述纳米线的最上一个纳米线上方的多个第三栅极结构，其中：所述第一栅极结构的每个均设置在所述第三栅极结构的一个下面；以及所述第二栅极结构的每个均设置在所述第三栅极结构的另一个下面，其中，所述第三栅极结构在至少所述第一方向上具有彼此相同的尺寸。
在上述半导体结构中，还包括设置在所述纳米线的最上一个纳米线上方的多个第三栅极结构，其中：所述第一栅极结构的每个均设置在所述第三栅极结构的一个下面；以及所述第二栅极结构的每个均设置在所述第三栅极结构的另一个下面，其中，所述第一栅极结构、所述第二栅极结构和所述第三栅极结构的每个均包括高k栅极电介质和金属栅电极，并且其中，所述高k栅极电介质至少部分地包裹所述金属栅电极。
在上述半导体结构中，其中：所述第一栅极结构位于所述半导体结构的标准阈值电压(SVt)区域中；以及所述第二栅极结构位于所述半导体结构的高阈值电压(HVt)区域中。
在上述半导体结构中，其中：所述第一栅极结构位于所述半导体结构的标准阈值电压(SVt)区域中；以及所述第二栅极结构位于所述半导体结构的高阈值电压(HVt)区域中，所述第一尺寸大于所述第二尺寸。
在上述半导体结构中，还包括：每个均包裹所述纳米线的相应的一个纳米线的多个源极/漏极组件。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
提供半导体结构，所述半导体结构包括与多个第二半导体层交错的多个第一半导体层，所述第一半导体层和所述第二半导体层具有不同的材料组分；
在最上第一半导体层上方形成伪栅极堆叠件；
实施第一蚀刻工艺以去除未设置在所述伪栅极堆叠件下面的所述第二半导体层的部分，从而形成多个空隙，其中，所述第一蚀刻工艺在所述第一半导体层和所述第二半导体层之间具有蚀刻选择性；以及
实施第二蚀刻工艺以扩大所述空隙。
2.根据权利要求1所述的方法，其中，配置所述第一半导体层和所述第二半导体层之间的蚀刻选择性，从而使得所述第一蚀刻工艺去除所述第二半导体层的部分而没有去除所述第一半导体层。
3.根据权利要求1所述的方法，其中，实施所述第二蚀刻工艺以扩大所述空隙的每个的水平尺寸。
4.根据权利要求1所述的方法，其中：
所述第一半导体层的每个均包括硅层；以及
所述第二半导体层的每个均包括硅锗层。
5.根据权利要求1所述的方法，还包括：在扩大的空隙中外延生长第三半导体层。
6.根据权利要求1所述的方法，还包括：用具有高k栅极电介质和金属栅电极的栅极结构替换所述伪栅极堆叠件。
7.根据权利要求6所述的方法，其中，替换所述伪栅极堆叠件包括用具有高k栅极电介质和金属栅电极的多个栅极结构替换设置在所述伪栅极堆叠件下面的所述第二半导体层的部分。
8.根据权利要求7所述的方法，其中，对于替换所述第二半导体层的部分的所述栅极结构的每个，所述高k栅极电介质圆周地包裹所述金属栅电极。
9.一种形成半导体器件的方法，包括：
提供半导体结构，所述半导体结构包括多个第一半导体层和多个第二半导体层，所述第一半导体层和所述第二半导体层具有不同的材料组分并且在垂直方向上彼此交替设置；
在最上第一半导体层上方形成多个伪栅极堆叠件；
去除所述半导体结构的第一区域中的所述第二半导体层的部分，从而在所述第一区域中的所述第二半导体层的去除部分的位置形成多个第一间隔；
经由横向蚀刻工艺水平地延伸所述第一间隔；以及
之后，去除所述半导体结构的第二区域中的所述第二半导体层的部分，从而在所述第二区域中的所述第二半导体层的去除部分的位置形成多个第二间隔，其中，所述第一区域中的所述第二半导体层的剩余部分与所述第二区域中的所述第二半导体层的剩余部分具有不同的水平尺寸。
10.一种半导体结构，包括：
多个纳米线，每个均在第一方向上延伸，其中，所述纳米线在垂直于所述第一方向的第二方向上彼此堆叠；以及
多个第一栅极结构和第二栅极结构，每个均包裹所述纳米线的相应的一个纳米线，其中，所述第一栅极结构的每个均具有在所述第一方向上测量的第一尺寸，并且其中，所述第二栅极结构的每个均具有在所述第一方向上测量的第二尺寸，所述第一尺寸大于或小于所述第二尺寸。
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