CN106664071A - 高速芯片间通信用多电平驱动电路 - Google Patents
高速芯片间通信用多电平驱动电路 Download PDFInfo
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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Abstract
所描述的输出线路驱动器系统包括多个并行的驱动器元件。所述并行结构允许有效地产生可调输出幅度的多个输出信号电平,可选地包括有限脉冲响应信号整形和偏斜预补偿。
Description
相关申请的交叉引用
本申请要求申请日为2014年6月25日,申请号为14/315,306,名称为“高速芯片间通信用多电平驱动器”的美国专利申请的优先权,并通过引用将其内容整体并入本文。
参考文献
以下参考文献通过引用整体并入本文,以供所有目的之用:
公开号为2011/0268225,申请号为12/784,414,申请日为2010年5月20日,发明人为Harm Cronie和Amin Shokrollahi,名称为“正交差分向量信令”的美国专利申请(下称《Cronie I》);
公开号为2011/0302478,申请号为12/982,777,申请日为2010年12月30日,发明人为Harm Cronie和Amin Shokrollahi,名称为“具有抗共模噪声和抗同步开关输出噪声能力的高引脚利用率高功率利用率芯片间通信”的美国专利申请(下称《Cronie II》);
申请号为13/030,027,申请日为2011年2月17日,发明人为Harm Cronie、AminShokrollahi和Armin Tajalli,名称为“利用稀疏信令码进行抗噪声干扰、高引脚利用率、低功耗通讯的方法和系统”的美国专利申请(下称《Cronie III》);
申请号为61/753,870,申请日为2013年1月17日,发明人为John Fox,BrianHolden,Peter Hunt,John D Keay,Amin Shokrollahi,Richard Simpson,Anant Singh,Andrew Kevin John Stewart和Giuseppe Surace,名称为“低同步开关噪声芯片间通信方法和系统”的美国临时专利申请(下称《Fox I》);
申请号为61/763,403,申请日为2013年2月11日,发明人为John Fox,BrianHolden,Ali Hormati,Peter Hunt,John D Keay,Amin Shokrollahi,Anant Singh,AndrewKevin John Stewart,Giuseppe Surace和Roger Ulrich,名称为“高带宽芯片间通信接口方法和系统”的美国临时专利申请(下称《Fox II》);
申请号为61/773,709,申请日为2013年3月6日,发明人为John Fox,BrianHolden,Peter Hunt,John D Keay,Amin Shokrollahi,Andrew Kevin John Stewart,Giuseppe Surace和Roger Ulrich,名称为“高带宽芯片间通信接口方法和系统”的美国临时专利申请(下称《Fox III》);
申请号为61/812,667,申请日为2013年4月16日,发明人为John Fox,BrianHolden,Ali Hormati,Peter Hunt,John D Keay,Amin Shokrollahi,Anant Singh,AndrewKevin John Stewart和Giuseppe Surace,名称为“高带宽通信接口方法和系统”的美国临时专利申请(下称《Fox IV》);
申请号为13/842,740,申请日为2013年3月15日,发明人为Brian Holden、AminShokrollahi和Anant Singh,名称为“芯片间通信用向量信令码中偏斜耐受方法以及用于芯片间通信用向量信令码的高级检测器”的美国专利申请(下称《Holden I》);
申请号为13/895,206,申请日为2013年5月15日,发明人为Roger Ulrich和PeterHunt,名称为“利用差分和有效检测芯片间通信用向量信令码的电路”的美国专利申请(下称《Ulrich I》);
本申请还引用了以下参考文献,并以括号内的标记对其进行表示:
【Kojima】专利号为8,575,961,申请日为2009年10月13日,授权日为2013年11月5日,发明人为Shoji Kojima,名称为“多值驱动器电路”的美国专利。
背景技术
通信系统中,信息可从一个物理位置传输至另一物理位置。对于此类信息传输,人们一般要求其可靠,快速,且消耗的资源最少。一种最常见的信息传输媒介为串行通信链路,其可基于以地面或其他常用参考为相对参考的单个有线电路,或基于多个此类以地面或其他常用参考为相对参考的电路,或基于相互间作为相对参考的多个电路。
一般情况下,串行通信链路可用来跨越多个时间周期。在每个此类时间周期内,链路内的一个或多个信号表示一定量的信息,从而实现该信息的传送,所述信息通常以比特为度量单位。其中,在高电平上,串行通信链路将发射器连接至接收器,所述发射器在每一时间周期内发送一个或多个信号,而所述接收器接收被发送信号的近似信号(因链路内信号退化,噪声及其他失真引起)。发射器通过“消耗”被传送的信息而生成代表信号。接收器用于从其接收的信号中确定出所传送的信息。在总体不发生错误的情况下,接收器可精确地输出发射器所消耗的比特。
串行通信链路的最佳设计往往取决于其用途。在许多情况下,需要在各种性能参数之间做出权衡,例如带宽(每单位时间和/或周期所能传送的比特数)、引脚利用率(一次可传送的比特或比特等同物的数量与实现所述传送所要求的线路的数目的比值)、功耗(发射器、信号逻辑、接收器等每传送一个比特所消耗的功率单位)、抗同步开关输出噪声(Simultaneous Switching Output,SSO)能力及抗串扰能力、以及期望误差率。
串行通信链路的一例为差分信令(Differential Signaling,DS)链路。差分信令的工作原理为:在一条线路上发送信号,并在与该线路成对的线路上发送所述信号的反信号;所述信号的信息由两条线路之间的差值,而非其相对于地面或其他固定参考的绝对值表示。相比于单端信令(Single-EndedSignaling,SES),差分信令可抵消串扰及其他共模噪声,从而提高接收器对原始信号的恢复能力。此外,还有多种信令方法可在保留差分信令的有用特性的同时,实现比差分信令更高的引脚利用率。多种此类方法均同时运行于两条以上线路,每条线路使用二进制信号,但以分组比特形式对信息进行映射。
向量信令为一种信令方法。通过向量信令,多条线路中的多个信号在保持每个信号的独立性的同时可视为一个整体。该整体信号中的每一个均称为分量,所述多条线路的数量称为向量的“维数”。在一些实施方式中,与差分信令的成对线路一样,某一线路中的信号完全取决于另一线路中的信号。因此,在某些情况下,上述向量维数可指多条线路中信号的自由度的个数,而非所述多条线路的数量。
在二进制向量信令中,每一分量具有坐标值(或简称“坐标”),该坐标值为两个可能取值当中之一。举例而言,可将8条单端信令线视为一个整体,其中,每个分量/线路的取值为信号周期两值中的一值。那么,该二进制向量信令的一个“码字”即对应所述整体分量/线路组的其中一个可能状态。对于一个给定的向量信令编码方案,有效可取码字的集合称为“向量信令码”或“向量信令向量集”。“二进制向量信令码”即为将信息比特映射至二进制向量的一种映射方法和/或一组规则。在8条单端信令线的上例中,由于每个分量的自由度允许其取值为上述两个可取坐标中的任何一个,该码字集合中码字的数量即为2^8,或256。在单端信令或差分信令链路中,二进制向量信令码所使用的输出驱动器仅需发送两个电压或电流电平,对应于每个向量元素的两个可能坐标值。
在非二进制向量信令中,每个分量的坐标值选自由多于两个的可能取值组成的组。“非二进制向量信令码”则指将信息比特映射至非二进制向量的一种映射方法和/或一组规则。非二进制向量信令码的对应驱动器必须能够发送与每个向量输出的所选坐标值对应的多个电压或电流电平。
《Cronie I》,《Cronie II》,《Cronie III》,《Fox I》,《Fox II》,《Fox III》,《FoxIV》和《Holden I》中均描述了向量信令方法的实例。
发明内容
可使用串行通信链路通信的发射器和接收器,其中,所述串行通信链路使用基于均衡向量信令码的信令。所述向量信令码在每个发送单位间隔内通过所述通信链路的多条线路发送符号向量。所述向量的分量数可以为二,三,四或大于四。分量的坐标值数可以为二,三,四或大于四。例如,链路可使用具有四个可能坐标值的四个分量,所述四个可能坐标值为一个高值、一个低值以及该高值和低值的相反值,而且具有所述高值的信号可抵消三个具有所述低值的相反值的信号,具有所述高值的相反值的信号可抵消三个具有所述低值的信号,而且在这种方式中,所述链路可使用所述四个分量通过下述方式在一个周期内传送三个比特:将所述八种可能的三个比特组合映射至由一个所述高值和三个所述低值的相反值的四种排列组合形式以及一个所述高值的相反值和三个所述低值的四种排列组合形式表示的八个向量码字。在一种更加具体的实施方式中,所述高值和低值为相对于参考值的电压值,所述高值与其相反值大小相等但符号相反,所述低值与其相反值大小相等但符号相反,所述高值的大小为所述低值大小的三倍。作为另一例,一种不同链路可使用选自三个可能坐标值的三个分量,所述三个可能坐标值分别为一个正值,一个较小正值以及一个最小正值或零,其中,所有向量分量值之和为常数。此类代码也为平衡码,只不过与依赖单端电源的实施方式的常见做法相同,所有可能坐标值上均叠加有额外偏移量或直流分量。
根据本发明的至少一种实施方式的方法和装置在物理信道中发送数据,从而提供以低功耗实现高总带宽的高速低延迟接口,以将多芯片系统中的集成电路芯片相互连接。在一些实施方式中,使用不同电压、电流等电平实现信令,并且可使用两个以上的电平,例如,每线信号具有四值当中一值的四进制信令系统。
此“发明内容”部分为以下“具体实施方式”部分中所描述概念的选择介绍,其描述形式较为简单,进一步的描述请见下文“具体实施方式”部分。此外,此“发明内容”部分的目的并不在于指出权利要求所述技术方案的关键或必要技术特征,也不在于辅助确定权利要求所述技术方案的范围。通过查阅以下“具体实施方式”的内容以及附图,本领域技术人员可清楚了解本发明的其他目的和/或优点。
附图说明
图1为采用四个处理阶段的四线驱动器的一种实施方式的框图。
图2A,图2B和图2C为三种多电平输出线路驱动器实施方式示意图。
图3为采用两个处理阶段且适用于多分片实施方式的输出线路驱动器子系统的示意图。
图4为使用多个图3子系统实例的多分片单线路驱动器的实施方式。
图5为采用四个处理阶段及发送预补偿的多分片单线路驱动器的实施方式框图。
图6A和图6B所示为根据本发明至少一种实施方式的已发送H4码的各个线路信号以及所有线路的组合信令,其描述了对每个发送间隔内四个信号电平中的两个进行使用的情形。
图7为根据至少一种实施方式的方法流程图。
具体实施方式
虽然将多个完整系统集成至单个集成电路的技术能力在不断提高,但是多芯片系统及子系统仍具有显著的技术优势。出于非限制性描述目的,在本文所描述发明的至少一些方面的例示实施方式中,假设如下系统环境:(1)至少一个点对点通信接口将分别表示发射器和接收器的两个集成电路芯片相互连接;(2)其中,所述通信接口由至少一个互连信号线路组支持,每个互连信号线路组由四条高速传输线信号线路组成,并可在高速下实现中度损耗连接性;(3)向量信令码将信息作为线路组内每条线路上的同时发送值从发射器发送至接收器,其中,各值选自于四个电平;(4)所述向量信令码将所述线路组整体约束至固定电平和。
因此,在一种实施方式中,将首次描述于《Cronie I》中的H4向量信令码的符号坐标值作为相对于固定参考值的偏移电压电平进行传输,例如,以+200mV的偏移量表示“+1”,-66mV的偏移量表示“-1/3”等。在至少一种实施方式中,可对发送偏移幅度进行调节,以实现对适于所需接收信噪比的最小电平的使用,从而将发送功率最小化。
物理信道特性
出于非限制性描述目的,作为第一例,假设一种由至少一导线组组成的通信信道,该导线组为通过介电层与接地平面分隔的四条微带状导线。为了减小衰减和传播速度差异,该导线组内的四条导线以相同的制造特性共同布线。此外,还假设上述信道的每条导线在每一端均以其特征传输线阻抗端接。如此,按照50Ω典型传输线阻抗的现有规范做法,信息由带50Ω源阻抗的发射器发送,并且在接收器处检测为跨越50Ω终端电阻的电压或流经50Ω终端电阻的电流。在第二例中,上述导线组的大小增大至六条导线,而所有其他特征均与上述相同。增加导线组大小可实现对能在每条导线上传输更多信息(即所谓的“引脚利用率”)的代码的使用,但其代价在于,为了保证组内所有导线都具有相同传输线特性,布线和制造方面所受的制约条件更多。
本文所述的例示信号电平,信号频率及物理尺寸用于解释而非限制目的。除了上述之外,还可使用其他不同向量信令码进行通信。这些代码的每导线组可具有更多或更少的导线,每线路可传输更多或更少数目的信号电平,以及/或者可具有不同的码字制约条件。为了方便起见,本文中将信号电平描述为电压,而非与其等效的电流值。
本发明的其他实施方式可采用不同的信令电平、连接拓扑结构、端接技术和/或其他物理接口,包括光学性、电感性、电容性或电气互连。类似地,基于从发射器至接收器的单向通信的示例仅用于描述的清晰性,组合式发射器/接收器的实施方式以及双向通信的实施方式同样明确属于本发明范围之内。
H4码
在本文中,“H4”码也称NRZ集码,其指发射器消耗三个比特并在每个符号周期内在四条线路上输出信号的向量信令码及其相应的逻辑。在一些实施方式中,可使用包括多于一个比特组的并行结构,每个比特组均包括在每个符号周期内在四条线路上传输的三个比特,以及为该比特组配置的H4编码器和H4解码器。H4码具有四条信号线,以及在本文中分别表示为+1,+1/3,-1/3,-1的四个可取坐标值。H4码字为平衡码字,其中,每个码字如非(+1,-1/3,-1/3,-1/3)的四种排列组合形式中的一种,则为(-1,+1/3,+1/3,+1/3)的四种排列组合形式的一种,所有这些排列组合形式的和为零值的等同值。图6A所示为针对四线输出的H4编码信号波形。应当指出的是,虽然所有码字总集共使用四个不同信号电平,但是如图6B所示,通过对所有的四种信号波形进行叠加,仅有两个信号电平将在任何码字中均被使用。
在一种具体实施方式中,可使用200mV的偏移量发送表示+1的信号,使用-200mV的偏移量发送表示-1的信号,使用66mV的偏移量发送表示+1/3的信号,使用-66mV的偏移量发送表示-1/3的信号,其中,所述各电压电平为相对于固定参考的相对值。需要注意的是,无论所表示的码字为何,在任何单个时间间隔内发送(或接收,不考虑偏斜、串扰和衰减所导致的非对称效应)的所有信号的平均值为“0”,与所述固定参考电压相对应。H4中使用八个不同码字,足以编码每个发送符号间隔内的三个二进制比特。
上述H4编码方案还存在其他变体。以上给出的信号电平作为示例而非限制,其表示相对于标称参考电平的信号增量值。
5b6w三进制码
本文中称为“5b6w”的另一种向量信令码设计为在六线组上发送2个“+”信号,两个“-”信号,以及两个“0”信号。由此可见,此代码为每组具有相同数量“+”值和“-”值以允许每个码字之和恒为零值的“平衡”码。有相关知识的从业人员可注意到的是,在没有其他制约条件的情况下,以在每个六线组上发送2个“+”信号及两个“-”信号为基础的代码具有90种不同组合,足以编码6个而非5个比特。然而,如《Fox III》所充分阐明的,此类代码中使用32个码字的子集编码5个二进制比特,以实现接收器的大幅简化。
《Fox III》中的示例将5b6w码与输出驱动器结构相结合,该输出驱动器结构优化为以极低的功耗在高阻抗CMOS兼容互连上产生三个不同输出电压。本文实施例描述了5b6w码通过输出驱动器与三进制信号电平的结合,所述输出驱动器优化为与匹配阻抗端接的传输线共用。
多阶段处理
高速通信实施方式通常比单个通信电路实例具有更高的性能,并因此依赖于并行处理或流水线处理技术以实现更高的吞吐量。作为非限制性实施例,图1和图5展示了具有四个处理阶段的实施方式,每个处理阶段均以线路单位间隔传输速率的1/4工作,并相互交织以生成最终的线路速率传输序列;图3和图4展示了具有两个处理阶段的实施方式,每个阶段均以线路间隔传输速率的1/2工作,并相互交织以生成最终的线路速率输出序列。在具体实施方式中,可使用下至执行所有操作的单个阶段上至16或更多阶段的任何数目的处理阶段,而且这些多个阶段中的每一个阶段在所述传输系统的延展范围可大于或小于图示实施例中的延展范围。
示例H4驱动器
图1为本发明至少一种实施方式的框图表现形式。如上所述,此例采用四个编码器逻辑阶段,每个阶段均以发送时钟速率的1/4工作,而且这些处理阶段的输出随后通过相互交织而生成最终的发送数据流。为了描述的目的,假设发射输出流单位间隔为62.5皮秒,其对应于16G符号/秒的传输速率。因此,所述1/4速率时钟的每个阶段均以4GHz工作,而且每个编码器在每个周期内均具有250皮秒的处理时间。
由于H4码在每个四符号码字内编码三个二进制比特,因此其数据输入由四个并行处理阶段中每个阶段的三个数据比特组成。如此,每四个发送间隔共处理12个输入比特。编码器110包含编码逻辑的四个不同实例,每个实例将三个二进制数据输入比特映射成四个符号值。由于这四个符号中的每个符号可以取四个坐标值当中的一值(因此每个符号需要两个二进制输出比特),每个编码器输出112,114,116,118均为八比特输出。
发送预驱动器120,220,320和420当中的每一个均具有数字驱动器输入端,该输入端接受与码字的一个符号相对应的编码器输出值,并使其进入待分别由一条线路w0,wl,w2和w3输出的预备状态。举例而言,120接收并处理所述编码器输出的两个最低有效比特(即码字向量最低有效符号的坐标值),并将所选符号值映射成一种对表示所述信号值的具体线路信号值进行选择的结果。之后,多路复用器130将所述四个结果阶段交织成由多电平输出线路驱动器140在线路w0上发送的单个输出流。相位补偿器150可对所述输出信号的时序进行调整,以在所述1/4速率时钟信号和输出驱动器之间引入可调相位延迟。此可调延迟可作为总偏斜补偿方案的一部分,为各线路上的传播时间差异提供预补偿。在一种示例实施方式中,所述调整的范围跨越大约一个1/4速率时钟间隔,小于编码器和输出端之间编码器信号路径内数据锁存的任何所需建立、保持和/或消除时间。在发送单位间隔为62.5皮秒的上述具体示例中,所述1/4速率时钟的90度的调整范围对应于高达62.5皮秒的偏斜预补偿量,这相当于普通背板材料上大约12mm的传输线差分路径长度。
多电平输出线路驱动器
图2A,2B和2C为多电平输出线路驱动器(如图1中140,240,340,440内的多电平输出线路驱动器)的操作示意图。该线路驱动器针对输出分辨率的每个有效比特均使用传统的CMOS互补对,堆叠对或源极跟随器输出驱动器,并对这些有效比特的输出进行电阻性模拟求和,以得到上述最终输出结果。因此,如图2A所示,一个四电平(坐标选择的两比特)驱动器实施方式使用两个输出级,每个输出级均驱动传输线阻抗的共同负载Rterm通过不同的源阻抗,以获得不同的输出电平。所述MSB驱动器的源阻抗R为LSB驱动器源阻抗2R的一半,因此对输出电压具有双倍影响。在一种实际实施方式中,R和2R的并联组合与传输线阻抗Rterm相匹配,以提供正确的源端接电阻。因此,如果传输线阻抗为50Ω,则当R为75Ω且2R为150Ω时,图2A可实现匹配的源阻抗。
如本领域技术人员所熟知,通过比率方式在芯片上实现电阻器值的匹配较为简单。然而,如果还需要通过对阻抗R和2R的选择、修整或调节而进一步将驱动器晶体管的内部阻抗纳入考虑,此R/2R结构将变得极为困难。图2B的替代实施方式使用重复的驱动器元件,以在保持前述实施方式各数据比特间二进制权重关系的同时,实现匹配方式的大幅简化。图2B中,所有的阻抗R值均相同,而且由图2B中的三个R阻抗的并联组合实现对Rterm的匹配。如此,对于例示的50Ω阻抗,每个R均为150Ω(包括其驱动晶体管的有效阻抗)。在集成电路设计中,依赖于多个同值电阻器及多个同特性晶体管的做法被公认为一种较为有利的做法。举例而言,【Kojima】中描述了一种采用多个并联输出驱动器和同值电阻器的多电平输出驱动器电路,其中,每个控制输入以与本申请图2B所示的类似方式对二进制加权数目个驱动器和电阻器进行处理,以将输出驱动至多个所需的电压电平。【Kojima】中还描述了通过使用R/2R电阻性阶梯网络获得类似的多电平输出电平,此阶梯式结构为本领域中的一种公知结构。
图2C所示替代实施方式采用一元加权,而非二进制加权。其中,前述各实施方式通过连入MSB并排除LSB的方式获得输出电平“2”,而如图3所示的一元加法驱动器要求连入A,B和C中的任何两个输入。因此,如果图2A可描述为采用了对MSB值和LSB值的二进制加法模拟求和,图2B则可描述为采用了对第一和第二数据值的一元加法模拟求和。
本领域技术人员可注意到的是,上述各实施例还可直接用于5b6w码等三电平(三进制)信令或实际用于两电平(二进制)信令,并且还可通过加入额外电阻器和驱动器元件而容易地扩展至更高阶的信令。类似地,将图2C电路简化至图2D电路即足以满足使用三进制以内信令的实施方式的要求。
图3为输出驱动器子系统示意图,该子系统采用图2B技术,并使用两阶段(即发送输出时钟速率的一半)输入处理。所述输入数据的两个阶段提供至驱动器分片500的数字驱动器输入端,而且为“奇”信号或“偶”信号,其中,由时钟ck控制的多路复用器将所述奇偶信号交织成合并的输出流。所述输入数据的MSB部分控制两个并联的输出晶体管501/502/503和504/505/506,而LSB部分控制单个输出晶体管507/508/509。布尔逻辑对数据比特的状态进行解码,其中,输入“1”使得MSB的晶体管501和504或LSB的晶体管507导通,以将Runit电阻器连接至正电压Vref,从而导致正的输出偏移。输入“0”使得MSB的晶体管503和506或LSB的晶体管509导通,以将Runit电阻器连接至Vdd,从而导致负的输出偏移。在图2B实施例中,与驱动一个Runit电阻器的LSB电压切换电路(507/508/509)相比,驱动两个Runit电阻器的MSB电压切换电路(501/502/503或504/505/506)对输出线路产生双倍效果。
此外,还可通过消除控制信号“摆动”的方式将输出“1”和“0”均关闭,以使得晶体管502,505和508将电阻器Rterm驱动至恒电压节点vcm,共模电压值或空闲电压值。
多个输出驱动器分片
本领域技术人员可注意到的是,由于半导体工艺中存在800-900Ω/□的典型方块电阻,因此采用适于图2和图3电路的低芯片上电阻器值存在一定问题。其中,即使150Ω电阻器值所需的长宽比仍然为不可接受的2:11。此外,输出晶体管所需的相应较低的导通电阻(即,数十Ω数量级)仍使得其大至无法接受。
类似地,【Kojima】的教示内容也未能解决上述驱动晶体管阻抗(即集成电路芯片上的器件物理尺寸)问题,或在集成电路实施方式中实现精确且可实施的低值电阻器。
图4所示为对控制单个输出线路的图3输出驱动器子系统的多个实例。500的四个实例分别标记为分片1-4,而且除控制输入“摆动”之外,每一实例均为并行结构。其中,如果仅分片1允许“摆动”,则只有其驱动器继续生成坐标数据的偏移电压,而分片2,3和4仅提供“out”至vcm的电阻性连接。
如果所有分片上的所有Runit值完全相同,允许加入额外并行分片将使的最终输出偏移线性增大,这是因为公共输出节点“out”处的输出值受控于每个分片所产生的每个增量偏移的算术和。此由分片实现的一元加法允许输出摆幅通过四个分片调整至四个不同值。此并行分片方法还可实现Runit/Rterm比值的显着增大。当使用上例四个分片时,对例示50Ω线路阻抗进行驱动的所有分片的每个单独输出电阻器或其他电阻性元件所需的电阻增加至600Ω。当使用40个此类分片时,所需的电阻器值增加至6000Ω,此值可例如通过将易实现的5400Ω芯片上电阻器与合理的600Ω驱动晶体管阻抗相结合的方式获得。此多个分片的相同重复设计可实现布局的简单性及结果的一贯性。因此,此方法对集成电路的实施极其有益。
可注意到的是,增大不同分片内电阻性元件的电阻值(即Runit值)可实现更宽的调整范围;举例而言,二进制式的增大(例如,使得分片2的电阻元件值为分片1的电阻元件值的一半等)将使得四个分片可提供16个不同增大量的输出幅度。然而,如图2A实施例一样,此类方案在保持精确比率式匹配方面存在问题,从而可能使得生成的集合具有非单调性的调整结果。此类加权方案也没有解决与更高有效(即更低的R比值)输出分片内的低值电阻和晶体管阻抗相关的实施问题。因此,低阻抗传输线路驱动器的一种优选实施方式采用更大数量的相同分片,并通过一元加法将这些分片相互结合。
带发送均衡功能的多分片输出驱动器
作为前述各实施例的扩展,图5所示为由N个输出驱动器分片组成的一个驱动器分片组,这些驱动器分片同时工作,以对输出线路进行驱动。每个输出驱动器分片600包括一个用于每个MSB和LSB输出控制比特的高速4:1数字多路复用器,该多路复用器将四个编码数据阶段组合为全速率输出流,该输出流驱动三个相同的线路驱动器,其中,两个用于MSB,一个用于LSB,以生成单个输出。在此实施例中,所述高速4:1多路复用器实施为两个2:1多路复用级,其中,元件602为第一级的代表元件,603为第二级的代表元件。类似地,为了说明的目的,该实施例所示为使用CMOS线路驱动器驱动每个Runit电阻元件的示例。
图5中,所述高速4:1多路复用器的上游设有输入选择多路复用器或预驱动器切换电路(601为其例示元件),其允许从main[]或post[]输入总线或从TERMSEL输入中选择驱动器输入源。因此,合理配置任何给定分片的TAPSEL控制信号输入可使得该分片专用于main[]标记符号值的主流,post[]标记符号值的延迟流,或由TERMSEL输入表示的固定输出值的输出。由此可见,TERMSEL输入提供静态输入,当该静态输入被选择时将产生固定输出电压等固定输出值。
在一种例示实施方式中,作为配置或初始化过程的一部分,对上述分片的分配进行确定,因此相对于输出数据速率,所述TAPSEL输入选择多路复用器控制信号和/或TERMSEL输入的变化仅偶尔发生或发生频率较低。根据布局制约条件及系统设计首选项的不同,上述源自集中式配置系统的数据分片控制信号输入TERMSEL和TAPSEL可由对每个分片或分片子集执行类似功能的分布式控制寄存器、分布式控制处理器或状态机代替。
将不同数目个分片分配于相同的输入可实现对该输入的相对输出电平的控制。举例而言,如果针对来自main[]的输入,将40个分片设置为提供主系列信号电平,则线路端“out”的总输出摆幅为Vdd×Rterm/((Runit/40×3)+Rterm),而且该总摆幅可通过将所述分片的一部分配置为输出固定输出值(例如,Vss)而非数据的方式以2.5%(所述总摆幅的1/40)的递减量递减。此外,还可通过为部分或所有非数据分片选择不同固定输出值的方式对所述输出端的静态电压电平进行调节。
由此可见,通过将合理的第一数量的分片分配至数据输入可实现对输出信号幅度的控制,而将第二数量的分片分配至固定信号输入可实现对输出信号偏压或偏移电平的控制。由于总驱动器输出阻抗由所有输出驱动器和分片的并联Runit值的数目决定,因此可根据对所述输出进行主动驱动的分片数量,对面向通信信道的源阻抗进行调节。其他分片可利用禁用电路置于三态或高阻抗模式。禁用电路可例如包括可将分片输出与公共输出节点断开的开关,或者其可可以包括设于所述电压切换电路内的可将分片输出连接至高阻抗节点而非恒电压源的晶体管。将所选分片禁用的方式可增大信号发生器的输出阻抗,而且可用于对传输线路的阻抗进行匹配。
有限脉冲响应均衡
针对反射和符号间干扰(Inter-Symbol Interference,ISI)等通信信道的异常,可利用有限脉冲响应(Finite Impulse Response,FIR)滤波技术在传输线路驱动器内实施频率均衡,波形控制及其他预补偿。
FIR滤波表示时域中所期望的基于频率或基于波形的信号,具体而言为N个信号值随时间的加权和。对于发射器而言,所述N个信号值表示N个按时间顺序连续的信号值,例如,当前值为当前传输单位间隔的输出值,而其他N-1个值表示按时间顺序在前或在后的传输单位间隔的输出值。举例而言,一种FIR实施方式可将表示两个之前单位间隔,当前单位间隔以及三个后续单位间隔的加权值相互结合。
本发明的多分片结构适用于简单高效的FIR实施方式。如上所述,所生成输出信号的幅度受控于为输出主系列信号电平而分配的分片的数目,其对应于对信号输出实施缩放或乘法加权。类似地,将不同分片或分片组分配于延迟系列信号电平或提前系列信号电平等不同功能将产生与分片输出之和对应的均衡输出信号,其中,所述和值的分量为由每组分片数量加权后的加权分量。
信号发生器可包括对驱动器分片输入进行处理的均衡电路。此类均衡电路中的一种为图5所示的FIR先进先出(First-In-First-Out)电路,该电路包括例如由FIR滤波器提供的时钟延迟线路,该线路允许对按时间顺序处于当前发送数据之前或之后的数据进行访问,以实现发送均衡目的。根据所需延迟量和处理能力的不同,可将级联锁存器,数字移位寄存器,FIFO寄存器文件或FIFO回圈缓冲器作为所述数字延迟元件。
所述FIR FIFO还可包括数据对准功能,该功能支持多阶段处理结构,例如,其允许输入数据流与一个时钟阶段对准,以使其获得用于输出不同时钟阶段数据的正确定时。此类数据对准功能对本领域技术人员而言为公知功能,其允许例如根据1/4速率时钟阶段0接受由图5中标记为“编码输入”的输入流表示的较宽输入数据字,并同时输出分别定时至由输入至每个驱动器输出多路复用器的clk4()和clk2()信号的各种组合表示的阶段0,阶段1,阶段2和阶段3输出间隔的四个较窄数据字,其中,在与一个单位间隔相等的各增量中设有节拍延迟。为了便于理解,所述FIR FIFO功能还可以解释为等同于由工作于全单位间隔时钟速率的简单单阶段窄FIFO组成的“黑匣子”,而各输出节拍之后再由锁存器重新定时至与相应所需输出时钟阶段同步。
作为一个非限制性实施例,图5所示FIR FIFO接受对应于来自四个编码器处理阶段当中每个阶段的两个比特的坐标选择信息的8比特编码输入流,并生成标记为main[7,0]的发送数据的主节拍输出(对于四个阶段当中的每个阶段,均为每符号2比特)以及一个延迟节拍输出,该延迟节拍输出表示标记为post[7,0]的按时间顺序偏移后发送数据。如果继续考虑该实施例,则为post[]分配六个分片,并为main[]分配40个分片,所述按时间顺序偏移后的信号表示为主输出信号的15%,其为用于发送均衡或ISI消除的典型的预加重或后加重量。本领域技术人员将注意到的是,上述总信号幅度和加权均衡量均可通过选择不同的为生成主系列信号电平所分配的分片数量与为生成延迟系列信号电平和/或提前系列信号电平所分配的分片数量而得到调节。
所需的调节信息可通过信号路径的外部测试获得,或通过经返回信道返回发射器的接收器信息的反馈获得。
本领域技术人员可意识到的是,FIR实施方式中使用的加权因子通常由一个正项(即当时或当前单位间隔分量的项)以及多个与之前或之后单位间隔分量对应的负项组成。一种实施方式根据这些预期FIR参数对节拍极性进行直接布线,例如,在将提前节拍输出和/或延迟节拍输出反转的同时,不反转主节拍输出。另一实施方式提供对反转或未反转FIR FIFO节拍数据进行选择的能力,例如,在部分或所有FIR FIFO节拍输出路径中引入XOR元件等数字逆变电路。
另一实施方式通过纳入额外FIR FIFO节拍,额外输入多路复用器选项以及更大数目的分片将图5结构扩展,以支持带可调输出幅度和偏移电压的更为复杂的FIR发送均衡。在另一此类实施方式中,针对每个线路输出,为提前节拍所提供的提前符号值流分配多达七个分片,为主节拍所提供的主符号值流分配多达40个分片,并为延迟节拍所提供的延迟符号值流分配15个分片。此外,还可将额外分片(以及未处于有效使用状态的任何分片)设置为静态驱动器分片以提供静态或基线输出电压,或可选设置为无效或高阻抗状态,从而在有需要时逐步增大有效发送阻抗,以更好地匹配传输线路特性。类似地,使用如图3所示输出驱动器结构的替代实施方式可选择端接至vcm等恒电压节点,端接至gnd,端接至vref,或端接至高阻抗节点等其他节点,或端接至可配置分片行为等有效数据输出。
在图5所示实施方式中,每个分片均具有输入多路复用器601,该多路复用器允许任何分片输出主、延迟或终端电平。其他实施方式可采用更宽的输入多路复用器,以允许分片例如从额外FIR FIFO节拍中选择数据。在替代实施方式,可对部分或所有分片内的输入多路复用器进行简化,以使这些分片专用于特定或更加有限的功能范围或节拍组。此简化因消除了在特定应用中未有效使用的电路元件,所以可降低功耗和/或电路负载。
根据为表示编码信号所需要的输出电平数目的不同,每个分片可需要更多或更少输出多路复用器,驱动器晶体管及串联电阻器,而且可为每个驱动器提供更多或更少编码输入比特,以实现此类电平的选择。为了说明的目的,图5所示此类元件的结构如图2B所述。
偏斜补偿
如结合图1所描述的,图5等实施方式可在控制全线路速率输出定时的clk4和clk2线路内使用数字相位延迟器或内插器620。通过对服务于特定线路的分片的时钟的相位调节,可实现对信号传播偏斜的发送侧预补偿,其中,所述相位调节可通过将所述线路的信号相对于其他线路信号逐步提前或延迟的方式实现。如《Ulrich I》所述,此类发送侧调节有助于接收检测器的使用。上述各图作为信号传播偏斜调节的一种直白图示,示出了对提供至驱动输出线路的所有分片的时钟信号进行调节的内插器620。其他实施方式可在每个分片或分片子集的附近或内部采用此类时钟相位或内插调节,以实现对芯片本身内时钟传播延迟的补偿,或允许在驱动同一输出的各个分片之间对定时进行逐步调节。
所需的调节信息可通过信号路径的外部测试获得,或通过经返回信道返回发射器的接收器信息反馈获得。接收器偏斜的发射器补偿的另一示例见《Holden I》。
当FIR FIFO具有足够的延迟能力,而且分片输入多路复用器具有足够的灵活性时,可利用所表示FIFO延迟量与提供至其他线路的延迟量不同的主输出,不仅可将待发送至特定线路输出的编码信号相对于其他线路的偏移量设定为单位间隔的一部分,而且还可将该相对于其他线路的偏移量设定为大于一个单位间隔。例如,共存储八个历史节拍(即八个线路速率传输间隔)的FIR FIFO可配置为输出提前一个单位间隔的预输出,主输出,以及延迟一个单位间隔和延迟两个单位间隔的延迟输出,其中,所述预输出和延迟输出用于输出波形的FIR滤波。如果这些FIFO输出例如分别取自于第二,第三,第四和第五节拍,而且当服务于其他线路输出的同等FIFO使用第四,第五,第六和第七节拍时,则前一线路输出相对于后一线路输出提前(预偏斜补偿)两个单位间隔。之后,可通过将前一线路的分片的clk信号上的相位内插器的值设置为与后一线路的分片的clk信号上的相位内插器的值为不同值的方式,对上述两个单位间隔的偏移以单位间隔的另一比例为增量逐步调节。
实施方式
在至少一种实施方式中,一种信号发生器包括:具有延迟输入和多个输出节拍的数字延迟电路,该多个输出节拍至少包括主节拍和延迟节拍;并行设置的多个驱动器分片,每个驱动器分片具有一数字驱动器输入和一分片输出,每个驱动器分片运作为产生一信号,所述信号的信号电平由所述数字驱动器输入决定,其中,每个驱动器分片包括:多个具有第一端和第二端的电阻性元件,每个所述电阻性元件的第一端连接于所述驱动器分片输出;以及对于每个所述电阻性元件,还具有与该电阻性元件的第二端连接的电压切换电路,该电压切换电路设置为将所述电阻性元件的第二端选择性地连接至由至少两个恒电压节点组成的一组恒电压节点中的相应恒电压节点,所述电压切换电路由所述数字驱动器输入控制;一公共输出节点连接至所述分片输出;以及对于每个所述驱动器分片,还具有一预驱动器切换电路,该预驱动器切换电路运作为将相应驱动器分片的数字输入选择性地连接至一组驱动器输入源中的一个驱动器输入源,所述一组驱动器输入源至少包括所述主节拍和延迟节拍。
在至少一种实施方式中,所述信号发生器还包括与每个所述驱动器分片相连的禁用电路,其中,通过对该驱动器分片的选择性禁用对所述信号发生器的输出阻抗进行调节。
在至少一种实施方式中,所述一组驱动器输入源还包括静一态输入,其中,每个所述驱动器分片运作为当连接至该静态输入时可产生一静态信号。
在至少一种实施方式中,每个所述驱动器分片运作为产生至少三个信号电平。
在至少一种实施方式中,每个所述驱动器分片均具有与所述数字驱动器输入无关的输出阻抗。
在至少一种实施方式中,所述多个电阻性元件具有相同电阻。
在至少一种实施方式中,所述数字延迟电路还包括一提前节拍,其中,所述一组驱动器输入源包括该提前节拍,且所述主节拍相对于该提前节拍延迟一个发送间隔。
在至少一种实施方式中,所述延迟节拍相对于所述主节拍延迟一个发送间隔。
在至少一种实施方式中,所述信号发生器还包括所述延迟节拍和驱动器分片之间的数字逆变电路。
在至少一种实施方式中,每个所述驱动器分片还包括数字逆变电路,该数字逆变电路运作为当所述驱动器分片的数字输入连接至所述延迟节拍时,将所述数字驱动器输入反转。
在至少一种实施方式中,所述信号发生器还包括至少40个驱动器分片。
在至少一种实施方式中,所述数字延迟电路还包括一先进先出缓冲器。
在至少一种实施方式中,所述预驱动器切换电路还包括一多路复用电路。
如图7所示,一种信号发生器的操作方法700包括:在步骤702中,通过选择至少第一数目的多个驱动器分片以提供主信号输出并选择第二数目的多个驱动器分片以提供延迟信号输出的方式对所述信号发生器进行配置;在步骤704中,从输入符号值流中获取主符号值流;在步骤706中,将主符号值流提供于所述第一数目的多个驱动器分片,并运作所述第一数目的多个驱动器分片,以产生由所述主符号值流决定的主系列信号电平,其中,所述主系列信号电平的产生包括将与所述第一数目的多个驱动器分片中的相应驱动器分片连接的相应电阻性元件选择性地连接至选自一组恒电压节点的相应恒电压节点,该恒电压节点的选择基于所述主符号值流;在步骤708中,从所述输入符号值流获取延迟符号值流;在步骤710中,将该延迟符号值流提供于所述第二数目的多个驱动器分片,并运作所述第二数目的多个驱动器分片,以产生由所述延迟符号值流决定的一延迟系列信号电平,其中,所述延迟系列信号电平的产生包括将与所述第二数目的多个驱动器分片中的相应驱动器分片连接的相应电阻性元件选择性地连接至选自所述一组恒电压节点的相应恒电压节点,该恒电压节点的选择基于所述延迟符号值流;以及在步骤712中,将所述主信号电平流和延迟信号电平流相结合,以在公共输出节点产生均衡输出信号。
在至少一种实施方式中,基于连接至所述信号发生器的传输信道的信道特性来选择所述第一数目的多个驱动器分片和所述第二数目的多个驱动器分片。
在至少一种实施方式中,对所述信号发生器进行配置还包括选择一定数目个无效驱动器分片,其中,该无效驱动器分片的数目选择为实现所述信号发生器的输出阻抗的调节。
在至少一种实施方式中,对所述信号发生器进行配置还包括选择一定数目个静态驱动器分片,其中,该静态驱动器分片的数目选择为实现所述信号发生器的静态输出信号的调节。
在至少一种实施方式中,所述主符号值流和延迟符号值流的获取实施为使得所述延迟符号值流相对于所述主符号值流延迟一个发送间隔。
在至少一种实施方式中,对所述信号发生器进行配置还包括选择一第三数目的多个驱动器分片以提供预信号输出;还包括:从所述输入符号值流获取提前符号值流,并使得所述主符号值流相对于该提前符号值流延迟一个发送间隔,以及将该提前符号值流提供至所述第三数目的多个驱动器分片,并运作所述第三数目的多个驱动器分片,以产生由所述提前符号值流决定的提前系列信号电平;其中,所述结合包括将所述第一,第二和第三系列信号电平相结合,以产生所述均衡输出信号。
在至少一种实施方式中,所述延迟信号电平流相对于所述主信号电平流反转。
在至少一种实施方式中,一种多线路信号发生器包括:编码器,该编码器运作为可将二进制数据输入至少映射至第一编码器输出端处的第一符号值以及第二编码器输出端处的第二符号值;多个驱动器分片的每个驱动器分片具有一数字驱动器输入和一分片输出,每个驱动器分片运作为产生一信号,所述信号的信号电平由所述数字驱动器输入决定,其中,每个驱动器分片包括:多个具有第一端和第二端的电阻性元件,每个所述电阻性元件的第一端连接于所述驱动器分片输出;以及对于每个所述电阻性元件,还具有与该电阻性元件的第二端连接的电压切换电路,该电压切换电路设置为将所述电阻性元件的第二端选择性地连接至由至少两个恒电压节点组成的一组恒电压节点中的相应恒电压节点,所述电压切换电路由所述数字驱动器输入控制;第一公共输出节点,其中,该第一公共输出节点连接至所述驱动器分片的第一子集的分片输出;第二公共输出节点,其中,该第二公共输出节点连接至所述驱动器分片的第二子集的分片输出;第一均衡电路,该第一均衡电路可选择性地将所述第一编码器输出端与所述驱动器分片的第一子集的数字驱动器输入相连接;以及第二均衡电路,该第二均衡电路可选择性地将所述第二编码器输出端与所述驱动器分片的第二子集的数字驱动器输入相连接。
在至少一种实施方式中,所述多线路信号发生器还包括一延迟元件,该延迟元件运作为延迟所述驱动器分片的第一子集和第二子集当中的至少一个子集的分片输出。
在至少一种实施方式中,所述第一均衡电路运作为将所述第一符号值的延迟形式提供至所述第一子集的驱动器分片当中的至少部分驱动器分片,所述第二均衡电路运作为将所述第二符号值的延迟形式提供至所述第二子集的驱动器分片当中的至少部分驱动器分片。
在至少一种实施方式中,所述多线路信号发生器在所述第一和第二子集中均包括至少40个驱动器分片。
在至少一种实施方式中,所述多个电阻性元件当中的每个电阻性元件的阻抗至少为与所述公共输出节点相对应的线路阻抗的至少12倍。在至少一种实施方式中,每个所述电阻性元件的阻抗至少为600Ω。在至少一种实施方式中,每个所述电阻性元件的阻抗至少为6000Ω。
在所述方法的至少一种实施方式中,所述相应电阻性元件的阻抗至少为与所述公共输出节点相对应的线路阻抗的至少12倍。在至少一种实施方式中,所述相应电阻性元件的阻抗至少为600Ω。在另一实施方式中,所述相应电阻性元件的阻抗至少为6000Ω。
在所述多线路信号发生器的至少一种实施方式中,所述多个电阻性元件当中的每个电阻性元件的阻抗至少为与公共输出节点相对应的线路阻抗的至少12倍。在至少一种实施方式中,每个所述电阻性元件的阻抗至少为600Ω。在至少一种实施方式中,每个所述电阻性元件的阻抗至少为6000Ω。
本文实施例描述了芯片间通信用阻抗匹配并联传输互连线所载向量信令码的使用。然而,这些例示性的细节不应视为对所述本发明范围的限制。本申请中所公开的方法同样适用于其他互连拓扑结构以及其他通信介质,这些通信介质包括光学性、电容性、电感性以及无线通信,并可依赖于所述发明的任何特性,这些特性包括但不限于通信协议,信令方法,和物理接口特征。因此,“电压”和“信号水平”等描述性词语应视为包括其在其他度量系统中的同等概念,如“电流”、“光强”、“射频调制”等。本文所使用的“信号”一词包括可传送信息的物理现象的任何适用形态和/或属性。此外,由此类信号传送的信息可以为有形的非暂时性信息。
Claims (15)
1.一种信号发生器,其特征在于,所述信号发生器包括:
具有一延迟输入和多个输出节拍的数字延迟电路,该多个输出节拍至少包括一主节拍和一延迟节拍;
并行设置的多个驱动器分片,每个驱动器分片具有一数字驱动器输入和一分片输出,每个驱动器分片运作为产生一信号,所述信号的信号电平由所述数字驱动器输入决定,其中,每个驱动器分片包括:
多个具有第一端和第二端的电阻性元件,每个所述电阻性元件的第一端连接于所述分片输出;以及
对于每个所述电阻性元件,还具有与该电阻性元件的第二端连接的电压切换电路,该电压切换电路设置为将所述电阻性元件的第二端选择性地连接至由至少两个恒电压节点组成的一组恒电压节点中的相应恒电压节点,所述电压切换电路由所述数字驱动器输入控制;
连接至所述分片输出的一公共输出节点;以及
对于每个所述驱动器分片,还具有一预驱动器切换电路,该预驱动器切换电路运作为将相应驱动器分片的数字输入选择性地连接至一组驱动器输入源中的一个驱动器输入源,所述一组驱动器输入源至少包括所述主节拍和所述延迟节拍。
2.如权利要求1所述的信号发生器,其特征在于,还包括与每个所述驱动器分片相连的禁用电路,通过对所述驱动器分片的选择性禁用对所述信号发生器的输出阻抗进行调节。
3.如权利要求1所述的信号发生器,其特征在于,所述一组驱动器输入源还包括一静态输入,且每个所述驱动器分片运作为当连接至所述静态输入时产生一静态信号。
4.如权利要求1所述的信号发生器,其特征在于,每个所述驱动器分片均具有与所述数字驱动器输入无关的输出阻抗。
5.如权利要求1所述的信号发生器,其特征在于,所述数字延迟电路还包括一提前节拍,其中,所述一组驱动器输入源包括所述提前节拍,且所述主节拍相对于所述提前节拍延迟一个发送间隔。
6.如权利要求1所述的信号发生器,其特征在于,还包括所述延迟节拍和所述驱动器分片之间的数字逆变电路。
7.如权利要求1所述的信号发生器,其特征在于,每个所述驱动器分片还包括数字逆变电路,所述数字逆变电路运作为当所述驱动器分片的数字输入连接至所述延迟节拍时,将所述数字驱动器输入反转。
8.如权利要求1所述的信号发生器,其特征在于,所述数字延迟电路包括一先进先出缓冲器。
9.一种信号发生器的操作方法,其特征在于,所述方法包括:
通过选择至少第一数目的多个驱动器分片以提供一主信号输出并选择第二数目的多个驱动器分片以提供一延迟信号输出的方式对所述信号发生器进行配置;
从输入符号值流中获取主符号值流;
将主符号值流提供于所述第一数目的多个驱动器分片,并运作所述第一数目的多个驱动器分片,以产生由所述主符号值流决定的一主系列信号电平,其中,所述主系列信号电平的产生包括将与所述第一数目的多个驱动器分片中的相应驱动器分片连接的相应电阻性元件选择性地连接至选自一组恒电压节点的相应恒电压节点,该恒电压节点的选择基于所述主符号值流;
从所述输入符号值流中获取延迟符号值流;
将该延迟符号值流提供于所述第二数目的多个驱动器分片,并运作所述第二数目的多个驱动器分片,以产生由所述延迟符号值流决定的一延迟系列信号电平,其中,所述延迟系列信号电平的产生包括将与所述第二数目的多个驱动器分片中的相应驱动器分片连接的相应电阻性元件选择性地连接至选自所述一组恒电压节点的相应恒电压节点,该恒电压节点的选择基于所述延迟符号值流;以及
将所述主信号电平流和延迟信号电平流相结合,以在一公共输出节点产生均衡输出信号。
10.如权利要求9所述的方法,其特征在于,基于连接至所述信号发生器的传输信道的信道特性来选择所述第一数目的多个驱动器分片和所述第二数目的多个驱动器分片。
11.如权利要求9所述的方法,其特征在于,对所述信号发生器进行配置还包括选择一定数目个无效驱动器分片,该无效驱动器分片的数目选择为实现所述信号发生器的输出阻抗的调节。
12.如权利要求9所述的方法,其特征在于,对所述信号发生器进行配置还包括选择一定数目个静态驱动器分片,该静态驱动器分片的数目选择为实现所述信号发生器的静态输出信号的调节。
13.如权利要求9所述的方法,其特征在于,所述主符号值流和延迟符号值流的获取实施为使得所述延迟符号值流相对于所述主符号值流延迟一个发送间隔。
14.如权利要求9所述的方法,其特征在于:
对所述信号发生器进行配置还包括选择一第三数目的多个驱动器分片以提供预信号输出;
还包括:
从所述输入符号值流中获取提前符号值流,并使得所述主符号值流相对于该提前符号值流延迟一个发送间隔;以及
将该提前符号值流提供至所述第三数目的多个驱动器分片,并运作所述第三数目的多个驱动器分片,以产生由所述提前符号值流决定的一提前系列信号电平;
其中,所述结合包括将所述第一,第二和第三系列信号电平相结合,以产生所述均衡输出信号。
15.如权利要求9所述的方法,其特征在于,所述延迟信号电平流相对于所述主信号电平流反转。
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Also Published As
Publication number | Publication date |
---|---|
US11716226B2 (en) | 2023-08-01 |
US20220217024A1 (en) | 2022-07-07 |
US20150381232A1 (en) | 2015-12-31 |
EP3787185B1 (en) | 2024-01-03 |
WO2015200506A1 (en) | 2015-12-30 |
US9917711B2 (en) | 2018-03-13 |
US20190028307A1 (en) | 2019-01-24 |
EP3138196A1 (en) | 2017-03-08 |
CN110198165B (zh) | 2023-12-29 |
CN110198165A (zh) | 2019-09-03 |
US10404500B2 (en) | 2019-09-03 |
US9112550B1 (en) | 2015-08-18 |
US20190394070A1 (en) | 2019-12-26 |
US10091033B2 (en) | 2018-10-02 |
EP3138196B1 (en) | 2020-09-09 |
US11283654B2 (en) | 2022-03-22 |
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US20180205580A1 (en) | 2018-07-19 |
US20210014089A1 (en) | 2021-01-14 |
US20170118048A1 (en) | 2017-04-27 |
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