CN1065658C - 用于制造半导体器件的电容器的方法及电容器 - Google Patents
用于制造半导体器件的电容器的方法及电容器 Download PDFInfo
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Abstract
一种用于高度集成的半导体器件的电容器，以下列方法依次进行下列步骤：设置半导体基片；在半导体基片上形成钌-铂膜；对钌-铂膜进行热处理以在钌-铂膜上生成钌-铂氧化物；及在钌-铂氧化物上形成介电膜和电导层。
Description
本发明涉及一种半导体器件的电容器，特别是涉及适用于高集成度的半导体器件的电容器。而且，本发明还涉及用于制造该电容器结构的方法。
随着半导体器件被高度集成，元件在尺寸上变得更小，而难于保证与存储电极的表面积成比例的足够存储电容量。尤其是，在DRAM器件的情况下，其单元元件由一个MOS晶体管和一个电容器组成，高集成度的关键点是提高电容器的存储电容量，而电容器占据了芯片中的很大面积，同时要减小由电容器所占据的面积。
已经建议了各种技术来提高由下式所代表的电容器的存储电容量；
其中，C代表电容器的存储电容量，Eo代表真空介电常数，Er代表介电膜的介电常数，A代表电容器的面积，T代表电容器的厚度。
例如，具有高介电常数的介电膜由薄BST((Ba，Sr)TiO3)或PZT(Pb(ZryTix)O3)膜形成，每种膜都具有高介电常数Er，使得半导体器件可被高度集成。但是，该技术存在下述缺陷：在构成电容器的下电极的表面上产生了小丘针孔，而使该器件的电性能不稳定以及使再现性变坏。
为了克服该缺陷，提出了另一项技术：电容器由下电极和上电极组成，两者都由氧化钌(RuO2)或铂(Pt)形成，并经过热处理使之稳定。
当使用氧化钌作电极时，在热处理中会在介电膜和上电极之间产生应力。进而，由于氧或硅从上和／或下电极扩散至介电膜中而使介电膜的特性变坏。另一个缺点是氧化钌膜形成较慢。
在上和下电极由铂形成的情况下，在热处理中在200-300℃下会在铂的表面上形成硅或硅化物，而导致大大地提高了漏电流。这样，不但电极的电性能变差，而且对绝缘膜的粘合性变得更差。而且，铂同样会因应力而产生小丘，并且薄膜的特性会随着时间的推移而降低。
在“Integrated Ferroelectrics，1995，Vol．8，P151-163，H．N．A1-Shareef”中公开的形成电极的技术，就是为了解决上述问题，并保持氧化钌和铂的优点。但是，上述现有的技术仍存在下列缺点：电容器的制造方法非常复杂，而使半导体器件的可靠性降低。而且，该复杂的方法也提高了生产成本，降低了生产率。
因而，上述现有的半导体器件的电容器的制造技术已不适合于半导体器件的高度集成。
本发明的目的是为了克服现有技术中存在的上述问题，而提供一种半导体器件的电容器结构，对于半导体器件的高集成度具有足够高的电容值。
本发明的另一个目的是提供一种用于制造电容器结构的方法。
根据本发明的一个方案，用于制造半导体器件的电容器的方法包括依次进行的下列步骤：设置一个半导体基片；在该半导体基片上形成钌-铂膜；对该钌-铂膜进行热处理以在该钌-铂膜上生长出氧化钌-铂；在该氧化钌-铂上形成介电膜和导电层。
根据本发明的另一个方案，用于制造半导体器件的电容器的方法包括下列依次进行的步骤：设置一个半导体基片；在所述半导体基片上形成下绝缘层，所述下绝缘层具有从暴露的所述半导体基片的预定面积中穿过的接触孔；在所述下绝缘层的所述接触孔中形成一接触栓(Contact plug)；在所述接触栓和所述下绝缘层上形成钛膜和氮化钛膜；在所述氮化钛膜上形成钌-铂膜；对所述钌-铂膜进行热处理以在所述钌-铂膜上生长出氧化钌-铂；对所述氧化钌-铂、所述钌-铂膜、所述氧化钛和钛膜进行刻图；在形成的结构上形成介电膜和平板电极。
根据本发明的另一方案，半导体器件的电容器包括：在半导体基片上的一个下电极，一个介电膜和一个上电极，其中所述下电极包括钌-铂膜和氧化钌-铂。
下面参照附图对实施例进行的描述，将使本发明的其他目的和方案变得更明确，其中图1至7是表示根据本发明的用于制造半导体器件的电容器的方法的截面图。
参照附图将会更好地理解本发明优选实施例的使用，其中相同的标号分别用于相同或相应部分。
如图1所示，下绝缘层13首先形成在半导体基片11上，其具有使由元件隔离膜(未示出)、栅氧化膜(未示出)和栅极(未示出)组成的全部结构平面化的目标。在形成该栅极之后，可以形成位线。下绝缘层13由具有优良流动性的绝缘材料制成。
然后，使用接触掩模(未示出)，通过有选择地使下绝缘层13露出以形成穿过半导体基片11的预定区域的接触孔15，即使杂质注入区露出，来进行刻蚀处理。
接着，在包括下绝缘层13和接触孔15的所形成的结构上，淀积多晶硅的覆盖层，然后再次刻蚀以在接触孔15中形成接触栓多晶硅膜17。
图2是在钛膜19和氮化钛膜21依次形成在其结构上之后的截面，接着使钌-铂膜23淀积在氮化钛膜21上。钛膜19具有约100-300埃的厚度，而氮化钛膜21具有约200-400埃的厚度。给钌-铂膜23提供一个以2000至5000埃范围的厚度。溅射处理被用于钌-铂膜23的淀积，其中钌和铂同时间用作为靶。该用于钌-铂膜23的淀积处理具有使用DC或RF磁源的溅射的优点。该淀积处理最好是在1mTorr-100Torr下以50-5000瓦的功率在室温至700℃的基片温度范围内进行1-10分钟。作为气氛，可使用氮气、氩气或氧气。
然后在氧气气氛中进行约0．5-2小时的热处理，以在钌-铂膜23的表面上生成出氧化物25，如图3所示那样。用RuxOyPtz(X、Y和Z代表具有X+Y+Z=1的组成率)来代表该钌-铂氧化物25。在约500-850℃的温度下进行热处理。
图4是在其结构上形成光敏膜图形27之后的截面图。为此，光敏膜(未示出)形成在所形成的结构上并且使用存储电极掩模(未示出)来进行刻蚀。
图5是在使用光敏膜图形27作为掩模之后的截面图，依次对钌-铂氧化物25、钌-铂膜23、氮化钛膜21和钛膜19进行刻蚀以分别形成钌-铂氧化物图形25a-钌-铂图形23a、氮化钛图形21a和钛膜图形19a，然后除去光敏膜图形27。
然后，如图6所示，在所形成的结构上以一定的厚度形成具有高介电常数的介电膜29。作为介电膜29，使用具有高介电常数的绝缘膜，例如BST或BIT。介电膜29最好其有约300-600埃的厚度。
最后，在介电膜29上淀积一导电层以形成一平板电极31，由此产生对高集成度的半导体器件具有足够高电容量的电容器。
如上述那样，由于钌和铂不形成复杂的组合结构而是同时作为用于淀积的靶，就能简化制造。进而，根据本发明，能够容易地控制钌和铂的组合，因而就能调整介电膜的特性。而且，钌-铂靶使得氧气氛可被用于形成钌-铂氧化物的下电极，即，存储电极。
因而，根据本发明半导体器件的电性能和可靠性可以得到大大改善，并最终提供半导体器件的高集成度的基础。
本发明是以说明的方式被描述，应当知道：所使用的术语仅是用于说明而不是限定。
可以根据上述教导进行本发明的多种改型和变化。应当清楚：在权利要求所限定的范围中，可以用除上述特例之外的方法实施。
Claims (21)
1．一种用于制造半导体器件的电容器的方法，包括下列依次进行的步骤：
设定一个半导体基片；在半导体基片上形成钌-铂膜；
对钌-铂膜进行热处理以在钌-钯膜上生成出钌-铂氧化物；及
在钌-铂氧化物膜上形成介电膜和导电层。
2．根据权利要求1的方法，进一步下列步骤：在半导体基片与钌-铂膜之间形成钛膜和氮化钛膜。
3．根据权利要求1的方法，其中以溅射处理形成所述钌-铂膜，其中钌-铂同时作为靶。
4．根据权利要求3的方法，其中用DC溅射处理在室温到700℃以50-5000瓦的功率在1mTorr至100Torr的淀积压力下持续1-10分钟地形成所述钌-铂膜。
5．根据权利要求3的方法，其中用RF溅射处理在室温至700℃以50-5000瓦的功率在1mTorr至100Torr的淀积压力下持续1-10分钟地形成所述钌-铂膜。
6．根据权利要求1的方法，其中所述热处理步骤在500-850℃下进行0．5-2小时。
7．根据权利要求1的方法，进一步包括下列依次进行的步骤：
在所述半导体基片上形成下绝缘层，所述下绝缘层具有穿过暴露的所述半导体器件的预定区域的接触孔；
在所述下绝缘层的所述接触孔中形成接触栓；
依次在所述接触栓和所述下绝缘层上形成钛膜和氮化钛膜；
对所述钌-铂氧化物、所述钌-铂膜所述氮化钛和钛膜进行刻图。
8．根据权利要求7的方法，其中所述下绝缘层由具有优良流动性的绝缘材料形成。
9．根据权利要求7的方法，其中所述接触栓由多晶硅形成。
10．根据权利要求7的方法，其中所述钛膜形成为100-300埃的厚度。
11．根据权利要求7的方法，其中所述氮化钛膜形成为200-400埃的厚度。
12．根据权利要求7的方法，其中以溅射处理所述钌-铂膜，其中钌-铂膜同时作为一个靶。
13．根据权利要求12的方法，其中用DC溅射处理在室温至700℃以50-5000瓦的功率在1mTorr至100Torr的淀积压力下持续1-10分钟地形成所述钌-铂膜。
14．根据权利要求12的方法，其中用RF溅射处理在室温至700℃以50-5000瓦的功率在1mTorr至100Torr的淀积压力下持续1-10分钟地形成所述钌-铂膜。
15．根据权利要求7的方法，其中在约500-850℃下进行0．5-2小时的所述热处理步骤。
16．根据权利要求7的方法，其中所述介电膜形成为300-600埃的厚度。
17．一种半导体器件的电容器，包括：在半导体基片上的下电极，介电膜和上电极，其中所述下电极包括钌-铂和钌-铂氧化物。
18．根据权利要求17的电容器，其中所述下电极进一步包括钛膜和氮化钛膜。
19．根据权利要求17的电容器，其中所述下电极穿过一接触栓而同所述半导体基片电接触。
20．根据权利要求17的电容器，其中用DC溅射处理在室温至700℃以50-5000瓦的功率在1mTorr至100Torr的淀积压力下持续1-10分钟地形成所述钌-铂膜。
21．权利要求17的电容器，其中用RF溅射处理在室温至700℃以50-5000瓦的功率在1mTorr至100Torr的淀积压力下持续1-10分钟地形成所述钌-铂膜。
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| KR1019950045483A KR100200299B1 (ko) | 1995-11-30 | 1995-11-30 | 반도체 소자 캐패시터 형성방법 |
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| KR95-45483 | 1995-11-30 |
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| CN96120755A Expired - Fee Related CN1065658C (zh) | 1995-11-30 | 1996-11-28 | 用于制造半导体器件的电容器的方法及电容器 |
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| US (1) | US5714402A (zh) |
| JP (1) | JP2820930B2 (zh) |
| KR (1) | KR100200299B1 (zh) |
| CN (1) | CN1065658C (zh) |
| DE (1) | DE19649670C2 (zh) |
| GB (1) | GB2307789B (zh) |
| TW (1) | TW454294B (zh) |
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| US6243691B1 (en) * | 1996-03-29 | 2001-06-05 | Onsale, Inc. | Method and system for processing and transmitting electronic auction information |
| US5930584A (en) * | 1996-04-10 | 1999-07-27 | United Microelectronics Corp. | Process for fabricating low leakage current electrode for LPCVD titanium oxide films |
| JP3452763B2 (ja) * | 1996-12-06 | 2003-09-29 | シャープ株式会社 | 半導体記憶装置および半導体記憶装置の製造方法 |
| KR100244251B1 (ko) * | 1997-06-19 | 2000-02-01 | 김영환 | 반도체 소자의 커패시터 제조 방법 |
| JP3484324B2 (ja) | 1997-07-29 | 2004-01-06 | シャープ株式会社 | 半導体メモリ素子 |
| JP3319994B2 (ja) * | 1997-09-29 | 2002-09-03 | シャープ株式会社 | 半導体記憶素子 |
| US6165833A (en) * | 1997-12-19 | 2000-12-26 | Micron Technology, Inc. | Semiconductor processing method of forming a capacitor |
| US6911371B2 (en) | 1997-12-19 | 2005-06-28 | Micron Technology, Inc. | Capacitor forming methods with barrier layers to threshold voltage shift inducing material |
| KR19990057857A (ko) * | 1997-12-30 | 1999-07-15 | 김영환 | 반도체 장치의 캐패시터 형성 방법 |
| US6025624A (en) * | 1998-06-19 | 2000-02-15 | Micron Technology, Inc. | Shared length cell for improved capacitance |
| KR100301371B1 (ko) * | 1998-07-03 | 2001-10-27 | 윤종용 | 반도체메모리장치및그의제조방법 |
| US6323081B1 (en) * | 1998-09-03 | 2001-11-27 | Micron Technology, Inc. | Diffusion barrier layers and methods of forming same |
| DE19858357A1 (de) * | 1998-12-17 | 2000-06-29 | Siemens Ag | Mikroelektronische Struktur sowie Verfahren zu deren Herstellung |
| DE19959711A1 (de) * | 1999-12-10 | 2001-06-21 | Infineon Technologies Ag | Verfahren zur Herstellung einer strukturierten Metallschicht |
| US6214661B1 (en) * | 2000-01-21 | 2001-04-10 | Infineon Technologoies North America Corp. | Method to prevent oxygen out-diffusion from BSTO containing micro-electronic device |
| US6727140B2 (en) * | 2001-07-11 | 2004-04-27 | Micron Technology, Inc. | Capacitor with high dielectric constant materials and method of making |
| KR20030025671A (ko) * | 2001-09-22 | 2003-03-29 | 주식회사 하이닉스반도체 | 커패시터의 제조방법 |
| US7655556B2 (en) | 2007-03-23 | 2010-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures for semiconductor devices |
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| EP0495114A1 (en) * | 1990-07-26 | 1992-07-22 | Seiko Epson Corporation | Semiconductor device |
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| WO1991016731A1 (en) * | 1990-04-24 | 1991-10-31 | Seiko Epson Corporation | Semiconductor device having ferroelectric material and method of producing the same |
| KR100266046B1 (ko) * | 1990-09-28 | 2000-09-15 | 야스카와 히데아키 | 반도체장치 |
| EP0490288A3 (en) * | 1990-12-11 | 1992-09-02 | Ramtron Corporation | Process for fabricating pzt capacitors as integrated circuit memory elements and a capacitor storage element |
| US5262920A (en) * | 1991-05-16 | 1993-11-16 | Nec Corporation | Thin film capacitor |
| JP2690821B2 (ja) * | 1991-05-28 | 1997-12-17 | シャープ株式会社 | 半導体装置 |
| US5142437A (en) * | 1991-06-13 | 1992-08-25 | Ramtron Corporation | Conducting electrode layers for ferroelectric capacitors in integrated circuits and method |
| US5254217A (en) * | 1992-07-27 | 1993-10-19 | Motorola, Inc. | Method for fabricating a semiconductor device having a conductive metal oxide |
| US5335138A (en) * | 1993-02-12 | 1994-08-02 | Micron Semiconductor, Inc. | High dielectric constant capacitor and method of manufacture |
| US5381302A (en) * | 1993-04-02 | 1995-01-10 | Micron Semiconductor, Inc. | Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same |
| US5407855A (en) * | 1993-06-07 | 1995-04-18 | Motorola, Inc. | Process for forming a semiconductor device having a reducing/oxidizing conductive material |
| JPH0730077A (ja) * | 1993-06-23 | 1995-01-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP3319869B2 (ja) * | 1993-06-24 | 2002-09-03 | 三菱電機株式会社 | 半導体記憶装置およびその製造方法 |
| JP2682392B2 (ja) * | 1993-09-01 | 1997-11-26 | 日本電気株式会社 | 薄膜キャパシタおよびその製造方法 |
| JPH0794680A (ja) * | 1993-09-22 | 1995-04-07 | Fujitsu Ltd | 半導体装置の製造方法 |
| US5489548A (en) * | 1994-08-01 | 1996-02-06 | Texas Instruments Incorporated | Method of forming high-dielectric-constant material electrodes comprising sidewall spacers |
| US5554564A (en) * | 1994-08-01 | 1996-09-10 | Texas Instruments Incorporated | Pre-oxidizing high-dielectric-constant material electrodes |
| US5622893A (en) * | 1994-08-01 | 1997-04-22 | Texas Instruments Incorporated | Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes |
| US5566045A (en) * | 1994-08-01 | 1996-10-15 | Texas Instruments, Inc. | High-dielectric-constant material electrodes comprising thin platinum layers |
| MX9602406A (es) * | 1994-10-04 | 1997-03-29 | Philips Electronics Nv | Mecanismo semiconductor que comprende un elemento de memoria ferroelectrica con un electrodo inferior provisto de una barrera de oxigeno. |
| US5555486A (en) * | 1994-12-29 | 1996-09-10 | North Carolina State University | Hybrid metal/metal oxide electrodes for ferroelectric capacitors |
| KR0144932B1 (ko) * | 1995-01-26 | 1998-07-01 | 김광호 | 반도체 장치의 캐패시터 및 그 제조방법 |
| US5573979A (en) * | 1995-02-13 | 1996-11-12 | Texas Instruments Incorporated | Sloped storage node for a 3-D dram cell structure |
| KR100199346B1 (ko) * | 1995-04-04 | 1999-06-15 | 김영환 | 반도체 소자의 전하저장전극 형성방법 |
| KR0147640B1 (ko) * | 1995-05-30 | 1998-08-01 | 김광호 | 반도체 장치의 커패시터 및 그 제조방법 |
| JPH09102591A (ja) * | 1995-07-28 | 1997-04-15 | Toshiba Corp | 半導体装置及びその製造方法 |
-
1995
- 1995-11-30 KR KR1019950045483A patent/KR100200299B1/ko active IP Right Grant
-
1996
- 1996-11-26 TW TW085114568A patent/TW454294B/zh not_active IP Right Cessation
- 1996-11-27 US US08/757,246 patent/US5714402A/en not_active Expired - Lifetime
- 1996-11-28 CN CN96120755A patent/CN1065658C/zh not_active Expired - Fee Related
- 1996-11-28 GB GB9624828A patent/GB2307789B/en not_active Expired - Fee Related
- 1996-11-29 DE DE19649670A patent/DE19649670C2/de not_active Expired - Fee Related
- 1996-12-02 JP JP8321927A patent/JP2820930B2/ja not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0495114A1 (en) * | 1990-07-26 | 1992-07-22 | Seiko Epson Corporation | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2820930B2 (ja) | 1998-11-05 |
| US5714402A (en) | 1998-02-03 |
| GB9624828D0 (en) | 1997-01-15 |
| TW454294B (en) | 2001-09-11 |
| GB2307789B (en) | 2000-03-22 |
| GB2307789A (en) | 1997-06-04 |
| DE19649670A1 (de) | 1997-06-05 |
| DE19649670C2 (de) | 2002-09-05 |
| JPH09199687A (ja) | 1997-07-31 |
| CN1158498A (zh) | 1997-09-03 |
| KR970030779A (ko) | 1997-06-26 |
| KR100200299B1 (ko) | 1999-06-15 |
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