CN106463420A - 电力用半导体装置及其制造方法 - Google Patents

电力用半导体装置及其制造方法 Download PDF

Info

Publication number
CN106463420A
CN106463420A CN201480078993.2A CN201480078993A CN106463420A CN 106463420 A CN106463420 A CN 106463420A CN 201480078993 A CN201480078993 A CN 201480078993A CN 106463420 A CN106463420 A CN 106463420A
Authority
CN
China
Prior art keywords
power semiconductor
metallic plate
stage portion
semiconductor device
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480078993.2A
Other languages
English (en)
Other versions
CN106463420B (zh
Inventor
川岛裕史
坂本健
鹿野武敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN106463420A publication Critical patent/CN106463420A/zh
Application granted granted Critical
Publication of CN106463420B publication Critical patent/CN106463420B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48108—Connecting bonding areas at different heights the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H01L2224/49052—Different loop heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/495—Material
    • H01L2224/49505—Connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

准备引线框，在其芯片焊盘(3)之上固接电力用半导体元件(5)。在芯片焊盘(3)的下表面隔着绝缘膜(9)而固接金属板(8)。在下模具(12a)与上模具(12b)之间的腔室(13)内配置内部引线(1a)、芯片焊盘(3)、电力用半导体元件(5)、绝缘膜(9)以及金属板(8)，利用封装树脂(10)进行封装。下模具(12a)在内部引线(1a)的下方具有设置于腔室(13)的底面的台阶部(14)。台阶部(14)的上表面的高度比在腔室(13)内配置的电力用半导体元件(5)的上表面的高度高。在将封装树脂(10)注入至腔室(13)内时，金属板(8)的下表面与腔室(13)的底面相接触，使封装树脂(10)从台阶部(14)的上方朝向电力用半导体元件(5)的上表面而流动至下方。

Description

电力用半导体装置及其制造方法
技术领域
本发明涉及一种利用封装树脂将电力用半导体元件进行封装的电力用半导体装置及其制造方法。
背景技术
在半导体装置之中，电力用半导体装置被用于在铁路车辆、混合动力车、电动汽车等车辆、家电设备、工业用机器等对较大的电力进行控制、整流。在使用时电力用半导体元件会发热，因此对电力用半导体装置要求元件的散热性。另外，由于施加大于或等于几百V的高电压，因此需要与装置外部绝缘。
在这里，IPM(Intelligent Power Module)为电力用半导体元件和控制用半导体元件成为一体后的模块。在配线材料使用引线框的情况下，电力用半导体元件和控制用半导体元件大多安装于被物理地切分开的芯片焊盘，然后利用金属细线等进行电连接。由于电力用半导体元件流通大电流，因此发热大，要求作为模块来说的散热性。
作为散热构造的一种而具有下述构造，即，在芯片焊盘的背面隔着散热性高的绝缘膜而对金属板进行热压接，通过传递模塑而对它们进行成型(例如，参照专利文献1)。
专利文献1：日本特开2004-172239号公报
发明内容
传递模塑所使用的封装树脂为热硬化性，利用热而暂时熔化，然后通过化学反应而逐渐进行硬化。因此，必须在有限的时间内全部注入，特别是对于大面积的封装件等，需要加快注入速度。但是，如果加快速度地进行注入，则对将芯片焊盘和内部引线连结的弯折部施加的流动阻力变高，芯片焊盘受到从绝缘膜剥离的力。因此，芯片焊盘与绝缘膜的粘接性变得不稳定，绝缘耐压降低。另外，针对电力用半导体元件的表面压力下降，电力用半导体元件与芯片焊盘的接合强度变弱。其结果，成品率降低。
由于配线的关系，在绝缘膜的外周部、局部会产生未粘接的部位，而不是绝缘膜的整个面与芯片焊盘粘接。此时在未粘接的外周部，发生由于绝缘膜与金属板的线膨胀系数差而引起的翘曲。绝缘膜主要为树脂，由于线膨胀系数比金属大，因此翘曲成为向下侧凸的形状。在传递模塑中，如果将翘曲的金属板载置于下模具，则出现从模具翘起的部分。如果这样直接进行树脂注入，则沿水平方向流动的封装树脂进入至金属板的下表面与下模具之间，产生树脂毛刺。并且，在树脂毛刺多的情况下，散热性降低。
本发明就是为了解决上述课题而提出的，其目的在于得到一种能够提高成品率和散热性的电力用半导体装置及其制造方法。
本发明涉及的电力用半导体装置的制造方法的特征在于，具有下述工序：准备引线框的工序，该引线框具有内部引线、与所述内部引线连接的外部引线、与所述内部引线相比配置于下方的芯片焊盘以及将所述内部引线和所述芯片焊盘连结的弯折部；在所述芯片焊盘之上固接电力用半导体元件的工序；在所述芯片焊盘的下表面隔着绝缘膜而固接金属板的工序；以及在下模具与上模具之间的腔室内配置所述内部引线、所述芯片焊盘、所述电力用半导体元件、所述绝缘膜以及金属板，利用封装树脂进行封装的工序，所述下模具在所述内部引线的下方具有设置于所述腔室的底面的台阶部，所述台阶部的上表面的高度比在所述腔室内配置的所述电力用半导体元件的上表面高，在将所述封装树脂注入至所述腔室内时，所述金属板的下表面与所述腔室的底面相接触，使所述封装树脂从所述台阶部的上方朝向所述电力用半导体元件的上表面而流动至下方。
发明的效果
在本发明中，使封装树脂从台阶部的上方朝向电力用半导体元件的上表面而流动至下方，向下方按压芯片焊盘。另外，通过设置台阶部，从而降低针对弯折部的流动阻力。由此，芯片焊盘与绝缘膜的粘接性稳定，因此绝缘耐压提高。并且，通过还对电力用半导体元件进行按压，从而表面压力上升，电力用半导体元件的正下方的芯片焊盘与绝缘膜的接合强度变高。其结果，成品率提高。另外，通过设置台阶部，从而在树脂注入时，到封装树脂抵达至金属板为止，封装树脂的水平方向的流动变少，封装树脂难以进入至金属板与下模具之间。并且，通过向下方按压绝缘膜及金属板而抑制金属板的翘曲，从而封装树脂更难进入至金属板与下模具之间。因此，抑制金属板的下表面的树脂毛刺的产生，由于在鳍片等外部冷却器的安装时并未夹着树脂毛刺，所以散热性提高。
附图说明
图1是表示本发明的实施方式1涉及的电力用半导体装置的仰视图。
图2是沿图1的I—II的剖视图。
图3是表示本发明的实施方式1涉及的电力用半导体装置的内部的俯视图。
图4是本发明的实施方式1涉及的电力用半导体装置的侧视图。
图5是表示本发明的实施方式1涉及的电力用半导体装置的制造方法的剖视图。
图6是表示本发明的实施方式1涉及的电力用半导体装置的制造方法的俯视图。
图7是表示本发明的实施方式1涉及的电力用半导体装置的制造方法的放大剖视图。
图8是表示对比例涉及的电力用半导体装置的制造方法的放大剖视图。
图9是表示本发明的实施方式2涉及的电力用半导体装置的仰视图。
图10是沿图9的I—II的剖视图。
图11是表示本发明的实施方式2涉及的电力用半导体装置的制造方法的剖视图。
图12是表示本发明的实施方式3涉及的电力用半导体装置的仰视图。
图13是沿图12的I—II的剖视图。
图14是表示本发明的实施方式3涉及的电力用半导体装置的制造方法的剖视图。
图15是表示本发明的实施方式3涉及的电力用半导体装置的变形例的仰视图。
图16是沿图15的I—II的剖视图。
图17是表示本发明的实施方式4涉及的电力用半导体装置的仰视图。
图18是表示本发明的实施方式4涉及的电力用半导体装置的制造方法的剖视图。
图19是表示本发明的实施方式5涉及的电力用半导体装置的仰视图。
图20是沿图19的I—II的剖视图。
具体实施方式
参照附图对本发明的实施方式涉及的电力用半导体装置及其制造方法进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是表示本发明的实施方式1涉及的电力用半导体装置的仰视图。图2是沿图1的I－II的剖视图。图3是表示本发明的实施方式1涉及的电力用半导体装置的内部的俯视图。图4是本发明的实施方式1涉及的电力用半导体装置的侧视图。该电力用半导体装置为DIP型的封装件。
引线框具有内部引线1a、1b、1c、分别与内部引线1a、1b、1c连接的外部引线2a、2b、2c、与内部引线1a相比配置于下方的芯片焊盘3、以及将内部引线1a和芯片焊盘3连结的弯折部4。内部引线1a、1b为功率内部引线，内部引线为控制内部引线。外部引线2a、2b为功率外部引线，外部引线2c为它们的控制外部引线。
使用无Pb焊料将电力用半导体元件5固接于芯片焊盘3之上。电力用半导体元件5为RC-IGBT(Reverse Conducting Insulated Gate Bipolar Transistor)。使用导电性粘接剂将控制用半导体元件6固接于内部引线1c之上。此外，电力用半导体元件5与芯片焊盘3的接合不限于焊料，能够使用导电性粘接剂等具有导电性的接合材料。
在电力用半导体元件5的上表面设置有发射极电极和栅极电极。Al线7a将发射极电极和内部引线1b连接，Au线7b将栅极电极和控制用半导体元件6连接，Au线7c将控制用半导体元件6和内部引线1c连接。此外，也可以使用Cu线，以取代Al线、Au线。
金属板8隔着散热性高的绝缘膜9而固接于芯片焊盘3的下表面。金属板8由Cu、Al等散热性高的材料构成。绝缘膜9为树脂与导热性的填料的混合物，且绝缘膜9的树脂可以为热塑性，也可以为热硬化性，能够取得粘接性即可。填料为SiO2、Al2O3、BN等，兼具电绝缘和高导热率即可。
封装树脂10将内部引线1a、1b、1c、芯片焊盘3、电力用半导体元件5、绝缘膜9、Al线7a、Au线7b、7c、以及金属板8进行封装。金属板8的下表面从封装树脂10的下表面露出。外部引线2a、2b、2c分别从装置两端凸出。在内部引线1a、1b的下方，在封装树脂10的下表面设置有台阶部11。台阶部11处的封装树脂10的下表面的高度h1比电力用半导体元件5的上表面的高度h2高。
下面，对本实施方式涉及的电力用半导体装置的制造方法进行说明。图5是表示本发明的实施方式1涉及的电力用半导体装置的制造方法的剖视图。图6是表示本发明的实施方式1涉及的电力用半导体装置的制造方法的俯视图。
首先，准备引线框，在其芯片焊盘3之上使用无Pb焊料而固接电力用半导体元件5，在内部引线1c之上使用导电性粘接剂而固接控制用半导体元件6。利用Al线7a将电力用半导体元件5的发射极电极和内部引线1a连接，利用Au线7b将电力用半导体元件5的栅极电极和控制用半导体元件6连接，利用Au线7c将控制用半导体元件6和内部引线1c连接。
通过热压接而将预先接合有金属板8的半硬化的绝缘膜9临时粘接于芯片焊盘3的下表面。在这里，半硬化是指在常温下为固体而在高温下暂时熔化之后向完全硬化转变的、硬化不完全的状态。
接下来，如图5及图6所示，在下模具12a与上模具12b之间的腔室13内，配置内部引线1a、1b、1c、芯片焊盘3、电力用半导体元件5、Al线7a、Au线7b、7c、金属板8、以及绝缘膜9等。此时，在腔室13的底面，从下模具12a凸出有定位用可动销12c，将金属板8及绝缘膜9进行定位。然后，在合模后从处于外部引线2a、2b之间的浇口将封装树脂10注入至腔室13内，利用该封装树脂10进行封装(传递模塑)。利用该封装树脂10的注入压力而将绝缘膜9完全地热压接，并且形成封装体。
关于树脂注入，为了使封装树脂10的针对控制用内部引线1c之上的Au线7c的流动阻力减小，从电力用内部引线1a、1b侧向控制用内部引线1c侧流过封装树脂10。在注入过程中将定位用可动销12c拔出，在模具内施加流体静压。封装树脂10在硬化之后通过模具的脱离而进行脱模。
下模具12a在内部引线1a的下方具有设置于腔室13的底面的台阶部14。台阶部14的上表面的高度h1比在腔室13内配置的电力用半导体元件5的上表面的高度h2高。在将封装树脂10注入至腔室13内时，金属板8的下表面与腔室13的底面相接触，使封装树脂10从台阶部14的上方朝向电力用半导体元件5的上表面而流动至下方。
将传递模塑后在外部引线2a、2b之间的浇口处残存的封装树脂10从封装体切除。在封装体的侧面，留下如图4所示的表面粗糙度(Rz)大于或等于20μm的浇口树脂去除痕15。然后，对外部引线2a、2b、2c实施防锈处理等后续加工，进行外形加工而加工成规定的形状。
下面，一边与对比例进行比较，一边说明本实施方式的效果。图7是表示本发明的实施方式1涉及的电力用半导体装置的制造方法的放大剖视图。图8是表示对比例涉及的电力用半导体装置的制造方法的放大剖视图。在本实施方式中，在内部引线1a的下方将台阶部14设置于腔室13的底面，但在对比例中未设置台阶部14。
在对比例中由于无台阶部14，因此注入后的封装树脂10相对于绝缘膜9、芯片焊盘3而沿水平方向(平面方向)流动。从而，弯折部4从封装树脂10受到向上的流动阻力，因此在树脂注入过程中连续地施加将芯片焊盘3从绝缘膜9剥离的力，绝缘膜9与芯片焊盘3的粘接性变得不稳定。另外，针对电力用半导体元件5的表面压力下降，电力用半导体元件5与芯片焊盘3的接合强度变弱。沿水平方向流动的封装树脂10进入至金属板8的下表面与下模具之间，从而产生树脂毛刺。
另一方面，在本实施方式中，使封装树脂10从台阶部14的上方朝向电力用半导体元件5的上表面而流动至下方，向下方按压芯片焊盘3。另外，通过设置台阶部14，从而针对弯折部4的流动阻力降低。由此，绝缘膜9与芯片焊盘3的粘接性稳定，因此绝缘耐压提高。并且，通过还对电力用半导体元件5进行按压，从而表面压力上升，电力用半导体元件5的正下方的芯片焊盘3与绝缘膜9的接合强度变高。其结果，成品率提高。
另外，通过设置台阶部14，从而在树脂注入时，到封装树脂10抵达至金属板8为止，封装树脂10的水平方向的流动变少，封装树脂10难以进入至金属板8与下模具12a之间。并且，通过向下方按压绝缘膜9及金属板8而抑制金属板8的翘曲，从而封装树脂10更难进入至金属板8与下模具12a之间。因此，抑制金属板8的下表面的树脂毛刺的产生，由于在鳍片等外部冷却器的安装时并未夹有树脂毛刺，因此散热性提高。
另外，在本实施方式中，在内部引线1a的下方，在封装树脂10的下表面设置有台阶部11。利用该台阶部11，外部引线2a、2b与金属板8之间的沿面距离变长，因此能够使电力用半导体装置小型化。
此外，在实施方式1中，为了确保在下模具12a设置可动销12c的区域，需要使台阶部14与金属板8之间分离一定的间隔(0.5～3mm)。从而，在制造后的装置中，在台阶部11与金属板8之间需要一定宽度的封装树脂10的底面。
实施方式2.
图9是表示本发明的实施方式2涉及的电力用半导体装置的仰视图。图10是沿图9的I－II的剖视图。图11是表示本发明的实施方式2涉及的电力用半导体装置的制造方法的剖视图。
在台阶部14与金属板8之间，在腔室13的底面设置有高度比台阶部14低的2个凸起16。通过转印该下模具12a的凸起16，从而在台阶部11与金属板8之间，在封装树脂10的下表面设置深度比台阶部11浅的2个凹坑17。优选凹坑17的高度比金属板8和绝缘膜9的合计厚度小。
由于能够沿下模具12a的凸起16将金属板8定位而载置，因此能够省去在实施方式1中使用的定位用可动销12c。由此，能够省略在下模具12a之上设置可动销12c的区域，因此能够使封装树脂10的底面的宽度变窄，能够使电力用半导体装置小型化。
另外，能够利用凸起16使金属板8的侧面与下模具12a的间隔进一步地变窄，因此针对弯折部4的流动阻力进一步地降低，绝缘膜9与芯片焊盘3的粘接性更加稳定。并且，封装树脂10更难进入至金属板8的下表面与下模具12a的底面之间。
另外，如果金属板8的侧面与下模具12a的台阶部14的间隔根据位置而不同，则向金属板8的水平方向流动变得不均一，因此树脂毛刺的出现方式发生波动。因此，优选将凸起16设为大于或等于2个。并且，在将金属板8和绝缘膜9设置于下模具12a之上时，利用凸起16能够稳定地进行位置固定，而不会旋转。从而，金属板8的侧面与下模具12a的台阶部14的间隔变得均等，制造波动变小。在将凸起16设为大于或等于2个的情况下，在制造后的装置中，在封装树脂10的下表面设置大于或等于2个凹坑17。
另外，根据本实施方式2，能够省略在下模具12a之上设置可动销12c的区域。从而，在制造后的装置中，能够使封装树脂10的底面的宽度变窄，因此能够实现产品的小型化。
实施方式3.
图12是表示本发明的实施方式3涉及的电力用半导体装置的仰视图。图13是沿图12的I－II的剖视图。图14是表示本发明的实施方式3涉及的电力用半导体装置的制造方法的剖视图。
在台阶部11与金属板8之间，在腔室13的底面设置有高度比台阶部14低的小台阶部18，以取代实施方式2的凸起16。通过转印该下模具12a的小台阶部18，从而在台阶部11与金属板8之间，在封装树脂10的下表面设置深度比台阶部11浅的小台阶部19。与凹坑17相比，小台阶部18的构造简单且为直线式的形状，因此模具容易清扫，维护性提高。优选小台阶部18的高度比金属板8和绝缘膜9的合计厚度小。
图15是表示本发明的实施方式3涉及的电力用半导体装置的变形例的仰视图。图16是沿图15的I－II的剖视图。将台阶部11与小台阶部18的倾斜面连结而设为整体式的倾斜，使该倾斜延长至金属板8的附近。在该情况下也能够得到实施方式3的效果。
实施方式4.
图17是表示本发明的实施方式4涉及的电力用半导体装置的仰视图。图18是表示本发明的实施方式4涉及的电力用半导体装置的制造方法的剖视图。图18对应于图17的装置的沿I－II的剖面。
与实施方式1相同地，沿金属板8的长边而设置台阶部11，在此基础上，在腔室13的底面，沿金属板8的短边而在下模具12a设置有凸部20。通过转印该下模具12a的凸部20，从而沿金属板8的短边而在封装树脂10的下表面的螺孔附近设置凹部21。
利用凸部20，在短边侧封装树脂10的水平方向的流动也变少，因此针对金属板8的短边方向的翘曲，也抑制树脂毛刺的产生。凸部20的高度(凹部21的深度)优选比金属板8的厚度大。
实施方式5.
图19是表示本发明的实施方式5涉及的电力用半导体装置的仰视图。图20是沿图19的I－II的剖视图。在本实施方式中，实施方式1等的台阶部14设置为将金属板8的外周包围。通过转印该下模具12a的台阶部14，从而在封装树脂10的下表面以将金属板8的外周包围的方式设置台阶部11。将树脂浇口设置于金属板8的短边侧。即使在这样将树脂浇口设置于功率引线侧以外的方向的情况下，也能够通过将台阶部14设置为包围金属板8的外周，从而使绝缘膜9与芯片焊盘3的粘接性变得稳定，且抑制金属板的背面的树脂毛刺。
此外，电力用半导体元件5不限于由硅形成，也可以由与硅相比带隙宽的宽带隙半导体形成。宽带隙半导体为例如碳化硅、氮化镓类材料或者金刚石。对于这种由宽带隙半导体形成的电力用半导体元件5，由于耐电压性、容许电流密度高，因此能够小型化。通过使用该小型化的元件，能够使组装有该元件的电力用半导体装置也小型化。另外，由于元件的耐热性高，因此能够将散热器的散热鳍片小型化，能够将水冷部进行空冷化，因而能够将半导体模块进一步小型化。另外，元件的电力损耗低且高效率，因此能够使电力用半导体装置高效率化。
标号的说明
1a内部引线，2a外部引线，3芯片焊盘，4弯折部，5电力用半导体元件，8金属板，9绝缘膜，10封装树脂，12a下模具，12b上模具，13腔室，14台阶部，16凸起，17凹坑，18小台阶部，19小台阶部，20凸部，21凹部。

Claims (11)

1.一种电力用半导体装置的制造方法，其特征在于，具有下述工序：
准备引线框的工序，该引线框具有内部引线、与所述内部引线连接的外部引线、与所述内部引线相比配置于下方的芯片焊盘以及将所述内部引线和所述芯片焊盘连结的弯折部；
在所述芯片焊盘之上固接电力用半导体元件的工序；
在所述芯片焊盘的下表面隔着绝缘膜而固接金属板的工序；以及
在下模具与上模具之间的腔室内配置所述内部引线、所述芯片焊盘、所述电力用半导体元件、所述绝缘膜以及金属板，利用封装树脂进行封装的工序，
所述下模具在所述内部引线的下方具有设置于所述腔室的底面的台阶部，
所述台阶部的上表面的高度比在所述腔室内配置的所述电力用半导体元件的上表面高，
在将所述封装树脂注入至所述腔室内时，所述金属板的下表面与所述腔室的底面相接触，使所述封装树脂从所述台阶部的上方朝向所述电力用半导体元件的上表面而流动至下方。
2.根据权利要求1所述的电力用半导体装置的制造方法，其特征在于，
所述下模具在所述台阶部与所述金属板之间具有凸起，该凸起设置于所述腔室的底面，高度比所述台阶部低。
3.根据权利要求1所述的电力用半导体装置的制造方法，其特征在于，
所述下模具在所述台阶部与所述金属板之间具有小台阶部，该小台阶部设置于所述腔室的底面，高度比所述台阶部低。
4.根据权利要求1～3中任一项所述的电力用半导体装置的制造方法，其特征在于，
沿所述金属板的长边而设置所述台阶部，
所述下模具具有凸部，该凸部沿所述金属板的短边而设置于所述腔室的底面。
5.根据权利要求1～3中任一项所述的电力用半导体装置的制造方法，其特征在于，
所述台阶部设置为将所述金属板的外周包围。
6.一种电力用半导体装置，其特征在于，具有：
引线框，其具有内部引线、与所述内部引线连接的外部引线、与所述内部引线相比配置于下方的芯片焊盘以及将所述内部引线和所述芯片焊盘连结的弯折部；
电力用半导体元件，其固接于所述芯片焊盘之上；
金属板，其隔着绝缘膜而固接于所述芯片焊盘的下表面；以及
封装树脂，其将所述内部引线、所述芯片焊盘、所述电力用半导体元件、所述绝缘膜以及金属板进行封装，
所述金属板的下表面从所述封装树脂的下表面露出，
在所述内部引线的下方，在所述封装树脂的下表面设置台阶部，
所述台阶部处的所述封装树脂的下表面的高度比所述电力用半导体元件的上表面的高度高。
7.根据权利要求6所述的电力用半导体装置，其特征在于，
在所述台阶部与所述金属板之间，在所述封装树脂的下表面设置有深度比所述台阶部浅的凹坑。
8.根据权利要求7所述的电力用半导体装置，其特征在于，
所述凹坑设置有大于或等于2个。
9.根据权利要求6所述的电力用半导体装置，其特征在于，
在所述台阶部与所述金属板之间，在所述封装树脂的下表面设置有深度比所述台阶部浅的小台阶部。
10.根据权利要求6～9中任一项所述的电力用半导体装置，其特征在于，
沿所述金属板的长边而设置有所述台阶部，沿所述金属板的短边而在所述封装树脂的下表面设置有凹部。
11.根据权利要求6～9中任一项所述的电力用半导体装置，其特征在于，
所述台阶部设置为将所述金属板的外周包围。
CN201480078993.2A 2014-05-12 2014-05-12 电力用半导体装置及其制造方法 Active CN106463420B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/062608 WO2015173862A1 (ja) 2014-05-12 2014-05-12 電力用半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN106463420A true CN106463420A (zh) 2017-02-22
CN106463420B CN106463420B (zh) 2019-07-26

Family

ID=54479436

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480078993.2A Active CN106463420B (zh) 2014-05-12 2014-05-12 电力用半导体装置及其制造方法

Country Status (6)

Country Link
US (1) US9716072B2 (zh)
JP (1) JP6195019B2 (zh)
KR (1) KR101915873B1 (zh)
CN (1) CN106463420B (zh)
DE (1) DE112014006660B4 (zh)
WO (1) WO2015173862A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109637983A (zh) * 2017-10-06 2019-04-16 财团法人工业技术研究院 芯片封装
CN116247049A (zh) * 2023-02-28 2023-06-09 海信家电集团股份有限公司 功率模块及具有其的电子设备

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6546892B2 (ja) * 2016-09-26 2019-07-17 株式会社 日立パワーデバイス 半導体装置
US10483178B2 (en) * 2017-01-03 2019-11-19 Infineon Technologies Ag Semiconductor device including an encapsulation material defining notches
CN110998812B (zh) 2017-08-23 2023-08-18 三菱电机株式会社 半导体装置的制造方法
JP7030481B2 (ja) * 2017-11-10 2022-03-07 エイブリック株式会社 樹脂封止金型および半導体装置の製造方法
JP7040032B2 (ja) * 2018-01-17 2022-03-23 株式会社デンソー 半導体装置
US20200031661A1 (en) * 2018-07-24 2020-01-30 Invensense, Inc. Liquid proof pressure sensor
CN113261095A (zh) * 2019-01-18 2021-08-13 三菱电机株式会社 半导体装置、半导体装置的制造方法及电力转换装置
JP7090579B2 (ja) * 2019-05-08 2022-06-24 三菱電機株式会社 半導体装置およびその製造方法
JP7459465B2 (ja) * 2019-08-28 2024-04-02 富士電機株式会社 半導体装置及び半導体装置の製造方法
JP7196815B2 (ja) * 2019-10-23 2022-12-27 三菱電機株式会社 半導体モジュール及び電力変換装置
JP2021145036A (ja) * 2020-03-12 2021-09-24 富士電機株式会社 半導体装置の製造方法及び半導体装置
DE112020006890T5 (de) * 2020-03-13 2022-12-22 Mitsubishi Electric Corporation Halbleitervorrichtung und leistungswandler
US11765528B2 (en) * 2020-09-28 2023-09-19 Lite-On Singapore Pte. Ltd. Sensing device and method for packaging the same
JP2022059117A (ja) * 2020-10-01 2022-04-13 三菱電機株式会社 半導体装置、半導体装置の製造方法及び電力変換装置
US11764209B2 (en) 2020-10-19 2023-09-19 MW RF Semiconductors, LLC Power semiconductor device with forced carrier extraction and method of manufacture
WO2023058437A1 (ja) * 2021-10-08 2023-04-13 三菱電機株式会社 半導体装置、電力変換装置、および、半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1983574A (zh) * 2005-12-12 2007-06-20 三菱电机株式会社 半导体器件以及半导体器件的树脂密封用模具
US20120032316A1 (en) * 2010-08-09 2012-02-09 Renesas Electronics Corporation Semiconductor device, method of manufacturing semiconductor device, mold, and sealing device
CN102637679A (zh) * 2011-02-14 2012-08-15 三菱电机株式会社 半导体模块

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02152260A (ja) * 1988-12-05 1990-06-12 Fujitsu Ltd 樹脂封止半導体装置およびそれの製造に用いる金型
JP2771838B2 (ja) * 1989-03-31 1998-07-02 ポリプラスチックス株式会社 電子部品の樹脂封止方法、樹脂封止用成形金型及び電子部品封止成形品
JPH09129661A (ja) * 1995-10-31 1997-05-16 Hitachi Ltd 成形装置および成形方法
JP4073559B2 (ja) * 1998-10-30 2008-04-09 三菱電機株式会社 半導体装置
JP4277168B2 (ja) 2002-11-18 2009-06-10 サンケン電気株式会社 樹脂封止型半導体装置及びその製法
JP2005109100A (ja) * 2003-09-30 2005-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3854957B2 (ja) * 2003-10-20 2006-12-06 三菱電機株式会社 半導体装置の製造方法および半導体装置
JP4463146B2 (ja) * 2005-05-18 2010-05-12 三菱電機株式会社 半導体装置の製造方法
KR101489325B1 (ko) * 2007-03-12 2015-02-06 페어차일드코리아반도체 주식회사 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
JP5598189B2 (ja) * 2010-09-08 2014-10-01 株式会社デンソー 半導体装置の製造方法
JP5720514B2 (ja) 2011-09-27 2015-05-20 三菱電機株式会社 半導体装置の製造方法
JP5680011B2 (ja) * 2012-03-26 2015-03-04 三菱電機株式会社 電力用半導体装置および電力用半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1983574A (zh) * 2005-12-12 2007-06-20 三菱电机株式会社 半导体器件以及半导体器件的树脂密封用模具
US20120032316A1 (en) * 2010-08-09 2012-02-09 Renesas Electronics Corporation Semiconductor device, method of manufacturing semiconductor device, mold, and sealing device
CN102637679A (zh) * 2011-02-14 2012-08-15 三菱电机株式会社 半导体模块

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109637983A (zh) * 2017-10-06 2019-04-16 财团法人工业技术研究院 芯片封装
US10622274B2 (en) 2017-10-06 2020-04-14 Industrial Technology Research Institute Chip package
CN109637983B (zh) * 2017-10-06 2021-10-08 财团法人工业技术研究院 芯片封装
US11387159B2 (en) 2017-10-06 2022-07-12 Industrial Technology Research Institute Chip package
CN116247049A (zh) * 2023-02-28 2023-06-09 海信家电集团股份有限公司 功率模块及具有其的电子设备
CN116247049B (zh) * 2023-02-28 2024-01-23 海信家电集团股份有限公司 功率模块及具有其的电子设备

Also Published As

Publication number Publication date
WO2015173862A1 (ja) 2015-11-19
DE112014006660B4 (de) 2019-10-31
CN106463420B (zh) 2019-07-26
JP6195019B2 (ja) 2017-09-13
DE112014006660T5 (de) 2017-01-19
US9716072B2 (en) 2017-07-25
KR101915873B1 (ko) 2018-11-06
KR20160143802A (ko) 2016-12-14
US20160343644A1 (en) 2016-11-24
JPWO2015173862A1 (ja) 2017-04-20

Similar Documents

Publication Publication Date Title
CN106463420A (zh) 电力用半导体装置及其制造方法
US8569890B2 (en) Power semiconductor device module
JP6183226B2 (ja) 電力用半導体装置の製造方法
US9640460B2 (en) Semiconductor device with a heat-dissipating plate
CN108604578B (zh) 电力用半导体装置及其制造方法
JP6619356B2 (ja) 電力用半導体装置およびその製造方法
CN103050470B (zh) 智能功率模块及其制作方法
JP2002237562A (ja) 半導体装置とその製造方法
US8823151B2 (en) Semiconductor device
CN104282641A (zh) 半导体装置
CN104303299B (zh) 半导体装置的制造方法及半导体装置
CN101675520A (zh) 电力用半导体模块
CN111276447B (zh) 双侧冷却功率模块及其制造方法
JP2002329815A (ja) 半導体装置と、その製造方法、及びその製造装置
CN203232866U (zh) 智能功率模块
CN105990275A (zh) 功率模块封装件及其制作方法
US11152275B2 (en) Semiconductor device and method for manufacturing semiconductor device
CN103855103A (zh) 半导体装置及其制造方法
JP2012174747A (ja) パワー半導体モジュールの構造およびその製造方法
CN107546199A (zh) 功率模块及制造其的方法
JP2012174748A (ja) 半導体モジュールの構造およびその製造方法
CN110444520B (zh) 具有电绝缘散热体的功率器件模组及其制备方法
US20230045523A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP2012119488A (ja) 半導体装置の製造方法及び半導体装置
JP2023077978A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant