CN106233459B - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN106233459B CN106233459B CN201580000517.3A CN201580000517A CN106233459B CN 106233459 B CN106233459 B CN 106233459B CN 201580000517 A CN201580000517 A CN 201580000517A CN 106233459 B CN106233459 B CN 106233459B
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- China
- Prior art keywords
- capacitor
- convex block
- power supply
- intermediate substrate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 239000003990 capacitor Substances 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 239000010409 thin film Substances 0.000 claims description 46
- 239000003985 ceramic capacitor Substances 0.000 description 27
- 238000010276 construction Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 14
- 239000010408 film Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000005611 electricity Effects 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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Abstract
本发明涉及一种半导体器件(1),设置有:半导体芯片(10),面向上地管芯接合安装在支承体(2)上;中间基板(20),设置在半导体芯片上并将半导体芯片连接到多个外部连接部(3);多个连接凸块(6),连接半导体芯片和中间基板,包括用于向半导体芯片供电的、与半导体芯片上的多个电极焊盘(11)连接的多个电源凸块(6V、6G)。中间基板包括:多个电源焊盘(21V、21G),通过多个电源凸块连接到多个电极焊盘;凸块表面(22),面对半导体芯片并具有在其上形成的多个电源焊盘;外部连接表面(24),设置在凸块表面的相反侧并具有在其上形成的与外部连接部连接的多个外部连接焊盘;电容器(30),连接到多个电源凸块。
Description
技术领域
本发明涉及半导体器件,更特别地,涉及设置有被面向上地管芯接合(die-bonded)到支承体的半导体芯片并且设置有电容器的半导体器件。
背景技术
传统地,作为以上类型的半导体器件,已知的是(例如)专利文献1中公开的技术。在专利文献1中,如该文献的图1中示出的,作为半导体芯片的上层芯片2被面向上地管芯接合到作为支承体的下层芯片7上。在半导体器件1中,例如,上芯片2和围绕上芯片2安装的无源芯片组件3,诸如芯片电容器,经由布线5和布线基板4连接。
专利文献
专利文献1:JP-A-2004-296613
发明内容
技术问题
然而,随着近年来半导体芯片(LSI)的时钟频率增加,当从LSI到电容器的布线距离大时,由于布线导致的高频阻抗增加。结果,电容器的降噪效果减弱,这会造成在高频下无法得到LSI的预期操作的问题。
因此,在本申请中,提供了一种半导体器件,在该半导体器件中,从被面向上地管芯接合到支承体的半导体芯片到电容器的布线距离减小,由此电容器的降噪效果增加,并且高频操作期间半导体芯片的可靠性增加。
问题的解决方案
本申请公开的一种半导体器件包括:支承体;半导体芯片,其被面向上地管芯接合安装在所述支承体上;多个外部连接部,其将所述半导体芯片电连接到外部;中间基板,其设置在所述半导体芯片的与所述支承体相反的一侧并且将所述半导体芯片连接到所述多个外部连接部;多个连接凸块,其连接所述半导体芯片和所述中间基板。所述半导体芯片包括通过所述多个电极焊盘与所述中间基板连接的多个电极焊盘。所述多个连接凸块包括用于向所述半导体芯片供电的多个电源凸块。所述中间基板包括:多个电源焊盘,其通过所述多个电源凸块连接到所述多个电极焊盘;凸块表面,其面对所述半导体芯片并且具有在其上形成的所述多个电源焊盘;外部连接表面,其设置在所述凸块表面的相反侧并且具有在其上形成的与所述外部连接部连接的多个外部连接焊盘;电容器,其连接到所述多个电源凸块。
根据该构造,中间基板设置在半导体芯片上方并且经由电源凸块直接连接到半导体芯片的电极焊盘。电容器形成在中间基板上并且通过电源凸块连接到半导体芯片的电极焊盘。因此,相比于通过引线和通过基板布线连接到半导体芯片的传统电容器,从半导体芯片到电容器的布线距离大大减小。具体地,根据本构造的半导体器件,从被面向上地管芯接合安装在支承体上的半导体芯片到电容器的布线距离能够减小。因此,电容器的降噪效果能够增加,由此能够实现稳定的电源,并且能够增加高频操作期间半导体芯片的可靠性。
在所述半导体器件中,所述电容器可以是形成在所述中间基板的所述凸块表面上并且与所述多个电源焊盘连接的薄膜电容器。
根据本构造,薄膜电容器形成在中间基板的凸块表面上并且仅仅通过凸块表面上的电源焊盘和电源凸块连接到半导体芯片的电极焊盘。因此,相比于通过引线和通过基板布线连接到半导体芯片的传统电容器,从半导体芯片到薄膜电容器的布线距离大大减小。
在所述半导体器件中,所述电容器还可包括形成在所述外部连接表面上的芯片电容器,所述芯片电容器可通过形成在所述中间基板中的通孔塞并联连接到所述薄膜电容器。
根据该构造,例如电容比薄膜电容器大得多的多层陶瓷电容器进一步与薄膜电容器并联连接。因此,相比于只使用薄膜电容器的情况,电容器的降噪效果能够进一步增加,由此能够实现稳定的电源,并且能够增加高频操作期间LSI芯片10的可靠性。
在所述半导体器件中,所述电容器可以是形成在所述外部连接表面上的薄膜电容器,所述薄膜电容器可以通过形成在所述中间基板中的通孔塞连接到所述多个电源凸块。
根据该构造,相比于通过引线和通过基板布线连接到半导体芯片的传统电容器,能够减小布线距离。
在所述半导体芯片中,所述电容器可以是形成在所述外部连接表面上的芯片电容器,所述芯片电容器可通过形成在所述中间基板中的通孔塞连接到所述多个电源凸块。
根据该构造,相比于通过引线和通过基板布线连接到半导体芯片的传统电容器,能够减小布线距离。另外,因为该结构使得芯片电容器设置在半导体芯片上方,所以能够减小半导体器件的面积,这有助于减小其上安装有半导体器件的诸如母板的电路基板的尺寸。
在所述半导体芯片中,所述电容器可以是形成在所述外部连接表面上的芯片电容器,所述芯片电容器可经由形成在所述外部连接表面上的电源布线部连接到所述多个电源凸块。
根据该构造,相比于通过引线和通过基板布线与半导体芯片连接的传统电容器,能够减小布线距离。另外,因为该结构使得芯片电容器设置在半导体芯片上方,所以能够减小半导体器件的面积,并且能够减小中间基板中的通孔塞的数量。
在所述半导体器件中,所述电容器可包括第一电极和第二电极;所述多个电源凸块可包括第一电源凸块和第二电源凸块,所述第一电源凸块用于向所述半导体芯片施加一个极性的电源电压,所述第二电源凸块用于向所述半导体芯片施加另一个极性的电源电压;所述通孔塞可包括第一通孔塞和第二通孔塞,所述第一通孔塞将所述第一电极连接到所述第一电源凸块,所述第二通孔塞将所述第二电极连接到所述第二电源凸块;所述芯片电容器的所述第一电极可通过形成在所述外部连接表面上的焊盘、所述第一通孔塞、形成在所述凸块表面上的第一电源布线部连接到所述第一电源凸块;所述芯片电容器的所述第二电极可通过形成在所述外部连接表面上的第二电源布线部和所述第二通孔塞连接到所述第二电源凸块。
根据该构造,芯片电容器的布线电路独立地形成在凸块表面和外部连接表面之间。例如,与正电压关联的第一电源布线部形成在凸块表面上,与地电压关联的第二电源布线部形成在外部连接表面上。因此,相比于布线电路仅形成在外部连接表面上的情况,布线电路的电路图案能够被简化并且长度被减小。因此,布线电路中产生的ESR(等效串联电阻)或ESL(等效串联电感)的值能够被减小。
在所述半导体器件中,可通过中间基板中形成的通孔塞来连接多个电源焊盘和多个外部连接焊盘,并且可通过引线接合来连接多个外部连接焊盘和多个外部连接部。
根据该构造,在经由引线接合来连接半导体芯片和外部连接部的构造中,能够减小从半导体芯片到电容器的布线距离。
本发明的效果
根据本发明,提供了一种半导体器件,在该半导体器件中,减小了从被面向上地管芯接合到支承体上的半导体芯片到电容器的布线距离,由此能够增加电容器的降噪效果,并且能够增加高频操作期间半导体芯片的可靠性。
附图说明
图1是根据第一实施例的半导体器件的示意性横截面图。
图2是示出薄膜电容器的部分放大视图。
图3是示出根据第一实施例的半导体器件的中间基板的外部连接表面的平面图。
图4是示出根据第一实施例的半导体器件的中间基板的凸块表面的平面图。
图5是示出根据第一实施例的半导体器件的另一个示例的示意性横截面图。
图6是根据第二实施例的半导体器件的示意性横截面图。
图7是示出根据第二实施例的半导体器件的另一个示例的示意性横截面图。
图8是根据第二实施例的半导体器件的另一个示例的示意性横截面图。
图9是根据第二实施例的半导体器件的另一个示例的示意性横截面图。
图10是示出图9的半导体器件的中间基板的外部连接表面的平面图。
图11是示出图9的半导体器件的中间基板的凸块表面的平面图。
具体实施方式
(第一实施例)
将参照图1至图5描述本发明的第一实施例。
1.第一实施例的半导体器件的构造
如图1所示,根据第一实施例的半导体器件1是四方扁平无引线封装(QFN)半导体器件。如图1所示的半导体器件1设置有支承体2和LSI芯片(“半导体芯片”的示例)10,LSI芯片10被面向上地管芯接合安装在支承体2上。半导体器件1还设置有:多个外部连接部3,其将LSI芯片10电连接到外部;中间基板20,其设置在LSI芯片10的与支承体2相反的一侧并且将LSI芯片10连接到多个外部连接部3;以及多个连接凸块6,其连接LSI芯片10和中间基板20。
LSI芯片10包括多个电极焊盘11,电极焊盘11设置在管芯接合表面的相反侧的表面12上,并且连接到中间基板20。
如图3和图4所示,中间基板20从平面图看具有四边形形状,并且例如包括已经被热压接合的BT树脂(预浸渍片)。中间基板20不限于BT(双马来酰亚胺三嗪)树脂。例如,中间基板20可由诸如硼硅酸盐玻璃、石英玻璃或钠玻璃的玻璃制成,只要该基板允许实施薄膜形成处理和金属微制造即可。
中间基板20包括面对LSI芯片10的凸块表面(下表面)22。形成在LSI芯片10的多个电极焊盘11上的多个连接凸块6连接到凸块表面22。具体地,连接凸块6连接到形成在凸块表面22上的焊盘21。
除了信号凸块6之外,多个连接凸块6还包括电源凸块(6V、6G),电源凸块(6V、6G)连接到LSI芯片10的多个电极焊盘11,用于向LSI芯片10供电(参见图2)。焊盘21包括经由多个电源凸块(6V、6G)与多个电极焊盘(11V、11G)连接的多个电源焊盘(21V、21G)。
电源凸块6V是用于向LSI芯片10施加预定正电压的凸块。电源凸块6G是用于向LSI芯片10施加地电压(零电压)的凸块。正电压对应于施加到LSI芯片10的电源电压的一个极性。地电压对应于施加到LSI芯片10的电源电压的另一个极性。然而,应该注意,这并非限制并且极性可被反转。也就是说,电源电压的所述一个极性可对应于地电压,而电源电压的所述另一个极性可对应于正电压。在本实施例中,指明与正电压关联的构件的符号附有字母“V”,指明与地电压关联的构件的符号附有字母“G”。“V”或“G”中的任一个将不被附于指明与除了电源信号之外的信号关联的构件的符号,或者当不是特别必要进行区分时,将不附有“V”或“G”中的任一个。
中间基板20具有外部连接表面(上表面)24,外部连接表面24在凸块表面22的相反侧并且其上形成有与外部连接部3连接的多个外部连接焊盘23,并且中间基板20包括与电源凸块(6V、6G)连接的电容器。在中间基板20中,形成有连接多个焊盘21和多个外部连接焊盘23的多个通孔塞25。
在第一实施例中,电容器是形成在中间基板20的凸块表面22上并且与电源焊盘(21V、21G)直接连接的薄膜电容器30,如图1和图2所示。图1和图2中示出的中间基板20的横截面是沿着示出外部连接表面24的图3的线A-A截取的。
如图2和图4所示,薄膜电容器30包括第一平面电极31、第二平面电极32和电介质层33。如图4所示,例如,第一平面电极31、第二平面电极32和电介质层33每个均由适形于中间基板20的四条边的、与从平面图看具有四边形形状的薄膜片构成。也就是说,薄膜电容器30是从平面图看具有四边形形状的片电容器。图4是从LSI芯片10侧看到的中间基板20的平面图。
如图4所示,第一平面电极31包括凸块连接部31V。凸块连接部31V直接连接到电源凸块6V。第二平面电极32也包括凸块连接部32G。凸块连接部32G直接连接到电源凸块6G。也就是说,薄膜电容器30具有所谓旁路电容器的功能。凸块连接部(31V、32G)还兼作与电源凸块(6V、6G)连接的电源焊盘(21V、21G)。虽然图4示出其中凸块连接部31V、32G分别形成在平面电极31、32的四个位置的示例,但并非限制。
2.制造半导体器件的方法
制备通过熟知方法被面向上地管芯接合在预定支承体2上的LSI芯片10。通过熟知方法,在LSI芯片10的电极焊盘11上形成连接凸块6。例如,连接凸块6是金堆叠凸块。连接凸块6不限于金堆叠凸块,并且例如可以是微焊料球。连接凸块6可形成在中间基板20的焊盘21上。
例如,如下所述,在中间基板20的凸块表面22上制造薄膜电容器30。首先,在金属基材上形成包括诸如STO的金属氧化物的电介质膜。例如,通过溅射,在电介质膜上形成诸如铜薄膜的金属薄膜,然后将金属薄膜图案化,以形成第一平面电极31、第二平面电极32的凸块连接部32G和焊盘21。此时,将凸块连接部31V(电源焊盘21V)与第一平面电极31一体地形成。
然后,将BT树脂(预浸料片)热压接合到第一平面电极31上,使得第一平面电极31等被嵌入,从而形成中间基板20的绝缘部。然后,去除金属基材以暴露电介质膜,并且将电介质膜图案化以形成电介质层33。此后,例如,通过使用掩膜进行溅射,在电介质层33上形成诸如铜薄膜的金属薄膜,从而形成第二平面电极32。此时,将凸块连接部32G(电源焊盘21G)与第二平面电极32形成一体。在该制造方法中,如图2所示,该结构使得第一平面电极31和凸块连接部32G被嵌入中间基板20的绝缘部(BT树脂)中。
如图4所示,第一平面电极31和第二平面电极32是具有大致相同形状和尺寸的矩形形状的电极。因此,如图2所示,在中间基板20的凸块表面22上形成薄膜电容器30,在薄膜电容器30中,第一平面电极31、电介质层33和第二平面电极32依次层叠。
在中间基板20的凸块表面22上制造薄膜电容器30的方法不限于以上方法。在另一个示例中,例如,通过金属溅射或镀敷,在中间基板20的表面(凸块表面)22上,将第一平面电极31与凸块连接部31V一体地形成。然后,在第一平面电极31上方,形成包括ITO或STO等的金属氧化物膜的电介质层33。然后,如第一平面电极31的情况一样,用通过溅射或镀敷形成的第二平面电极32覆盖电介质层33。在该情况下,该结构使得第一平面电极31等没有被嵌入在中间基板20的绝缘部(BT树脂)中。
然后,在中间基板20中的预定位置,例如,通过激光处理形成通孔,并且例如用铜材料填充通孔,从而形成多个通孔塞25。此后,例如,通过使用超声波,将连接凸块6连接到中间基板20的凸块表面22上的与通孔塞25对应的焊盘21,由此将中间基板20连接在LSI芯片10上方。例如,用底部填料(未示出)填充LSI芯片10和中间基板20之间的间隙。
然后,通过使用诸如金线的引线4进行引线接合,将中间基板20上的外部连接焊盘23连接到外部连接部3。然后,通过熟知的成型技术,用成型树脂5将LSI芯片10、中间基板20等成型成预定尺寸,从而完成如图1所示的半导体器件1。
3.第一实施例的效果
在第一实施例中,通过通孔连接凸块6将中间基板20直接连接到LSI芯片10上。薄膜电容器30形成在中间基板20的凸块表面22上并且仅通过与凸块表面22连接的电源凸块6V、6G连接到LSI芯片10。因此,相比于经由引线和通过基板布线连接到半导体芯片的传统电容器,从LSI芯片10到薄膜电容器30的布线距离大大减小。因此,在根据第一实施例的半导体器件1中,从LSI芯片10到薄膜电容器30的布线距离减小,由此薄膜电容器30的降噪效果增加。结果,能够实现稳定的电源,并且能够增加高频操作期间LSI芯片10的可靠性。
4.第一实施例的其它示例
如图5所示,可在中间基板20的外部连接表面24上形成薄膜电容器30。在该情况下,薄膜电容器30通过中间基板20中形成的通孔塞25连接到电源凸块(6V、6G)。具体地,薄膜电容器30的第一平面电极31通过凸块连接部31V和通孔塞25V连接到电源凸块6V。薄膜电容器30的第二平面电极32通过凸块连接部32G和通孔塞25G连接到电源凸块6G。
在该情况下,同样,相比于经由引线和通过基板布线连接到LSI芯片10的传统电容器,可减小布线距离。因此,能够增加薄膜电容器30的降噪效果,并且能够实现稳定的电源,由此能够增加高频操作期间LSI芯片10的可靠性。
(第二实施例)
5.根据第二实施例的半导体器件的构造
现在,将参照图6至图11描述第二实施例。将用类似的符号指明与第一实施例的构件类似的构件,并且将省略对其的描述。因此,将仅描述与第一实施例的差别。
如图6所示,根据第二实施例的半导体器件1A与第一实施例的半导体器件1的不同之处仅在于设置在中间基板20上的电容器。具体地,在半导体器件1A中,除了半导体器件1的薄膜电容器30之外,在中间基板20上还设置多层陶瓷电容器(“芯片电容器”的示例)40。芯片电容器不限于多层陶瓷电容器(MLCC)。
多层陶瓷电容器40形成在中间基板20的外部连接表面24上,并且通过中间基板20中形成的通孔塞25VV、25GG并联连接到薄膜电容器30。具体地,如图6所示,多层陶瓷电容器40的第一电极41经由外部连接表面24上的焊盘26和通孔塞25VV连接到薄膜电容器30的第一平面电极31。多层陶瓷电容器40的第二电极42经由焊盘26和通孔塞25GG连接到薄膜电容器30的第二平面电极32。
5.第二实施例的效果
根据第二实施例,在将电容比薄膜电容器30大的多层陶瓷电容器40连接到LSI芯片10的电极焊盘11V、11G时,利用薄膜电容器30的第一平面电极和第二平面电极(31、32)作为低阻抗电源布线部。因此,相比于第一实施例,薄膜电容器30的降噪效果更进一步增加,由此能够实现稳定的电源,并且能够增加高频操作期间LSI芯片10的可靠性。
6.第二实施例的第一个其它示例
如图7所示,可从根据第二实施例的半导体器件1A的构造中省去薄膜电容器30。也就是说,在该示例中,半导体器件1B包括在中间基板20的外部连接表面(上表面)24上形成的多层陶瓷电容器40,作为中间基板20上设置的电容器。多层陶瓷电容器40通过形成在中间基板20中的通孔塞25VV、25GG连接到电源凸块(6V、6G)。
具体地,如图7所示,多层陶瓷电容器40的第一电极41经由通孔塞25VV和兼作电源焊盘21V的电源布线部27V连接到电源凸块6V。多层陶瓷电容器40的第二电极42经由通孔塞25GG和兼作电源焊盘21G的电源布线部27G连接到电源凸块6G。
在该情况下,同样,相比于经由引线和通过基板布线连接到半导体芯片的传统电容器,能够减小布线距离。因此,能够增加薄膜电容器30的降噪效果,由此,能够实现稳定的电源,并且能够增加高频操作期间LSI芯片10的可靠性。另外,因为该结构使得多层陶瓷电容器40设置在LSI芯片10上方,所以能够减小半导体器件的面积,从而有助于减小其上安装半导体器件的诸如母板的电路基板的尺寸。
7.第二实施例的第二个其它示例
如图8所示,可按将多层陶瓷电容器40连接到LSI芯片10的方式,对图7所示的半导体器件1B的构造进行修改。具体地,在图8所示的示例中,半导体器件1C包括形成在中间基板20的外部连接表面(上表面)24上的多层陶瓷电容器40,作为设置在中间基板20上的电容器。多层陶瓷电容器40经由形成在外部连接表面24上的电源布线部28V、28G连接到电源凸块(6V、6G)。
具体地,如图8所示,多层陶瓷电容器40的第一电极41通过兼作焊盘的电源布线部28V、通孔塞25V和电源焊盘21V连接到电源凸块6V。多层陶瓷电容器40的第二电极42通过兼作焊盘的电源布线部28G、通孔塞25G和电源焊盘21G连接到电源凸块6G。在该情况下,可用焊料抗蚀剂29覆盖中间基板20的外部连接表面24。
在该情况下,同样,相比于经由引线和通过基板布线连接到半导体芯片的传统电容器连,能够减小布线距离。因此,能够增加薄膜电容器30的降噪效果,由此能够实现稳定的电源,并且能够增加高频操作期间LSI芯片10的可靠性。另外,因为该结构使得多层陶瓷电容器40设置在LSI芯片10上方,所以能够减小半导体器件的面积,从而有助于减小其上安装半导体器件的诸如母板的电路基板的尺寸。另外,相比于图7中示出的半导体器件1B,通孔塞25的数量可减少。
8.第二实施例的第三其它示例
如图9所示,可按将多层陶瓷电容器40连接到LSI芯片10的方式,对图7的半导体器件1B的构造进行修改。具体地,在图9所示的示例中,半导体器件1D包括形成在中间基板20的外部连接表面(上表面)24上的多层陶瓷电容器40,作为设置在中间基板20上的电容器,如在半导体器件1B的情况中一样。
具体地,多层陶瓷电容器40的第一电极41经由形成在外部连接表面24上的焊盘26V、形成在中间基板20中的通孔塞25VV(第一通孔塞的示例)、形成在凸块表面22上的电源布线部(第一电源布线部的示例)27V连接到电源凸块(第一电源凸块的示例)6V。在该情况下,如图10所示,凸块连接部28GG兼作与通孔塞25G连接的焊盘23。如图11所示,凸块连接部27VV兼作与电源凸块6V连接的电源焊盘21V。
第二电极42经由形成在外部连接表面24上的电源布线部(第二电源布线部)28G和与通孔塞25VV分开的通孔塞25G(第二通孔塞的示例)连接到电源凸块(第二电源凸块的示例)6G。
另外,如图10和图11所示,电源布线部27V和电源布线部28G被分别形成为具有大致相同的四边形形状的平面电极,等同于图4中示出的薄膜电容器30的第一平面电极31和第二平面电极32。电源布线部27V和电源布线部28G可不被形成为如图10和图11所示的平面电极。
在该情况下,相比于图7的半导体器件1B,多层陶瓷电容器40的布线电路在凸块表面22和外部连接表面24之间分开。具体地,在凸块表面22上,形成与正电压关联的电源布线部27V,并且在外部连接表面24上,形成与地电压关联的电源布线部28G。因此,相比于图7中示出的半导体器件1B,多层陶瓷电容器40的布线电路的电路图案被简化并且其长度缩短。
在图10中示出的外部连接表面24上,如果分别处于四个位置的外部连接焊盘23V、23G将连接到处于多层陶瓷电容器40的两个位置的焊盘26,则电路图案可变得复杂并且变长。结果,趋于更容易地产生与电路图案关联的ESR或ESL。如果产生的ESR或ESL的值大,则布线电路的电特性可变得劣化。在本实施例中,能够减小ESR或ESL的值。
电源布线部27V和电源布线部28G被分别形成为平面电极,如图4中示出的薄膜电容器30的平面电极31、32的情况中一样。因此,电源布线部27V、中间基板20的绝缘体部、电源布线部28G构成与多层陶瓷电容器40并联连接的电容器。因此,通过例如调节绝缘体部的介电常数,相比于图7的半导体器件1B,能够进一步增加多层陶瓷电容器40的降噪效果。因此,能够实现稳定的电源,并且能够增加高频操作期间LSI芯片10的可靠性。
<其它实施例>
本发明不限于以上参照附图描述的实施例,并且可包括诸如在本发明的技术范围内的如下的各种其它实施例。
(1)在以上实施例中,已经描述了一个薄膜电容器30或多层陶瓷电容器40设置在中间基板20上的示例。然而,这并非限制。例如,三个薄膜电容器30可设置在中间基板20上,或者两个多层陶瓷电容器40可设置在中间基板20上。
(2)在以上实施例中,已经描述了提出将QFN半导体器件作为半导体器件的示例。然而,这并非限制。本发明可应用于例如QFP半导体器件或者事实上应用于设置有被面向上地管芯接合安装在支承体上的半导体芯片的任何半导体器件。
参考标记列表
1 半导体器件
2 支承体
3 外部连接部
4 引线
6 连接凸块
6V、6G 电源凸块
10 LSI芯片
11 电极焊盘
20 中间基板
21V、21G 电源焊盘
24 外部连接表面
25 通孔塞
27V 第一电源布线部
28G 第二电源布线部
30 薄膜电容器
40 多层陶瓷电容器
41 第一电极
42 第二电极
Claims (7)
1.一种半导体器件,包括:
支承体;
半导体芯片,所述半导体芯片被面向上地管芯接合安装在所述支承体上;
多个外部连接部,所述多个外部连接部将所述半导体芯片电连接到外部;
中间基板,所述中间基板设置在所述半导体芯片的与所述支承体相反的一侧,并且将所述半导体芯片连接到所述多个外部连接部;以及
多个连接凸块,所述多个连接凸块连接所述半导体芯片和所述中间基板,
其中:
所述半导体芯片包括通过所述多个连接凸块连接到所述中间基板连接的多个电极焊盘;
所述多个连接凸块包括用于向所述半导体芯片供电的多个电源凸块;并且
所述中间基板包括:
多个电源焊盘,所述多个电源焊盘通过所述多个电源凸块连接到所述多个电极焊盘,
凸块表面,所述凸块表面面对所述半导体芯片,并且具有在其上形成的所述多个电源焊盘,
外部连接表面,所述外部连接表面设置在所述凸块表面的相反侧,并且具有在其上形成的连接到所述外部连接部的多个外部连接焊盘,以及
电容器,所述电容器连接到所述多个电源凸块,
其中,所述电容器还包括形成在所述外部连接表面上的芯片电容器,
其中,所述芯片电容器通过形成在所述中间基板中的通孔塞并联连接到所述电容器。
2.根据权利要求1所述的半导体器件,其中,所述电容器是薄膜电容器,所述薄膜电容器形成在所述中间基板的所述凸块表面上并且连接到所述多个电源凸块。
3.根据权利要求1所述的半导体器件,其中,所述电容器是形成在所述外部连接表面上的薄膜电容器,
其中,所述薄膜电容器通过形成在所述中间基板中的通孔塞连接到所述多个电源凸块。
4.根据权利要求1所述的半导体器件,其中,所述电容器是形成在所述外部连接表面上的芯片电容器,
其中,所述芯片电容器通过形成在所述中间基板中的通孔塞连接到所述多个电源凸块。
5.根据权利要求4所述的半导体器件,其中:
所述电容器包括第一电极和第二电极;
所述多个电源凸块包括第一电源凸块和第二电源凸块,所述第一电源凸块用于向所述半导体芯片施加一个极性的电源电压,所述第二电源凸块用于向所述半导体芯片施加另一个极性的电源电压;
所述通孔塞包括第一通孔塞和第二通孔塞,所述第一通孔塞将所述第一电极连接到所述第一电源凸块,所述第二通孔塞将所述第二电极连接到所述第二电源凸块;
所述芯片电容器的所述第一电极通过形成在所述外部连接表面上的焊盘、所述第一通孔塞、形成在所述凸块表面上的第一电源布线部连接到所述第一电源凸块;并且
所述芯片电容器的所述第二电极通过形成在所述外部连接表面上的第二电源布线部和所述第二通孔塞连接到所述第二电源凸块。
6.根据权利要求1所述的半导体器件,其中,所述电容器是形成在所述外部连接表面上的芯片电容器,
其中,所述芯片电容器经由形成在所述外部连接表面上的电源布线部连接到所述电源凸块。
7.根据权利要求1至6中的任一项所述的半导体器件,其中:
所述多个电源焊盘和所述多个外部连接焊盘通过形成在所述中间基板中的通孔塞连接;并且
通过引线接合连接所述多个外部连接焊盘和所述多个外部连接部。
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CN118471943A (zh) * | 2024-07-08 | 2024-08-09 | 苏州华太电子技术股份有限公司 | 芯片封装结构及芯片封装方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177670A (en) * | 1991-02-08 | 1993-01-05 | Hitachi, Ltd. | Capacitor-carrying semiconductor module |
CN1533227A (zh) * | 2003-03-19 | 2004-09-29 | �ձ�������ҵ��ʽ���� | 中间板、带有中间板的基板和结构部件以及制造中间板的方法 |
TW200620780A (en) * | 2004-03-25 | 2006-06-16 | Integral Wave Technologies Inc | Switched capacitor power supply system and method |
US7378733B1 (en) * | 2006-08-29 | 2008-05-27 | Xilinx, Inc. | Composite flip-chip package with encased components and method of fabricating same |
TW200834879A (en) * | 2007-02-06 | 2008-08-16 | Stats Chippac Ltd | Integrated circuit packaging system with interposer |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04211191A (ja) * | 1990-02-09 | 1992-08-03 | Hitachi Ltd | 実装構造体 |
JP2002057244A (ja) * | 2000-08-10 | 2002-02-22 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002289756A (ja) * | 2001-03-26 | 2002-10-04 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2004304181A (ja) * | 2003-03-19 | 2004-10-28 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
JP2004296613A (ja) | 2003-03-26 | 2004-10-21 | Renesas Technology Corp | 半導体装置 |
JP2008124072A (ja) * | 2006-11-08 | 2008-05-29 | Toshiba Corp | 半導体装置 |
-
2015
- 2015-04-07 JP JP2017510823A patent/JPWO2016162938A1/ja active Pending
- 2015-04-07 WO PCT/JP2015/060808 patent/WO2016162938A1/ja active Application Filing
- 2015-04-07 CN CN201580000517.3A patent/CN106233459B/zh not_active Expired - Fee Related
- 2015-04-07 US US14/781,975 patent/US9653421B2/en active Active
- 2015-09-23 TW TW104131464A patent/TWI566350B/zh not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177670A (en) * | 1991-02-08 | 1993-01-05 | Hitachi, Ltd. | Capacitor-carrying semiconductor module |
CN1533227A (zh) * | 2003-03-19 | 2004-09-29 | �ձ�������ҵ��ʽ���� | 中间板、带有中间板的基板和结构部件以及制造中间板的方法 |
TW200620780A (en) * | 2004-03-25 | 2006-06-16 | Integral Wave Technologies Inc | Switched capacitor power supply system and method |
US7378733B1 (en) * | 2006-08-29 | 2008-05-27 | Xilinx, Inc. | Composite flip-chip package with encased components and method of fabricating same |
TW200834879A (en) * | 2007-02-06 | 2008-08-16 | Stats Chippac Ltd | Integrated circuit packaging system with interposer |
Also Published As
Publication number | Publication date |
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US20170040278A1 (en) | 2017-02-09 |
TWI566350B (zh) | 2017-01-11 |
WO2016162938A1 (ja) | 2016-10-13 |
US9653421B2 (en) | 2017-05-16 |
JPWO2016162938A1 (ja) | 2017-08-31 |
CN106233459A (zh) | 2016-12-14 |
TW201637155A (zh) | 2016-10-16 |
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