CN110494973A - 薄膜电容器构造及具备该薄膜电容器构造的半导体装置 - Google Patents

薄膜电容器构造及具备该薄膜电容器构造的半导体装置 Download PDF

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Publication number
CN110494973A
CN110494973A CN201780089382.1A CN201780089382A CN110494973A CN 110494973 A CN110494973 A CN 110494973A CN 201780089382 A CN201780089382 A CN 201780089382A CN 110494973 A CN110494973 A CN 110494973A
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opening portion
thin film
insulating film
film capacitor
hole
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小山田成圣
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Noda Jikyou
Noda Screen Co Ltd
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Noda Jikyou
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    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
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Abstract

薄膜电容器构造(50)与在电极垫面(2S)呈面阵状地配置有多个电极垫(3G、3P、3S)的面阵式集成电路(2)的电极垫面(2S)接合。薄膜电容器构造(50)具备薄膜电容器(10)、第一绝缘膜(21)、第二绝缘膜(22)及多个贯通孔(30P、30G、30S)，薄膜电容器(10)包括第一薄板电极(11)、第二薄板电极(13)及形成于第一薄板电极(11)与第二薄板电极(12)之间的薄膜电介质层(12)。多个贯通孔(30P、30G、30S)从第一绝缘膜(21)经由薄膜电容器(10)贯通到第二绝缘膜(22)，形成于与多个电极垫(3G、3P、3S)对应的位置。

Description

薄膜电容器构造及具备该薄膜电容器构造的半导体装置
技术领域
本发明涉及薄膜电容器构造及具备该薄膜电容器构造的半导体装置，详细地说，涉及用于降低面阵式集成电路的电源电路中的阻抗的薄膜电容器的构造。
背景技术
以往，作为这种薄膜电容器，例如已知在专利文献1中公开的技术。在专利文献1中公开了如下的薄膜电容器10：在能够作为中间基板使用的层叠式电容器中，能够有效地排除成为电感增加的原因的引线部，进而能够实现低阻抗化及宽带宽化。
现有技术文献
专利文献
专利文献1：日本特开2005-33195号公报
发明内容
发明要解决的技术问题
但是，在上述的以往薄膜电容器10中，虽然能够形成与面阵式集成电路2对应的薄膜电容器，但如专利文献1的图1及图4等所示，集成电路2和薄膜电容器10的各电极14、17经由形成于薄膜电容器10的上部的端子阵列5的端子5a、5b连接。因此，需要在薄膜电容器10的上部形成端子阵列5。另外，担心在高频区域中，端子阵列5的端子5a、5b导致电感的增加。
因此，本说明书中，提供能够使薄膜电容器与集成电路的连接结构简化并且能够降低薄膜电容器的布线的阻抗的电容器构造及具备该电容器构造的半导体装置。
用于解决技术问题的技术方案
由本说明书公开的薄膜电容器构造是与在电极垫面呈面阵状地配置有多个电极垫的面阵式集成电路的所述电极垫面接合的薄膜电容器构造，所述多个电极垫包括电源垫、接地垫及信号垫，该薄膜电容器构造具备：薄膜电容器，包括第一薄板电极、第二薄板电极及形成于所述第一薄板电极与所述第二薄板电极之间的薄膜电介质层；第一绝缘膜，将所述第一薄板电极绝缘；第二绝缘膜，将所述第二薄板电极绝缘；及多个贯通孔，从所述第一绝缘膜经由所述薄膜电容器贯通到所述第二绝缘膜，形成在与所述多个电极垫对应的位置，包括形成于与所述电源垫对应的位置的电源用贯通孔、形成于与所述接地垫对应的位置的接地用贯通孔及形成于与所述信号垫对应的位置的信号用贯通孔。
根据本结构，设置有多个贯通孔，该多个贯通孔从第一绝缘膜经由薄膜电容器贯通到第二绝缘膜，并形成于与多个电极垫对应的位置。因此，在将薄膜电容器与面阵式集成电路接合时，通过向该多个贯通孔填充铜膏等导电构件直至到达电极垫为止，由此能够将薄膜电容器与面阵式集成电路接合。由此，不需要在薄膜电容器的上部形成端子阵列，也不需要在面阵式集成电路的电极垫上形成连接凸起。另外，能够以大致最短距离将薄膜电容器与面阵式集成电路的电极垫面结合。其结果，能够简化薄膜电容器与集成电路的连接结构，并且能够降低薄膜电容器的布线的阻抗。
在上述薄膜电容器构造中，也可以是，所述第一薄板电极包括：第一伸出部，伸出到所述接地用贯通孔内；第一开口部，形成于与所述电源垫及所述信号垫对应的位置；及接地垫用开口部，形成于与所述接地垫对应的位置，具有在周边形成所述第一伸出部的平面形状，所述第二薄板电极包括：第二伸出部，伸出到所述电源用贯通孔内；第二开口部，形成于与所述接地垫及所述信号垫对应的位置；及电源垫用开口部，形成于与所述电源垫对应的位置，具有在周边形成所述第二伸出部的平面形状。
根据本结构，在多个贯通孔填充铜膏等导电构件到电极垫时，因第一伸出部及第二伸出部使导电构件与第一薄板电极及第二薄板电极的接合面积增加。由此，能够使导电构件与第一薄板电极及第二薄板电极更牢固地接合，由此提高导电构件与各薄板电极接合的可靠性。另外，能够由各开口部形成电源用贯通孔、接地用贯通孔及信号用贯通孔。另外，能够由接地垫用开口部以简单的结构形成第一伸出部，能够由电源垫用开口部以简单的结构形成第二伸出部。
另外，在上述薄膜电容器构造中，也可以是，所述薄膜电介质层包括电介质开口部，该电介质开口部形成于与所述多个电极垫对应的位置，具有比所述第一开口部及所述第二开口部的开口面积小的开口面积，所述第一绝缘膜包括形成于与所述多个电极垫对应的位置的第一绝缘膜开口部，所述第二绝缘膜包括形成于与所述多个电极垫对应的位置的第二绝缘膜开口部，所述电源用贯通孔由第一绝缘膜开口部、所述电介质开口部、所述电源垫用开口部及所述第二绝缘膜开口部构成，所述接地用贯通孔由第一绝缘膜开口部、所述接地垫用开口部及所述第二绝缘膜开口部构成，所述信号用贯通孔由第一绝缘膜开口部、所述电介质开口部及所述第二绝缘膜开口部构成。
根据本结构，能够将第一薄板电极的一部分及第二薄板电极的一部分绝缘，且能够由各开口部形成电源用贯通孔、接地用贯通孔及信号用贯通孔。
另外，在上述薄膜电容器构造中，也可以是，所述第一开口部、所述第二开口部及所述电介质开口部在俯视下具有正方形的形状，所述电源垫用开口部及所述接地垫用开口部在俯视下具有十字状的形状。
根据本结构，由于能够使用于形成各开口部的掩膜的形状简单，所以能够简单地形成各开口部。
另外，由本说明书公开的半导体装置具备：面阵式集成电路；上述任意所述的薄膜电容器构造，贴附于所述面阵式集成电路的电极垫面；及导电材料，填充在所述电源用贯通孔、所述接地用贯通孔及所述信号用贯通孔中直至到达所述多个电极垫位置为止。
根据本结构，能够使薄膜电容器与面阵式集成电路的连接结构简化，并且能够降低薄膜电容器的布线的阻抗。
在上述半导体装置中，可以在所述导电材料的所述电极垫侧的相反侧设置有外部连接用的连接垫。
根据本结构，例如能够通过在连接垫形成焊锡微小凸起，构筑具备薄膜电容器的面阵式半导体装置，能够使半导体装置与外部电路连接。
另外，在上述半导体装置中可以具备中间基板，该中间基板设置于所述薄膜电容器构造的所述电极垫面侧的相反侧，在与所述多个电极垫对应的位置具有多个中间基板垫。
根据本结构，能够通过在中间基板设置再布线层，变更面阵式集成电路的电极垫间距。由此，能够使半导体装置连接于与集成电路的电极间距不同的电极间距的外部电路基板，例如主板。
发明的效果
根据本发明，能够简化薄膜电容器和集成电路的连接结构，并且能够降低薄膜电容器的布线的阻抗。
附图说明
图1是示出实施方式的半导体装置的概略剖视图。
图2是示出半导体装置的电极垫面的俯视图。
图3是薄膜电容器的接地电极的局部俯视图。
图4是薄膜电容器的薄膜电介质层的局部俯视图
图5是薄膜电容器的电源电极的局部俯视图。
图6是薄膜电容器的局部俯视图。
图7是图6的局部放大图。
图8是薄膜电容器构造接合于LSI芯片的状态的剖视图。
图9是示出半导体装置(薄膜电容器构造)的制造方法的概略局部剖视图。
图10是示出半导体装置(薄膜电容器构造)的制造方法的概略局部剖视图
图11是示出半导体装置的制造方法的概略局部剖视图。
图12是示出另外的例子的接地垫用开口部的概略俯视图。
图13是示出另外的例子的接地垫用开口部的概略俯视图。
图14是示出另外的例子的半导体装置的概略局部剖视图。
图15是示出图14的半导体装置的制造方法的局部剖视图。
图16是示出图14的半导体装置的另外的制造方法的局部剖视图。
具体实施方式
＜实施方式＞
参照图1～图11说明一个实施方式。此外，图中，同一标号表示同一或相当部分。另外，将用图1的箭头Z表示的方向设为上方向。此外，为了便于说明，在图1等的剖视图中放大薄膜部分的厚度方向的尺寸而示出。因此，剖视图的上下方向尺寸与实际尺寸不同。
1.半导体装置的结构
如图1所示，半导体装置100主要包括LSI芯片(“面阵式集成电路”的一个例子)2和薄膜电容器构造50。此外，图1是与图7的单点划线A-A表示的位置对应的半导体装置100的剖视图。
如图2所示，在LSI芯片2的焊接侧的面即电极垫面2S呈面阵状地形成有多个电极垫3。多个电极垫3包括电源垫3P、接地垫3G及信号垫3S。经由薄膜电容器构造50向电源垫3P施加高压侧电压，例如5V的电压，经由薄膜电容器构造50向接地垫3G施加低压侧电压，例如，零V的电压。另外，经由信号垫3S输入输出控制信号等。如图2所示，电源垫3P、接地垫3G及信号垫3S分散配置于大致整个电极垫面2S。各电极垫3被保护膜8隔离。此外，在说明中，在不需要区别电源垫3P、接地垫3G及信号垫3S的情况下，仅表示为“电极垫3”。在本实施方式中，电极垫3的尺寸例如约为50μm见方左右，电极垫3的配置间距例如约为150μm。
另外，如图1所示，在后述的薄膜电容器构造50的(贯通孔30G、30P、30S)中填充有导电材料4，例如铜膏。在该导电材料4的电极垫3侧的相反侧，换言之，在导电材料4的下方侧设置有外部连接用的连接垫5。
2.薄膜电容器构造的结构
如图1所示，薄膜电容器构造50主要包括薄膜电容器10、第一绝缘膜21及第二绝缘膜22。
薄膜电容器10包括与地(低压电位)连接的接地电极(“第一薄板电极”的一个例子)11、与电源(高压电位)连接的电源电极(“第二薄板电极”的一个例子)13及形成于接地电极11与电源电极13之间的薄膜电介质层12。
接地电极11是薄膜金属电极，如图3所示，包括第一开口部11A和接地垫用开口部11B。第一开口部11A形成于与电源垫3P及信号垫3S对应的位置。接地垫用开口部11B形成于与接地垫3G对应的位置，具有在其周边形成将后述的接地用贯通孔30G的一部分堵住的伸出部11C的平面形状。在本实施方式中，如图3所示，第一开口部11A在俯视下具有正方形的形状，接地垫用开口部11B在俯视下具有十字状的形状。与接地垫用开口部11B的十字部相邻的接地电极11的四处伸出部11C堵住接地用贯通孔30G的一部分，换言之，与接地用贯通孔30G重叠。在此，四处伸出部11C是伸出到接地用贯通孔30G内的“第一伸出部”的一个例子。
如图4所示，薄膜电介质层12包括形成于与多个电极垫3对应的位置，即与电源垫3P、接地垫3G及信号垫3S对应的位置的电介质开口部12A。在本实施方式中，电介质开口部12A在俯视下具有正方形的形状，具有比上述第一开口部11A及后述的第二开口部13A的开口面积小的开口面积。
电源电极13是薄膜金属电极，如图5所示，包括第二开口部13A和电源垫用开口部13B。第二开口部13A形成于与接地垫3G及信号垫3S对应的位置。电源垫用开口部13B形成于与电源垫3P对应的位置，具有在其周边形成伸出部13C的平面形状。在本实施方式中，如图5所示，与第一开口部11A同样地，第二开口部13A在俯视下具有正方形的形状，电源垫用开口部13B与接地垫用开口部11B同样地，在俯视下具有十字状的形状。与电源垫用开口部13B的十字部相邻的电源电极13的四处伸出部13C堵住后述的电源用贯通孔30P的一部分，换言之，与电源用贯通孔30P重叠。在此，四处伸出部13C是伸出到电源用贯通孔30P内的“第二伸出部”的一个例子。
第一绝缘膜21将接地电极11绝缘。第一绝缘膜21包括在与多个电极垫3对应的位置，即，在与电源垫3P、接地垫3G及信号垫3S对应的位置形成的第一绝缘膜开口部21A(参照图8)。此外，图8是与图7的单点划线A-A表示的位置对应的剖视图。
另外，第二绝缘膜22将电源电极13绝缘。第二绝缘膜22与第一绝缘膜21同样地，包括在与多个电极垫3对应的位置，即，在与电源垫3P、接地垫3G及信号垫3S对应的位置形成的第二绝缘膜开口部22A(包括图8)。
另外，薄膜电容器构造50包括从第一绝缘膜21经由薄膜电容器10贯通到第二绝缘膜22且形成于与多个电极垫3对应的位置的多个贯通孔(30P、30G、30S)。多个贯通孔(30P、30G、30S)包括形成于与电源垫3P对应的位置的电源用贯通孔30P、形成于与接地垫3G对应的位置的接地用贯通孔30G和形成于与信号垫3S对应的位置的信号用贯通孔30S(参照图6、图7及图8)。
详细地说，如图8所示，电源用贯通孔30P由第一绝缘膜开口部21A、电介质开口部12A、电源垫用开口部13B及第二绝缘膜开口部22A构成。另外，接地用贯通孔30G由第一绝缘膜开口部21A、接地垫用开口部11B及第二绝缘膜开口部22A构成。另外，信号用贯通孔30S由第一绝缘膜开口部21A、电介质开口部12A及第二绝缘膜开口部22A构成。此外，构成各贯通孔(30G、30P、30S)的开口部的结构不限于上述结构。
3.半导体装置(薄膜电容器构造)的制造方法
接着，参照图9～图11，说明半导体装置100的制造方法的一个例子。此外，半导体装置100的制造方法中的图9(a)到图10(g)示出薄膜电容器构造50的制造方法。另外，图9(c)～图11(j)以与图1的上下关系相反地描绘。另外，图9～图11所示的制造工序的顺序表示一个例子，并不对其进行限定。
在该制造方法中，首先在ABF(Ajinomoto Build-Up Film)等具有粘接性及固化性的支承基材31上，从下依次层叠没有形成开口部的固体状态的接地电极11、薄膜电介质层12及电源电极13(未图示)。在此，接地电极11及电源电极13例如由铜箔构成，薄膜电介质层12例如由STO(钛酸锶)膜构成。在该状态下，为了形成电源电极13的各开口部(13A、13B)，对电源电极13进行选择性地蚀刻。之后，利用激光加工或等离子体的干蚀刻或利用溶剂的湿蚀刻，从而形成薄膜电介质层12的电介质开口部12A。该状态在图9(a)中示出。
接着，将具有粘接性及固化性的环氧类树脂或聚酰亚胺类树脂等有机绝缘薄板22M载置在电源电极13上，并对有机绝缘薄板22M进行热压接合。该状态在图9(b)中示出。如图9(b)所示，通过热压接合，有机绝缘薄板22M填充电介质开口部12A及第二开口部13A，到达固体状态的接地电极11M。
接着，除去支承基材31，将支承基材31被除去了的半加工品上下颠倒，将半加工品固定于ABF等具有粘接性及固化性的新的支承基材32上。该状态在图9(c)中示出。
接着，对固体状态的接地电极11M进行选择性地蚀刻而形成各开口部(11A、11B)，并且对有机绝缘薄板22M进行蚀刻而形成第二绝缘膜22及第二绝缘膜开口部22A。该状态在图9(d)中示出。
接着，如图10(e)所示，在接地电极11等上涂敷抗蚀膜等作为成为第一绝缘膜21的绝缘膜21M。接着，对绝缘膜21M进行选择蚀刻，由此如图10(f)所示，形成电源用贯通孔30P、接地用贯通孔30G及信号用贯通孔30S。接着，通过除去支承基材32，完成图10(g)所示的薄膜电容器构造50。
接着，如图10(h)所示，将薄膜电容器构造50接合于LSI芯片2的电极垫面2S。作为接合的方法，使用薄型且具有粘接性的DAF(Die Attach Film：粘贴膜)材料或NCF(NonConductive Film：非导电膜)等粘接构件(未图示)进行接合。或者，可以涂敷不需要清洗的助焊剂，利用助焊剂的微黏着性接合。而且，在第二绝缘膜22是具有暂时粘接和正式粘接的功能的构件的情况下，也能够由第二绝缘膜22兼用作粘接构件。
在此，接地电极11和电源电极13形成为，在大致全部区域与LSI芯片2的电极垫面2S维持平行，在利用刮刀等填充导电性膏(铜膏等)时能够以面接触。由此，在将薄膜电容器构造50接合于LSI芯片2的电极垫面2S时，能够增大接合面积，降低接触阻力，进一步提高接合的可靠性。
接着，如图11(i)所示，使用刮刀等而通过作为导电材料的例如固化性铜膏4来填充电源用贯通孔30P、接地用贯通孔30G及信号用贯通孔30S，并使铜膏4固化。此时，各铜膏4和各电极垫3直接电连接。
接着，如图11(j)所示，在铜膏4上的与电源用贯通孔30P、接地用贯通孔30G及信号用贯通孔30S对应的位置形成用于与插入基板等电路基板连接的外部连接用的外部连接垫5。接着，除去形成有外部连接垫5的部位而形成阻焊膜等保护膜7，使微焊锡球6附着于外部连接垫5。由此，完成图1所示那样的半导体装置100。
4.实施方式的效果
如上所述，在本实施方式的薄膜电容器构造50中，设置有多个贯通孔(30G、30P、30S)，该多个贯通孔(30G、30P、30S)从第一绝缘膜21经由薄膜电容器10贯通到第二绝缘膜22，且形成在与LSI芯片2的多个电极垫(3G、3P、3S)对应的位置。因此，在将薄膜电容器构造50换言之将薄膜电容器10接合于LSI芯片2(面阵式集成电路)时，例如本实施方式那样，向多个贯通孔(30G、30P、30S)填充铜膏这样的导电构件4而直至到达电极垫3为止，由此能够将薄膜电容器10接合于LSI芯片2。由此，不需要在薄膜电容器10的上部形成端子阵列，也不需要在LSI芯片2的电极垫3上形成连接凸起。另外，能够以大致最短距离将薄膜电容器10与LSI芯片2的电极垫面2S结合。其结果，能够将薄膜电容器10与LSI芯片2(集成电路)的连接结构简化，并且能够降低薄膜电容器10的布线的阻抗。
另外，在向多个贯通孔30填充铜膏等导电构件4而直至到达电极垫3为止时，通过接地电极11的伸出部11C及电源电极13的伸出部13C，使导电构件4与接地电极11及电源电极13接合的面积增加。由此，能够使导电构件4与接地电极11及电源电极13的接合更牢固，其结果，提高导电构件4与各电极(11、12)接合的可靠性。
此时，第一伸出部11C是伴随十字状的接地垫用开口部11B的形成而形成的，另外，第二伸出部13C是伴随十字状的电源垫用开口部13B的形成而形成的。因此，能够以简单的方法形成第一伸出部11C及第二伸出部13C。
另外，第一开口部11A、第二开口部13A及电介质开口部12A在俯视下具有正方形的形状，电源垫用开口部13B及接地垫用开口部11B在俯视下具有十字状的形状。因此，能够使用于形成各开口部的掩膜的形状简单，由此，各开口部的形成简单。另外，能够伴随着接地垫用开口部11B及电源垫用开口部13B的形成同时形成第一伸出部11C及第二伸出部13C。
＜其他实施方式＞
本发明不限于根据上述叙述及附图说明的实施方式，例如下面那样的实施方式也包含于本发明的技术范围。
(1)在上述实施方式中，示出了第一开口部11A、第二开口部13A及电介质开口部12A在俯视下具有正方形的形状且接地垫用开口部11B及电源垫用开口部13B在俯视下具有十字状的形状的例子，但不限于此。例如，接地垫用开口部11B及电源垫用开口部13B可以仅为图12所示那样的矩形状，或者可以是图13所示那样的形状。另外，第一开口部11A、第二开口部13A及电介质开口部12A例如也可以在俯视下具有圆形的形状。
(2)在上述实施方式中，示出了由铜膏4构成导电材料的例子，但是不限于此。导电材料例如由镀铜构成。
(3)在上述实施方式中，示出了将图1中的下方的电极作为接地电极11(第一薄板电极)且将上方的电极作为电源电极13(第二薄板电极)的例子，但是不限于此，也可以相反。即，也可以将图1中的下方的电极作为电源电极13(第二薄板电极)，将上方的电极作为接地电极11(第一薄板电极)。
(4)半导体装置100的结构不限于图1所示的结构。例如，如图14所示的半导体装置100A那样，也可以是包括设置于薄膜电容器构造50的电极垫面2S侧的相反侧的插入基板(中间基板)60的结构。在插入基板60上，在与LSI芯片2的电源垫3P、接地垫3G及信号垫3S对应的位置形成有中间基板垫61P、中间基板垫61G及中间基板垫61S，且形成有将各中间基板垫61绝缘分离的绝缘层62。在该结构中，例如，通过在中间基板60设置再布线层，能够变更LSI芯片2的电极垫3的间距。由此，能够将半导体装置100A连接于与LSI芯片2的电极间距不同的电极间距的外部电路基板，例如主板。此外，在图14等中，插入基板60内的其他结构，例如再布线层等的图示省略。
在包括插入基板60的结构的情况下，关于LSI芯片2与插入基板60的连接，如图15所示，经由铜膏4等先将薄膜电容器构造50接合于LSI芯片2，将这样形成的部件通过热压接合与插入基板60连接。或者，如图16所示，也可以经由铜膏4等先将薄膜电容器构造50接合于插入基板60，将这样形成的构件通过热压接合与LSI芯片2连接。
标号说明
2…LSI芯片(集成电路)、2S…电极垫面、3G…接地垫(电极垫)、3P…电源垫(电极垫)、3S…信号垫(电极垫)、5…外部连接垫、10…薄膜电容器、11…接地电极(第一薄板电极)、11A…第一开口部、11B…接地垫用开口部、11C…伸出部(第一伸出部)、12…薄膜电介质层、13…电源电极、13A…第二开口部、13B…电源用开口部、13C…伸出部(第二伸出部)、30G…接地用贯通孔、30P…电源用贯通孔、30S…信号用贯通孔、50…薄膜电容器构造、60…插入基板、61…中间基板垫、100、100A…半导体装置。

Claims (7)

1.一种薄膜电容器构造，是与在电极垫面呈面阵状地配置有多个电极垫的面阵式集成电路的所述电极垫面接合的薄膜电容器构造，所述多个电极垫包括电源垫、接地垫及信号垫，
该薄膜电容器构造具备：
薄膜电容器，包括第一薄板电极、第二薄板电极及形成于所述第一薄板电极与所述第二薄板电极之间的薄膜电介质层；
第一绝缘膜，将所述第一薄板电极绝缘；
第二绝缘膜，将所述第二薄板电极绝缘；及
多个贯通孔，从所述第一绝缘膜经由所述薄膜电容器贯通到所述第二绝缘膜，形成在与所述多个电极垫对应的位置，包括形成于与所述电源垫对应的位置的电源用贯通孔、形成于与所述接地垫对应的位置的接地用贯通孔及形成于与所述信号垫对应的位置的信号用贯通孔。
2.根据权利要求1所述的薄膜电容器构造，其中，
所述第一薄板电极包括：
第一伸出部，伸出到所述接地用贯通孔内；
第一开口部，形成于与所述电源垫及所述信号垫对应的位置；及
接地垫用开口部，形成于与所述接地垫对应的位置，具有在周边形成所述第一伸出部的平面形状，
所述第二薄板电极包括：
第二伸出部，伸出到所述电源用贯通孔内；
第二开口部，形成于与所述接地垫及所述信号垫对应的位置；及
电源垫用开口部，形成于与所述电源垫对应的位置，具有在周边形成所述第二伸出部的平面形状。
3.根据权利要求2所述的薄膜电容器构造，其中，
所述薄膜电介质层包括电介质开口部，该电介质开口部形成于与所述多个电极垫对应的位置，具有比所述第一开口部及所述第二开口部的开口面积小的开口面积，
所述第一绝缘膜包括形成于与所述多个电极垫对应的位置的第一绝缘膜开口部，
所述第二绝缘膜包括形成于与所述多个电极垫对应的位置的第二绝缘膜开口部，
所述电源用贯通孔由第一绝缘膜开口部、所述电介质开口部、所述电源垫用开口部及所述第二绝缘膜开口部构成，
所述接地用贯通孔由第一绝缘膜开口部、所述接地垫用开口部及所述第二绝缘膜开口部构成，
所述信号用贯通孔由第一绝缘膜开口部、所述电介质开口部及所述第二绝缘膜开口部构成。
4.根据权利要求3所述的薄膜电容器构造，其中，
所述第一开口部、所述第二开口部及所述电介质开口部在俯视下具有正方形的形状，
所述电源垫用开口部及所述接地垫用开口部在俯视下具有十字状的形状。
5.一种半导体装置，具备：
面阵式集成电路；
权利要求1～4中任一项所述的薄膜电容器构造，与所述面阵式集成电路的电极垫面接合；及
导电材料，填充在所述电源用贯通孔、所述接地用贯通孔及所述信号用贯通孔中直至到达所述多个电极垫为止。
6.根据权利要求5所述的半导体装置，其中，
在所述导电材料的所述电极垫侧的相反侧设置有外部连接用的连接垫。
7.根据权利要求5所述的半导体装置，其中，
具备中间基板，该中间基板设置于所述薄膜电容器构造的所述电极垫面侧的相反侧，在与所述多个电极垫对应的位置具有多个中间基板垫。
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