TW201901716A - 薄膜電容器構造及具備該薄膜電容器構造之半導體裝置 - Google Patents

薄膜電容器構造及具備該薄膜電容器構造之半導體裝置 Download PDF

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TW201901716A
TW201901716A TW107116537A TW107116537A TW201901716A TW 201901716 A TW201901716 A TW 201901716A TW 107116537 A TW107116537 A TW 107116537A TW 107116537 A TW107116537 A TW 107116537A TW 201901716 A TW201901716 A TW 201901716A
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opening
pad
electrode
insulating film
ground
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TW107116537A
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TWI675387B (zh
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小山田成聖
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日商野田士克林股份有限公司
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Abstract

薄膜電容器構造(50)接合於面陣列狀地配置複數個電極墊(3G、3P、3S)於電極墊面(2S)的面陣列型積體電路(2)的電極墊面(2S)。薄膜電容器構造(50)具備：包含第1片狀電極(11)、第2片狀電極(13)及形成於第1片狀電極(11)與第2片狀電極(12)之間的薄膜介電體層(12)的薄膜電容器(10)、第1絕緣膜(21)、第2絕緣膜(22)、複數個貫通孔(30P、30G、30S)。複數個貫通孔(30P、30G、30S)從第1絕緣膜(21)經由薄膜電容器(10)貫通至第2絕緣膜(22)，形成於與複數個電極墊(3G、3P、3S)對應的位置。

Description

薄膜電容器構造及具備該薄膜電容器構造之半導體裝置
本發明涉及薄膜電容器構造及具備該薄膜電容器構造之半導體裝置，詳細而言涉及用於使在面陣列型積體電路的電源電路的阻抗減低的薄膜電容器的構造。
歷來，此種薄膜電容器方面，例如已知揭露於專利文獻1的技術。在專利文獻1，已揭露一種薄膜電容器10，可於可使用作為中間基板的層積型電容器方面，有效地排除成為電感增加的原因的佈接線部，進而可謀求低阻抗化及廣帶化。 [先前技術文獻] [專利文獻]
[專利文獻1] 日本特開2005-33195號公報
[發明所欲解決之問題]
然而，於上述的歷來的薄膜電容器10，雖可形成應付面陣列型積體電路2的薄膜電容器，惟如示於專利文獻1的圖1及圖4等，積體電路2與薄膜電容器10的各電極14、17係經由形成於薄膜電容器10之上部的端子陣列5的端子5a、5b而連接者。為此，需要於薄膜電容器10之上部形成端子陣列5。此外，於高頻區域，具有端子陣列5的端子5a、5b所致的對於電感的增加的影響之懸念。
所以，在本說明書，提供一種電容器構造及具備該電容器構造的半導體裝置，可簡略化薄膜電容器與積體電路的連接構成，同時可減低薄膜電容器的佈線方面的阻抗。 [解決問題之技術手段]
透過本說明書揭露的薄膜電容器構造一種薄膜電容器構造，接合於面陣列狀地配置複數個電極墊於電極墊面的面陣列型積體電路的前述電極墊面，前述複數個電極墊包含電源墊、接地墊及信號墊，該薄膜電容器構造具備：薄膜電容器，其包含第1片狀電極、第2片狀電極及形成於前述第1片狀電極與前述第2片狀電極之間的薄膜介電體層；第1絕緣膜，其將前述第1片狀電極絕緣；第2絕緣膜，其將前述第2片狀電極絕緣；複數個貫通孔，其係從前述第1絕緣膜經由前述薄膜電容器貫通至前述第2絕緣膜且形成於與前述複數個電極墊對應之位置的複數個貫通孔，包含形成於與前述電源墊對應的位置的電源用貫通孔、形成於與前述接地墊對應的位置的接地用貫通孔及形成於與前述信號墊對應的位置的信號用貫通孔。 　　依本構成時，設置複數個貫通孔，其從第1絕緣膜經由薄膜電容器貫通至第2絕緣膜，形成於與複數個電極墊對應的位置。為此，在將薄膜電容器接合於面陣列型積體電路之際，於此複數個貫通孔填充銅膏等的導電構材直到到達電極墊，使得可將薄膜電容器接合於面陣列型積體電路。藉此，無須於薄膜電容器之上部形成端子陣列，或於或面陣列型積體電路的電極墊形成連接凸塊。此外，可將薄膜電容器以大致最短距離結合於面陣列型積體電路的電極墊面。其結果，可簡略化薄膜電容器與積體電路的連接構成，同時可減低薄膜電容器的佈線相關的阻抗。
於上述薄膜電容器構造，亦可前述第1片狀電極包含：第1突出部，其突出於前述接地用貫通孔內；第1開口部，其形成於與前述電源墊及前述信號墊對應的位置；接地墊用開口部，其形成於與前述接地墊對應的位置，具有在周邊形成前述第1突出部的平面形狀；另外，前述第2片狀電極包含：第2突出部，其突出於前述電源用貫通孔內；第2開口部，其形成於與前述接地墊及前述信號墊對應的位置；電源墊用開口部，其形成於與前述電源墊對應的位置，具有在周邊形成前述第2突出部的平面形狀。 　　依本構成時，在將銅膏等的導電構材填充於複數個貫通孔至電極墊之際，由於第1突出部及第2突出部使得導電構材接合於第1片狀電極及第2片狀電極的面積增加。藉此，可使導電構材與第1片狀電極及第2片狀電極的接合為更強固者，藉此導電構材與各片狀電極的接合的可靠性提升。此外，可透過各開口部形成電源用貫通孔、接地用貫通孔及信號用貫通孔。此外，能以簡易的構成透過接地墊用開口部形成第1突出部，透過電源墊用開口部形成第2突出部。
此外，於上述薄膜電容器構造，亦可前述薄膜介電體層，包含介電體開口部，該介電體開口部形成於與前述複數個電極墊對應的位置，具有比前述第1開口部及前述第2開口部的開口面積小的開口面積，前述第1絕緣膜包含形成於與前述複數個電極墊對應的位置的第1絕緣膜開口部，前述第2絕緣膜包含形成於與前述複數個電極墊對應的位置的第2絕緣膜開口部，前述電源用貫通孔由第1絕緣膜開口部、前述介電體開口部、前述電源墊用開口部及前述第2絕緣膜開口部構成，前述接地用貫通孔由第1絕緣膜開口部、前述接地墊用開口部及前述第2絕緣膜開口部構成，前述信號用貫通孔由第1絕緣膜開口部、前述介電體開口部及前述第2絕緣膜開口部構成。 　　依本構成時，可一面將第1片狀電極的一部分及第2片狀電極的一部分絕緣，一面透過各開口部形成電源用貫通孔、接地用貫通孔及信號用貫通孔。
此外，於上述薄膜電容器構造，亦可前述第1開口部、前述第2開口部及前述介電體開口部於俯視下具有正方形的形狀，前述電源墊用開口部及前述接地墊用開口部於俯視下具有十字狀的形狀。
依本構成時，可將供於形成各開口部用的遮罩的形狀簡易化，故可簡易化各開口部的形成。
此外，由本說明書所揭露的半導體裝置具備：面陣列型積體電路；薄膜電容器構造，其係上述任一者的薄膜電容器構造，貼附於前述面陣列型積體電路的電極墊面；導電材料，其被填充於前述電源用貫通孔、前述接地用貫通孔及前述信號用貫通孔，直到到達前述複數個電極墊。 　　依本構成時，可簡略化薄膜電容器與面陣列型積體電路的連接構成，同時可減低薄膜電容器的佈線相關的阻抗。
於上述半導體裝置，亦可相對於前述導電材料在與前述電極墊側相反之側，設置外部連接用的連接墊。 　　依本構成時，例如於連接墊形成焊料微凸塊，使得可建構具備薄膜電容器的面陣列型的半導體裝置，可將半導體裝置連接於外部電路。
此外，於上述半導體裝置，亦可具備中間基板，該中間基板係相對於前述薄膜電容器構造設於與前述電極墊面側相反之側的中間基板，在與前述複數個電極墊對應的位置具有複數個中間基板墊。 　　依本構成時，可在中間基板設置再佈線層從而變更面陣列型積體電路的電極墊間距。藉此，可將半導體裝置連接於與積體電路的電極間距係不同的電極間距的外部電路基板如主機板。 [對照先前技術之功效]
依本發明時，可簡略化薄膜電容器與積體電路的連接構成，同時可減低薄膜電容器的佈線相關的阻抗。
＜實施方式＞ 　　就一實施方式參照圖1至圖11進行說明。另外，圖中，相同的符號表示相同或相當部分。此外，使圖1的以箭頭Z表示的方向為上方向。另外，於圖1等的剖面圖，說明的方便上，放大顯示薄膜部分的厚度方向的尺寸。為此，剖面圖之上下方向的尺寸與實際的尺寸不同。
1.半導體裝置的構成 　　如示於圖1，半導體裝置100主要包含LSI晶片(「面陣列型積體電路」的一例)2、薄膜電容器構造50。另外，圖1係與圖7的以點劃線A-A表示的位置對應的半導體裝置100的剖面圖。
在LSI晶片2的屬接合側的面之電極墊面2S，如示於圖2，面陣列狀地形成複數個電極墊3。複數個電極墊3包含電源墊3P、接地墊3G及信號墊3S。對電源墊3P，經由薄膜電容器構造50施加高壓側的電壓如5V的電壓，對接地墊3G，分別經由薄膜電容器構造50施加低壓側的電壓如零V的電壓。此外，經由信號墊3S輸出入控制信號等。電源墊3P、接地墊3G及信號墊3S係如示於圖2，分散配置於電極墊面2S的大致整體。各電極墊3係透過保護膜8隔離。另外，說明中無需區別電源墊3P、接地墊3G及信號墊3S的情況下，簡記為「電極墊3」。於本實施方式，電極墊3的尺寸係例如約50μm平方前後，電極墊3的配置間距係例如約150μm。
此外，如示於圖1，於後述的薄膜電容器構造50的(貫通孔30G、30P、30S)，填充導電材料4如銅膏。對該導電材料4，在與電極墊3側相反之側，換言之於導電材料4的下方側，設置外部連接用的連接墊5。
2.薄膜電容器構造的構成 　　薄膜電容器構造50如示於圖1，主要包含薄膜電容器10、第1絕緣膜21及第2絕緣膜22。
薄膜電容器10包含連接於接地(低壓電位)的接地電極(「第1片狀電極」的一例)11、連接於電源(高壓電位)的電源電極(「第2片狀電極」的一例)13及形成於接地電極11與電源電極13之間的薄膜介電體層12。
接地電極11係薄膜金屬電極，如示於圖3，包含第1開口部11A與接地墊用開口部11B。第1開口部11A形成於與電源墊3P及信號墊3S對應之位置。接地墊用開口部11B形成於與接地墊3G對應之位置，具有於其周邊形成將後述的接地用貫通孔30G的一部分覆蓋的突出部11C的平面形狀。在本實施方式，如示於圖3，第1開口部11A於俯視下具有正方形的形狀，接地墊用開口部11B於俯視下具有十字狀的形狀。與接地墊用開口部11B的十字部鄰接的接地電極11的四處的突出部11C覆蓋接地用貫通孔30G的一部分，換言之與接地用貫通孔30G重疊。於此，四處的突出部11C係突出於接地用貫通孔30G內的「第1突出部」的一例。
薄膜介電體層12係如示於圖4，包含介電體開口部12A，其形成於與複數個電極墊3對應的位置，亦即與電源墊3P、接地墊3G及信號墊3S對應的位置。於本實施方式，介電體開口部12A係於俯視下具有正方形的形狀，具有比上述第1開口部11A及後述的第2開口部13A的開口面積小的開口面積。
電源電極13係薄膜金屬電極，如示於圖5，包含第2開口部13A與電源墊用開口部13B。第2開口部13A形成於與接地墊3G及信號墊3S對應的位置。電源墊用開口部13B形成於與電源墊3P對應的位置，具有在其周邊形成突出部13C的平面形狀。在本實施方式，如示於圖5，如同第1開口部11A，第2開口部13A於俯視下具有正方形的形狀，電源墊用開口部13B如同接地墊用開口部11B，於俯視下具有十字狀的形狀。與電源墊用開口部13B的十字部鄰接的電源電極13的四處的突出部13C覆蓋後述的電源用貫通孔30P的一部分，換言之，與電源用貫通孔30P重疊。於此，四處的突出部13C係突出於電源用貫通孔30P內的「第2突出部」的一例。
第1絕緣膜21將接地電極11絕緣。第1絕緣膜21包含第1絕緣膜開口部21A，其形成於與複數個電極墊3對應的位置，亦即與電源墊3P、接地墊3G及信號墊3S對應之位置(圖8參照)。另外，圖8係與圖7的以點劃線A-A表示的位置對應的剖面圖。
此外，第2絕緣膜22將電源電極13絕緣。第2絕緣膜22係如同第1絕緣膜21，包含第2絕緣膜開口部22A，其形成於與複數個電極墊3對應的位置，亦即與電源墊3P、接地墊3G及信號墊3S對應之位置(圖8參照)。
此外，薄膜電容器構造50包含複數個貫通孔(30P、30G、30S)，其等係經由薄膜電容器10，從第1絕緣膜21貫通至第2絕緣膜22，形成於與複數個電極墊3對應的位置。於複數個貫通孔(30P、30G、30S)方面包含：形成於與電源墊3P對應的位置的電源用貫通孔30P、形成於與接地墊3G對應的位置的接地用貫通孔30G、形成於與信號墊3S對應的位置的信號用貫通孔30S(參照圖6、圖7及圖8)。
詳言之，如示於圖8，電源用貫通孔30P由第1絕緣膜開口部21A、介電體開口部12A、電源墊用開口部13B及第2絕緣膜開口部22A構成。此外，接地用貫通孔30G由第1絕緣膜開口部21A、接地墊用開口部11B及第2絕緣膜開口部22A構成。此外，信號用貫通孔30S由第1絕緣膜開口部21A、介電體開口部12A及第2絕緣膜開口部22A構成。另外，構成各貫通孔(30G、30P、30S)的開口部的構成不限於上述的構成。
3.半導體裝置(薄膜電容器構造)的製造方法 　　接著，參照圖9至圖11，就半導體裝置100的製造方法的一例進行說明。另外，半導體裝置100的製造方法之中，圖9(a)至圖10(g)示出薄膜電容器構造50的製造方法。此外，圖9(c)至圖11(j)係與圖1使上下關係相反而繪示。此外，示於圖9至圖11的製程的順序係顯示一例者，非限定於此者。
在同製造方法，首先在ABF(Ajinomoto Build-Up Film)等的具有黏合性及硬化性的支撐基材31上，將未形成開口部的整面狀態的接地電極11、薄膜介電體層12及電源電極13，從下依序層積(未圖示)。此處，接地電極11及電源電極13例如由銅箔構成，薄膜介電體層12由例如STO(鈦酸鍶)膜構成。此狀態下，為了形成電源電極13的各開口部(13A、13B)，就電源電極13選擇性進行回蝕。之後，透過雷射加工或利用電漿的乾式蝕刻或利用溶劑的濕式蝕刻，形成薄膜介電體層12的介電體開口部12A。此狀態示於圖9(a)。
接著，將具有黏合性及硬化性的環氧系樹脂或聚醯亞胺系樹脂等的有機絕緣片22M載置於電源電極13上，將有機絕緣片22M熱壓接。此狀態示於圖9(b)。如示於圖9(b)，透過熱壓接使得有機絕緣片22M將介電體開口部12A及第2開口部13A填充，到達於整面狀態的接地電極11M。
接著，除去支撐基材31，將除去支撐基材31的半加工品上下反轉，在ABF等的具有黏合性及硬化性的新的支撐基材32上固定半加工品。此狀態示於圖9(c)。
接著，將整面狀態的接地電極11M選擇性回蝕而形成各開口部(11A、11B)，同時將有機絕緣片22M回蝕而形成第2絕緣膜22及第2絕緣膜開口部22A。此狀態示於圖9(d)。
接著，如示於圖10(e)，作為成為第1絕緣膜21的絕緣膜21M，將抗蝕膜等塗佈於接地電極11等之上。接著，就絕緣膜21M進行選擇性蝕刻，從而如示於圖10(f)，形成電源用貫通孔30P、接地用貫通孔30G及信號用貫通孔30S。接著，除去支撐基材32，從而完成如示於圖10(g)的薄膜電容器構造50。
接著，如示於圖10(h)，將薄膜電容器構造50接合於LSI晶片2的電極墊面2S。接合的方法方面，使用薄型、具有黏合性的DAF(Die Attach Film))材或NCF(Non Conductive Film)等的黏合構材(未圖示)進行接合。或者，亦可塗佈不必要洗淨的焊劑，利用焊劑的微黏合性進行接合。再者，第2絕緣膜22為具有臨時黏合與主黏合的功能的構材的情況下，亦可由第2絕緣膜22代替黏合構材。
此處，接地電極11與電源電極13，和LSI晶片2的電極墊面2S於大致全區維持平行，形成為，於利用刷塗器等而進行的導電膏(銅膏等)的填充，能進行以面的接觸。藉此，將薄膜電容器構造50接合於LSI晶片2的電極墊面2S之際，可增加接合面積而降低接觸電阻，進一步使接合的可靠性提升。
接著，如示於圖11(i)，將電源用貫通孔30P、接地用貫通孔30G及信號用貫通孔30S，透過作為導電材料的例如硬化性的銅膏4，利用刷塗器等進行填充，使銅膏4硬化。此情況下，各銅膏4與各電極墊3直接電性連接。
接著，如示於圖11(j)，在銅膏4上的與電源用貫通孔30P、接地用貫通孔30G及信號用貫通孔30S對應的位置，形成供於連接於中介層基板等的電路基板用的外部連接用的外部連接墊5。接著，在形成外部連接墊5之處以外，形成阻焊層等的保護膜7，使微焊球6附著於外部連接墊5。藉此，完成如示於圖1的半導體裝置100。
4.實施方式的功效 　　如上述，於本實施方式的薄膜電容器構造50設置複數個貫通孔(30G、30P、30S)，其等係從第1絕緣膜21經由薄膜電容器10貫通至第2絕緣膜22，形成於與LSI晶片2的複數個電極墊(3G、3P、3S)對應的位置。為此，將薄膜電容器構造50，換言之將薄膜電容器10接合於LSI晶片2(面陣列型積體電路)之際，於複數個貫通孔(30G、30P、30S)，例如如本實施方式，填充銅膏的導電構材4直到到達電極墊3，使得可將薄膜電容器10接合於LSI晶片2。藉此，無須於薄膜電容器10之上部形成端子陣列，或於LSI晶片2的電極墊3形成連接凸塊。此外，能以大致最短距離將薄膜電容器10結合於LSI晶片2的電極墊面2S。其結果，可簡略化薄膜電容器10與LSI晶片2(積體電路)的連接構成，同時可減低薄膜電容器10的佈線方面的阻抗。
此外，於複數個貫通孔30填充銅膏等的導電構材4直到電極墊3之際，由於接地電極11的突出部11C及電源電極13的突出部13C使得導電構材4接合於接地電極11及電源電極13的面積增加。藉此，可使導電構材4與接地電極11及電源電極13的接合成為更強固者，其結果，導電構材4與各電極(11、12)的接合的可靠性提升。 　　此情況下，第1突出部11C係伴隨十字狀的接地墊用開口部11B的形成而形成，此外，第2突出部13C係伴隨十字狀的電源墊用開口部13B的形成而形成。為此，能以簡易的方法形成第1突出部11C及第2突出部13C。
此外，第1開口部11A、第2開口部13A及介電體開口部12A係於俯視下具有正方形的形狀，電源墊用開口部13B及接地墊用開口部11B係於俯視下具有十字狀的形狀。為此，可將供於形成各開口部用的遮罩的形狀簡易化，藉此，簡易化各開口部的形成。此外，可將第1突出部11C及第2突出部13C，伴隨接地墊用開口部11B及電源墊用開口部13B的形成而同時形成。
＜其他實施方式＞ 　　本發明非限定於透過上述記述及圖式而說明的實施方式者，例如以下的實施方式亦包含於本發明的技術範圍。
(1)於上述實施方式，雖示出第1開口部11A、第2開口部13A及介電體開口部12A於俯視下具有正方形的形狀，接地墊用開口部11B及電源墊用開口部13B於俯視下具有十字狀的形狀之例，惟不限於此。例如，接地墊用開口部11B及電源墊用開口部13B亦可僅為如示於圖12的矩形狀，或者亦可為如示於圖13的形狀。此外，第1開口部11A、第2開口部13A及介電體開口部12A例如亦可為於俯視下具有圓形的形狀者。
(2)於上述實施方式，雖示出透過銅膏4構成導電材料之例，惟不限於此。導電材料例如亦可由鍍銅構成。
(3)於上述實施方式，雖示出使圖1中的下方的電極為接地電極11(第1片狀電極)，使上方的電極為電源電極13(第2片狀電極)之例，惟不限於此，亦可為其相反。亦即，可使圖1中的下方的電極為電源電極13(第2片狀電極)，使上方的電極為接地電極11(第1片狀電極)。
(4)半導體裝置100的構成非限於示於圖1者。例如，如示於圖14的半導體裝置100A，亦可為包含相對於薄膜電容器構造50設在與電極墊面2S側相反之側的中介層基板(中間基板)60的構成。於中介層基板60上，在與LSI晶片2的電源墊3P、接地墊3G及信號墊3S對應的位置，形成中間基板墊61P、中間基板墊61G及中間基板墊61S、將各中間基板墊61絕緣而分離的絕緣層62。在此構成下，例如可透過在中間基板60設置再佈線層從而變更LSI晶片2的電極墊3之間距。藉此，可使半導體裝置100A連接於與LSI晶片2的電極間距係不同的電極間距的外部電路基板如主機板。另外，於圖14等，中介層基板60內的其他構成如佈線層等的圖式係省略。 　　包含中介層基板60的構成的情況下，在LSI晶片2與中介層基板60的連接方面，可如示於圖15，將先經由銅膏4等將薄膜電容器構造50連接於LSI晶片2者，透過熱壓接連接於中介層基板60。或者，亦可如示於圖16，將先經由銅膏4等將薄膜電容器構造50連接於中介層基板60者，透過熱壓接連接於LSI晶片2。
2‧‧‧LSI晶片(積體電路)
2S‧‧‧電極墊面
3G‧‧‧接地墊(電極墊)
3P‧‧‧電源墊(電極墊)
3S‧‧‧信號墊(電極墊)
5‧‧‧外部連接墊
10‧‧‧薄膜電容器
11‧‧‧接地電極(第1片狀電極)
11A‧‧‧第1開口部
11B‧‧‧接地墊用開口部
11C‧‧‧突出部(第1突出部)
12‧‧‧薄膜介電體層
13‧‧‧電源電極
13A‧‧‧第2開口部
13B‧‧‧電源用開口部
13C‧‧‧突出部(第2突出部)
30G‧‧‧接地用貫通孔
30P‧‧‧電源用貫通孔
30S‧‧‧信號用貫通孔
50‧‧‧薄膜電容器構造
60‧‧‧中介層基板
61‧‧‧中間基板墊
100、100A‧‧‧半導體裝置
[圖1] 就實施方式相關的半導體裝置進行繪示的概略的剖面圖 　　[圖2] 就半導體裝置的電極墊面進行繪示的平面圖 　　[圖3] 薄膜電容器的接地電極的局部平面圖 　　[圖4] 薄膜電容器的薄膜介電體層的局部平面圖 　　[圖5] 薄膜電容器的電源電極的局部平面圖 　　[圖6] 薄膜電容器的局部平面圖 　　[圖7] 圖6的局部放大圖 　　[圖8] 薄膜電容器構造接合於LSI晶片的狀態下的剖面圖 　　[圖9] 就半導體裝置(薄膜電容器構造)的製造方法進行繪示的概略的局部剖面圖 　　[圖10] 就半導體裝置(薄膜電容器構造)的製造方法進行繪示的概略的局部剖面圖 　　[圖11] 就半導體裝置的製造方法進行繪示的概略的局部剖面圖 　　[圖12] 就別例的接地墊用開口部進行繪示的概略的平面圖 　　[圖13] 就別例的接地墊用開口部進行繪示的概略的平面圖 　　[圖14] 就別例的半導體裝置進行繪示的概略的的局部剖面圖 　　[圖15] 就圖14的半導體裝置的製造方法進行繪示的局部剖面圖 　　[圖16] 就圖14的半導體裝置的別的製造方法進行繪示的局部剖面圖

Claims (7)

  1. 一種薄膜電容器構造，接合於面陣列狀地配置複數個電極墊於電極墊面的面陣列型積體電路的前述電極墊面，前述複數個電極墊包含電源墊、接地墊及信號墊， 　　該薄膜電容器構造具備： 　　薄膜電容器，其包含第1片狀電極、第2片狀電極及形成於前述第1片狀電極與前述第2片狀電極之間的薄膜介電體層； 　　第1絕緣膜，其將前述第1片狀電極絕緣； 　　第2絕緣膜，其將前述第2片狀電極絕緣； 　　複數個貫通孔，其係從前述第1絕緣膜經由前述薄膜電容器貫通至前述第2絕緣膜且形成於與前述複數個電極墊對應之位置的複數個貫通孔，包含形成於與前述電源墊對應的位置的電源用貫通孔、形成於與前述接地墊對應的位置的接地用貫通孔及形成於與前述信號墊對應的位置的信號用貫通孔。
  2. 如請求項1的薄膜電容器構造，其中， 　　前述第1片狀電極包含： 　　第1突出部，其突出於前述接地用貫通孔內； 　　第1開口部，其形成於與前述電源墊及前述信號墊對應的位置； 　　接地墊用開口部，其形成於與前述接地墊對應的位置，具有在周邊形成前述第1突出部的平面形狀； 　　前述第2片狀電極包含： 　　第2突出部，其突出於前述電源用貫通孔內； 　　第2開口部，其形成於與前述接地墊及前述信號墊對應的位置； 　　電源墊用開口部，其形成於與前述電源墊對應的位置，具有在周邊形成前述第2突出部的平面形狀。
  3. 如請求項2的薄膜電容器構造，其中， 　　前述薄膜介電體層包含介電體開口部，該介電體開口部形成於與前述複數個電極墊對應的位置，具有比前述第1開口部及前述第2開口部的開口面積小的開口面積， 　　前述第1絕緣膜包含形成於與前述複數個電極墊對應的位置的第1絕緣膜開口部， 　　前述第2絕緣膜包含形成於與前述複數個電極墊對應的位置的第2絕緣膜開口部， 　　前述電源用貫通孔由第1絕緣膜開口部、前述介電體開口部、前述電源墊用開口部及前述第2絕緣膜開口部構成， 　　前述接地用貫通孔由第1絕緣膜開口部、前述接地墊用開口部及前述第2絕緣膜開口部構成， 　　前述信號用貫通孔由第1絕緣膜開口部、前述介電體開口部及前述第2絕緣膜開口部構成。
  4. 如請求項3的薄膜電容器構造，其中， 　　前述第1開口部、前述第2開口部及前述介電體開口部於俯視下具有正方形的形狀， 　　前述電源墊用開口部及前述接地墊用開口部於俯視下具有十字狀的形狀。
  5. 一種半導體裝置，具備： 　　面陣列型積體電路； 　　薄膜電容器構造，其係如請求項1至請求項4中任一項的薄膜電容器構造，接合於前述面陣列型積體電路的電極墊面； 　　導電材料，其被填充於前述電源用貫通孔、前述接地用貫通孔及前述信號用貫通孔，直到到達前述複數個電極墊。
  6. 如請求項5的半導體裝置，其中，相對於前述導電材料在與前述電極墊側相反之側，設置外部連接用的連接墊。
  7. 如請求項5的半導體裝置，其具備中間基板，該中間基板係相對於前述薄膜電容器構造設於與前述電極墊面側相反之側的中間基板，在與前述複數個電極墊對應的位置具有複數個中間基板墊。
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