TWI231020B - Substrate with embedded passive components and method for fabricating the same - Google Patents

Abstract

A substrate with embedded passive components and a method for fabricating the substrate are proposed. At least a first unit circuit board is formed with circuit layers on upper and lower surfaces thereof. Conductive metal layers with a capacitor film and a resistor film separated from the first united circuit board by an insulating layer are mounted on the circuit layers of the first unit circuit board. After patterning the conductive metal layer and resistor film formed thereon, at least an opening is formed to penetrate the first unit circuit board. At least a second unit circuit board is formed with circuit layers separated from one to another by an insulating layer and electrically connected to each other via a plurality of conductive vias and blind vias formed in the second unit circuit board. The first and second unit circuit boards are integrated to form at least an indentation via the opening of the first unit circuit board which was covered by the second unit circuit board. A plurality of PTH was formed to penetrate the unit circuit boards in order to electrically connect at least one of the circuit layers formed on the surface of the capacitor film and the resistor film.

Description

1231020 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package substrate and a manufacturing method thereof, and more particularly to a passive component and two or more electronic components embedded in a layered circuit board structure. Semiconductor package substrate and manufacturing method thereof. -Jing [Previous Technology] With the vigorous development of the electronics industry, electronic products have gradually entered the direction of high-performance and high-performance research and development. In order to meet the needs of semiconductor package high integration and miniaturization, Mini printed circuit board (pr inted,

(Circuit Board) has gradually evolved from a single-layer board to a multi-layer board. In a limited space, the use of the Interlayer Connection technology to expand the available circuit area of the printed circuit board to match the high electron density. Integrated Circuit requirements. At the same time, it is also necessary to integrate passive components such as resistors, capacitors, and inductors on the semiconductor components to relatively improve or stabilize the electrical functions of electronic products. . As shown in Figure 1, most of the passive components 12 are placed on the surface of the substrate i. The substrate can be a general printed circuit board or a packaging substrate of a semiconductor wafer. However, in order to avoid these passive components 丨 2 hindering the semiconductor wafer 丨 丨Electrically connected to most solder pads, the passive elements 12 are traditionally placed at the corner end position of the substrate i or the additional layout area of the substrate of the semiconductor wafer ji connection area ^. However, limiting the placement of passive components 12 and 2 will reduce the flexibility of the surface circuit layout (r 〇 u t a b 丨 1 丨 t y) of substrate 1.

17098. ptd Page 8 1231020 V. Explanation of the invention (2) The fresh junction position needs to be considered, which leads to a limitation of the tower and the driver, which is not conducive to the height of the semiconductor device: the number of components 1 2 is affected by the number of components 12 For semiconductor packages ^ |, it is increased by ground, such as the conventional method of using the substrate 矣 矣 __ to meet the requirements of the conductor chip 11 and a large number of passive components 丨 2 \ must simultaneously accommodate most of the half thousand 1 2 ' The assembly company's survival is not in line with the development of thin, light, and short semiconductor packages. The size of the package is large. As shown in Figure 2, based on the above problems, it is possible to conceive of a semiconducting semiconductor element integrated on the substrate 2. ', X Xi counts the area between the chip 21 and the soldering area. However, with the increase in the number of output / input connections in the early area, the number of bonding wires 23 has also increased with the increase in the number of bonding wires 23. The height (about 0.8 mm) is higher than the height of the semiconductor wafer 21 ( (Approximately H: meters) 'If you want to avoid the short circuit caused by the welding wire 23 touching the passive element 22, the welding wire 23 needs to be pulled and traverses directly above the passive element 22, which will increase the difficulty of connection and make the wire arc (The degree of wlre loopm is increased. Moreover, the welding wire 23 has a weight. If the welding wire 23 that is connected to the high wire lacks support, it is easy to cause a short circuit due to its own gravity collapse% and touching the passive component. The welding wire 2 3 itself is made of gold and aluminum. Making 'increasing the arc length of the wire will significantly increase the cost of the welding wire 23. Furthermore, the passive component 22 is fixed to the passive component 22 by a solder paste using a conventional surface bonding technology (SMT). After the soldering position of the substrate 2 is preset, when the semiconductor device colloidal packaging process is performed, the molten packaging resin 24 is injected under a high temperature environment. At this time, the operating temperature (175 ° C) and the passive component 22 are fixedly used for soldering. Adhesive melting temperature (1 8 3 ° C ), The soldering agent is in a semi-melted and softened state, which may easily cause the passive components 22 to suffer from the molten encapsulation resin 24 after injection.

1231020 V. Description of the invention (3) Mold pre-flow (Mo 1 d f 1 0 w) stress impact, set the welding position, reduce the conductive quality and even; the moving element 22 deviates from this. In addition, in today's electronic products require lighter, J. Under the trend of sex, relatively, the placement of beans inside f, small and multi-functional, and high-electricity follow the requirements of thin, thin, and short, so how to package the unit is bound to increase the electrical functions of electronic products, but not $ = in the substrate, In order to improve the layout of the circuit and the overall package of the semiconductor package, θ = a problem to be solved for the conductive package substrate. The increase of 1 degree is really urgent at the present time. [Summary of the Invention] The conventional technology described above provides a built-in passive component guide. The main purpose is to use Ding Xingan ’s guide basket packaging substrate and its manufacturing method. The number of passive components in the circuit board wiring device is increased, and the substrate is increased to be sealed;:; = semiconducting conductor of the passive component? The thickness of the skirt is to achieve the goal of thin, light and short semiconductor devices. The body package 1: ί ::: is to provide a semi-conductive film with passive components embedded in it. This method prevents the passive components from being exposed to high temperatures and mold currents. The "Niuyin Road" also shortens the solitary length of the bonding wire, saves soldering and stripping of conductors, and other purposes. The semi-passive package substrate for passive components in the present invention and its manufacturing method include: 卞

1231020 V. Description of the invention (4) Provide a plurality of electrical and metal layers and an interlayer on the two sides of the single circuit board; pattern the electrical element and its electrodes, and open the surface; at the same time, form an insulation layer on the inside After the plural number, the first XJTJ is combined with the first XJTJ, and the shape connection is connected to the film-type moving element by the method, which also causes the short-circuit moving element cost. Circuit boards, openings, and table circuit board openings are formed in the majority of the openings. The number of packaged capacitor elements mounted on the board obtained by the present invention is placed on the substrate table to avoid passive phenomena, which may cause short circuits or cause them. The second side is provided with at least a element circuit board in a shape surface; then, at least one σ — road layer is respectively pressed with a load _ load * 7 ° as early as electrical insulation with a sound insulation right one of the right "valley film" The conductive film and the conductive full V electrical metal on its surface are on the first unit circuit board; = to form a resistance, and in at least one first frame: to form at least -through cm: the second unit circuit board is connected with the eye hole to Electrically connect the circuit layers; one handle rabbit, 1. Enclosed the circuit board 'supplied' by the Yiyiwu circuit board. The electric mine vias (PTT), power supply valley film and resistance film One of the circuit layers on the surface. = A semiconductor package substrate with passive components embedded therein. F At least one film-shaped resistance element and at least buried in the substrate, so as to improve the internal and electrical performance of the semiconductor. ; Know-how needs to be passive In order to increase the flexibility of the circuit layout of the substrate, and the components are skewed due to the effects of temperature and mold flow, even the welding difficulty is reduced. The first unit circuit board and the second unit electric unit circuit board can seal the first unit circuit board into a multilayer circuit board with a recessed portion of a passive element such as a resistive film and a capacitive film embedded in it, such as a semiconductor crystal.

1231020 V. Description of the invention (5) ---- Borrow :: m nanot is electrically connected to the recess of the multilayer circuit board, thin and short 4 = the overall thickness of the package, to achieve the lightness and shortness of the semiconductor package at the same time Purpose of high electricity. No, ::? The present invention will be further described in detail by way of examples, but the present invention is not limited by the examples. In addition, the drawings of the present invention are only briefly described in the middle & ® $ according to the size of the Bayesian, that is, the actual dimensions of each layer of the multi-layer substrate structure are not reflected. [Implementation method] π Refer to FIGS. 3A to 3I, which are schematic diagrams of a method for manufacturing a semi-V body package substrate with embedded passive components according to the present invention. As shown in FIG. 3A, firstly, at least one first unit circuit board and two it circuit boards are provided. The first unit circuit board 3 & is selected from the group consisting of a Copper Coated Laminate (CCL), a back Resin Coated Copper (RCC), or fr-4 resin, FR-5 tree month, Epoxy, silicon, Po 1 yesters, glass fiber and other insulation The copper foil resin layer, such as Copper Foil, is plated on the surface of the flexible material. In this embodiment, a double-layer copper metallurgy substrate is used as the material of the unit circuit board, that is, an insulating resin layer 30 The upper surface 30 a and the lower surface 30 b are each attached with a first conductive metal layer 31 and a second conductive metal layer 32 such as a copper foil layer. As shown in FIG. 3B, the first conductive metal layer 31 and the first conductive metal layer 32 of the first unit circuit board 3a are applied with a development, a surname, etc. to form a circuit. A conventional process is used to form the first circuit layer 31a of the patterned circuit (Pattern Circuit).

17098. ptd Page 12 1231020 V. Description of the invention (6) The circuit layer 32a ’constitutes a double-layer electrical circuit.

The circuit area can be used to form the circuit layer 3U 3 1, ^ 3aAV ^ A7; 7 circuit layer circuit board as described below, and related circuit patterns ^ There are many well-known technology of W. However, it is a private technology in the industry, which is not a technical feature of this case, so it is not. As shown in Figure 3C, in the first unit, the first lightning path layer 31a on the surface of the scm two and the electric tower 3a is combined—the three conductive golds carrying the capacitor film 41 are placed in the first unit. The two circuit layers 32a are separated by an insulating layer 40 to compress them-^ Electric = conductive] :! :! 4: The capacitor film 41 is selected from a dielectric layer with a large dielectric constant: ... 丨 an electrical layer, which is made of, for example, a South molecular material, a ceramic material, a ceramic filled South molecule and the like, and the material may be, for example, titanium Barium-titanate, Lead-zirconate-titanate, AmOrph〇us hydrogenated carbon 'or its powder is dispersed in a binder, such as resin , Glass powder, etc., can also be formed by sputtering, printing or roller coating. The material of the insulating layer 40 may be an insulating organic material or a ceramic material, such as epoxy resin, poiyimide, bismaleimide / triazine ( Bismaleimide triazine —based resin, or composite material of glass fiber (Glass fiber), etc. Of course, the insulating layer 40 is not limited to being formed of only a single organic material, but can also be formed by stacking different insulating material layers. . The resistive film 42 includes a thick film (Thick f i lm) and a thin film (Thin f i lm) resistive material. The thick film resistive material is, for example, silver powder or carbon particles.

17098. ptd page 13 1231020 V. Description of the invention (7) Part i cl e) is dispersed in resin, and ruthenium oxide (ru〇2) and glass powder are dispersed in a binder (Binder) and then cured; The thin film resistance materials are, for example, nickel-chromium (N i-C r), nickel-phosphorus (N i-P) ', nickel-tin (ni — s η), chromium-aluminum (Cr-Al), and titanium nitride (TaN) alloys. Etc., which can be formed by methods such as sputtering, electroplating, or electroless plating. As shown in FIG. 3D, 'the resistive film 42 and the fourth conductive metal layer 34 carrying the surface thereof are patterned to form a fourth circuit layer 34a and a resistive electrode 34b to complete the embedded resistive element 4 in the substrate structure. 2 a, and at least one through-surface opening 50 is formed in the first unit circuit board 3 a, and is used as a storage space for subsequent electronic components. As shown in FIG. 3E, at least one conductive hole 43 is formed in at least one second unit circuit board at the same time, and the fifth circuit layer 35a and the fifth circuit layer 35a formed on the surface of the second unit circuit board 3b are electrically connected. The sixth circuit layer 36a. Of course, the second unit circuit board can also be used as a multi-layer circuit board according to actual design requirements. As shown in FIG. 3F, a seventh circuit layer 37a and an eighth circuit are formed on the fifth circuit layer 3 5a and the sixth circuit layer 3 6 a of the second unit circuit board 3b by an insulation layer 4 respectively. The circuit layer 38a, and the seventh circuit layer 37a and the eighth circuit layer 38a are electrically connected to the fifth circuit layer 35a and the first through a conductive via (B1 ind) 4 4 formed in the insulating layer 40. Six circuit layers 36a. As shown in FIG. 3G, the first unit circuit board 3a and the second unit circuit board 3b are combined, so that one side of the opening of the first unit circuit board 50 is formed by the second unit circuit board 3b. It is closed to form a receiving recess 50a, and an insulation layer 40 is formed on the eighth circuit layer 38a of the second unit circuit board 3b.

ΙϋΗΙΙ IH Page 14 17098.ptd 1231020 *. 5. Description of the invention (8) A ninth conductive metal layer 39 is formed. Of course, the 50th of the first unit thunder cup can also be formed in the second unit circuit board 3b, and the same can be achieved when the first unit circuit board 3a and the second unit circuit board with an opening are joined. The opening side of the second unit circuit board 3b is closed by the first unit circuit board 3a to form a receiving space. The recessed portion 50a can be used for subsequent placement and electrical connection of electronic components such as semiconductor wafers to the substrate, thereby effectively reducing the overall thickness of the semiconductor device. As shown in FIG. 3H, a plurality of electrical through-holes (PTH) 45 penetrating through the surface of the package substrate are formed at predetermined positions on the substrate. These electrical through-holes 45 are electrically connectable to the capacitor film 41 and The circuit layer on at least one surface of the resistance film 42. The plated through-holes 4 and 5 can be formed mechanically or by laser drilling (D ri 1 1 ing) to form the through-holes 4 5 a, and the outer side of the package substrate and the surface of the through-holes 45 a can be formed as nickel plating or plating. A metal conductive layer 45b such as a copper layer is filled with a filling material 45c. For example, an insulating material such as epoxy (Epoxy) or a conductive material such as Solder Paste fills the through hole 45a to form a plated through hole 45. As shown in FIG. 31, the ninth conductive metal layer 39 and the third conductive metal layer 33 on the surface of the substrate are patterned to form a ninth circuit layer 39a and a third circuit layer 33a. Cooperate with the parallel plate 33b of one of the at least one capacitive element, and cooperate with the other parallel plate 3 1 b of the first patterned first circuit layer 31 a to complete the embedding of the capacitive element 4 1 a in the package substrate 100. The ninth circuit layer 39 a can be electrically connected to the circuit layer inside the package substrate through the blind hole 44. The substrate 100 can be applied to a flip-chip (F 1 i p Ch i p) package substrate, or a general wire bonding package substrate.

17〇98.Ptd Page 15 1231020 V. Description of the invention (9) The package substrate 100 formed by the above-mentioned method for manufacturing a semiconductor package substrate for passive components in the present invention mainly includes: a first unit circuit Board 3a and second unit circuit board 3b, and the first unit circuit board 3a has at least one opening 50 through the surface, and the second unit circuit board 3b closes the opening 50 of the first unit circuit board 3a On one side, 俾 may be formed with at least one receiving recess 5a; a plurality of patterned circuit layers 31a, 32a, 33a, 34a, 35a, 36a, 37a, 38a, 39a are provided with an insulating layer 40 spaced apart to be disposed on the stack Inside the second unit circuit board; at least one capacitive film 41 and at least one resistive film 42 are formed in the first unit circuit board 3a; most of the power-supplyable second unit circuit board 3b is a conductive blind hole 44 in the circuit layer; and A plurality of f1 plated through holes (PTH) penetrating through the package substrate 100 can be electrically connected to at least one of the circuit fields on the surface of the read capacitor film 41 and the resistance film 42. The first foil substrate, Multiple circuits of conductive gold such as Shi Xi, layer of copper foil, etc. This layer is a layer of 0 0 series, which can be electrically conductive, a single adhesive, polycylindrical tree, and a layer of road. The layering is composed of sexually insulated blind element circuit board steel foil, resin, and glass layer. To form multilayer circuits 31a, 32a, copper layers, machine materials, edge materials, holes 4 4 series 3 a or the second unit circuit board 3 b, may be selected from copper in FR-4 resin, FR-5 resin, ring The surface of an insulating material such as oxygen glass fiber is plated with copper foil, and the surface is patterned with a copper foil on the surface, a double-layer circuit board, or a stacked board. 3 3a, 3 4a, 3 5a, 3 6a, 37a, 38a, 39a are formed on the insulating layer 40, and the insulating fiber reinforced organic material or particles reinforce the organic structure. Formed in the insulating layer 40, which can be

Page 16 1231020 V. Description of the invention (10) Holes or laser drilling are formed, and at least one conductive metal layer is formed on the insulating layer 40 by electroplating, electroless plating or sputtering, and the The conductive metal layer may cover the conductive blind hole 44 in whole or in part, and the conductive blind layer 44 and the conductive hole 43 are used to electrically connect the circuit layer on the rain side of the insulating layer. The capacitor film 41 is selected from a high-dielectric layer having a large dielectric constant, and is made of a polymer material such as a polymer material, a ceramic material, a ceramic powder, and the like. Generally, the dielectric constant is greater than 5; Applicable. Of course, the higher the dielectric constant value, the better. The material can be, for example, barium titanate, lead titanate titanate, amorphous hydrogenated carbon 'or its powder dispersed in a binder such as resin, glass powder, etc. Can be formed by sputtering, printing or roller spin coating. In addition, the required capacitance value of the semiconductor package substrate can be based on the material of the capacitor film 41 used and the parallel plate 3 1 b, 3 3 b sandwiched between the capacitor film 41 and the capacitor element 41. a size plus decision. The resistive film 42 includes thick film (Thick fi lm) and thin film (Thin fi 1 m) resistive passive elements, and the thick film resistive material is such as silver powder or carbon particles dispersed in resin, and ruthenium oxide and glass powder are dispersed in A bonding agent is formed by coating and curing. In contrast, the thin film resistance materials such as nickel chromium, nickel plate: nickel tin, chromium tin, and titanium nitride alloy are formed by sputtering, electroplating, or electroless recording. The choice of using thick film resistors or thin film resistors is determined by the manufacturing cost of the multilayer circuit board and the passive components: lightning accuracy. In addition, the egg of the resistance value required for the semiconductor package substrate is small, and can be determined according to the material of the electrical limiting film 42 and the size of the resistance element 42a formed between the resistance film "upper electrode 34b." Through the inner or passive aspects of the present invention, Component semiconductor package substrate manufacturer

1231020 V. The parts obtained by the invention description method can be embedded in the quantity and electrical properties to avoid the phenomenon of causing a short circuit and then 'fine' and make the (11) substrate, which is the substrate, functions, and synchronous components reduced It is also possible to combine the two units of electricity to at least increase the temperature and connection difficulty when lifting, and shorten the side of the first single circuit board to form a multilayer connection with a recess embedded in the electricity to the body thickness surface to the element. The short semi-simultaneous resistance system uv port can be sealed early and can only be closed. Decoration, few pieces of conductors, high current film, and circuit should be closed for the implementation of any The package of electric pattern capacitors needs to be used in the first and second examples of the board. The application should be only the film in the whole part of the recessed electrical parts to open the X3V. Early X3X3. The electrical and circuit design can also shape the circuit board. The circuit board accommodates the application of a film-like semiconductor substrate wire plate, which does not depart from the disclosure, and avoids the line. Neuron circuit to close the barrier film and the multilayer circuit board, the number of layers to achieve the barrier film to be distributed in the opening between the tool and the opening. The points and functions of the invention are patented. The resistance elements and the passive circuit layout in the device are flexible and deviated. The direct length of the solder-free wire is covered by the joint plate and the capacitor film of the first unit. Concavity of the circuit board The nature of the semiconductor encapsulating at least one element, and even touches the conductor crystal part of the moving element of the circuit board of the welding-saving unit, and the number of light-weight capacitors is short. The circuit board, the opening, and the watch piece are represented by a thin and short capacitor film. In fact, the position is based on reality. In the first circuit board, when the same board is used, the circuit board is implemented. The scope of the invention and The side of the second unit circuit of the second unit electrical port of the laminated second unit electrical port on the opposite substrate is covered by the above-mentioned effect of the first unit, and is not completed by the spirit of opening. Concrete, limited, and technically effective

17098.ptd Page 18 1231020 Brief description of the drawings [Simplified description of the drawings]: Figure 1 shows the unintended layout of the passive components on the extra layout area of the substrate outside the semiconductor wafer mounting area. 9 Figure 2 For the sake of acquaintance, a schematic cross-sectional view of integrating a passive component between a semiconductor wafer and a soldering area 9 and FIGS. 3A to 3I are schematic views of a method for manufacturing a semiconductor package substrate with a passive component embedded in the present invention. , 21 Semiconductor wafer 12, 22 Passive element 23 Bonding wire 24 Packaging resin 3a First unit circuit board 3b First unit circuit board 30 Insulating resin layer 30a Upper surface 30b Lower surface 31 First conductive metal layer 32 Second conductive metal layer 33 second conductive metal layer 34 fourth conductive metal layer 39 ninth conductive metal layer 31a first circuit layer 32a second circuit layer 3 3a second circuit layer 34a fourth circuit layer 35a fifth circuit layer 36a sixth Path layer 37a of the seventh circuit layer 3 8a eighth circuit layer 3 9 s, 34b resistor electrically ninth circuit layers 31b, 33b parallel to the plate 40 insulating layer 41, the capacitance film 42 resistive film 41a is electrically 42a electrically 43 conductive hole resistor element receiving member

17098.ptd p. 19 1231020

17098.ptd Page 20

Claims (1)

1231020 6. Scope of patent application 1. Two types of embedded passive components q conductors include: clothing method, bag, supply, and less-the first unit circuit board, and the other is to press-fit a conductive gold carrying a capacitor film Layer, the circuit consists of the insulating layer and the unit circuit board and a borrow layer; conductive gold with a resistive film patterned the first unit circuit board metal layer; the resistance pan and its surface conduction provided at least one second unit Circuit board, a plurality of stacked circuit layers, electrically connected to each circuit layer by forming inside J 5 f isolation edge holes and blind holes, one of the youngest of the conductive board and the second unit circuit board An opening of the circuit board; and / or at least one circuit board penetrating through the first unit circuit board and electrically connected to the first unit circuit board, so as to form at least one recess. It is closed by the early 7 ^ circuit board. 2. If the semiconductor package of item 丨 of the patent application scope is combined with the first unit circuit board and the first anti-air method, the conductive metal layer on the surface of the capacitor film is patterned. To carry out. X formed into the capacitive element level 3 · If the semiconductor in the second patent application scope is sealed in the parallel plate forming the capacitive element, y 1 is used as a method of "plating through-holes, which can be connected to the power supply through the film of the substrate At least-the circuit on the surface is connected to the capacitor film and the resistor 17098. ptd page 21 1231020 VI. Application scope of patent 4. For the method of manufacturing a semiconductor package substrate according to item 3 of the patent application, wherein the conductive metal layer on the surface of the patterned resistive film can be formed as an electrode of a resistive element. 5. If the method for manufacturing a semiconductor package substrate according to item 4 of the patent application is completed, after the conductive metal layer on the surface of the patterned resistive film is completed, at least one insulating layer and a conductive blind hole may be formed. The conductive blind hole may be connected to the resistive element. The electrodes are conducting. 6. The method for manufacturing a semiconductor package substrate according to item 1 of the application, wherein the unit circuit board is any one of a double-layer circuit board and a multilayer circuit board. 7. The method for manufacturing a semiconductor package substrate according to item 1 of the application, wherein the resistive film is any of a thick film and a thin film resistive material. 8. The method for manufacturing a semiconductor package substrate according to item 7 of the patent application, wherein the thick film resistor material is silver powder (S i 1 ver ρ 〇wder), and carbon particles (C arb ο npartic 1 e) are dispersed in the resin. And ruthenium oxide (R u 0 2) and glass powder are dispersed in a binder (B inder) and coated with a solid dagger. 9. The method for manufacturing a semiconductor package substrate according to item 7 of the application, wherein the thin film resistor material is nickel chromium (N i-C r), nickel phosphorus (N i-P), nickel tin (Ni-Sn) , Cr-Al, and titanium nitride (TaN) alloys. 10. The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the capacitor film is made of a polymer material, a ceramic material, and a ceramic powder. 17098. ptd Page 22 12 1231020 6. Scope of patent application Composed of a mixture of filled polymers and their analogs. 11 · In the method of manufacturing a semiconductor package substrate according to item 丨 of the application, the electric valley film system is barium titanate, lead-zirconate-titanate, and amorphous hydrogenated carbon. ), And its powder is dispersed in the binder (B inder). A semiconductor package substrate with embedded passive components includes at least: ^ — at least a first unit circuit board and a second unit circuit board, and at least one through electric squat is formed in any of the two unit circuit boards ^ ^ 'Make one side of the opening of the circuit board of this unit be closed by another special circuit to form at least one recess; $ several layers of patterned conductive metal layer to form a circuit layer, spaced apart from each other to stack on each unit A circuit board; the first patterned resistive film and at least one capacitor film are used to form a unit circuit board; and a plurality of plated vias are formed in the substrate for 13 related patterns. The conductive metal layer, the resistive film, and the capacitive film. The pattern ^ patent range of the semiconductor package substrate, wherein the surface of the resistive film has a patterned conductive metal layer, which is an electrode of the element. 1 4 Scholars, • Capacitors; semiconductor package substrates in the 12th area of the patent, where the I surface of the part has a patterned conductive metal layer, which can be a capacitor traveling board. 1 5 Such as ΦShi Zhi * • T is called the semiconductor package substrate of the 13th item of the patent, in which, any of its zirconium acid is not insulated from the board element. 17098. ptd Page 23 1231020 6. Scope of patent application The surface of the conductive metal layer patterned on the surface of the resist film can form at least an insulating layer and a conductive blind hole, and the conductive blind hole can be connected to the electrode of the resistive element. 16. The semiconductor package substrate according to item 14 of the scope of patent application, wherein at least one insulating layer and a conductive blind hole may be formed on the surface of the conductive metal layer patterned on the surface of the capacitor film, and the conductive blind hole may be connected to the capacitor element. The parallel plates are conducting. 1 7. The semiconductor package substrate according to item 12 of the patent application scope, wherein at least one conductive metal layer can be added on the surface of the substrate. 1 8. If the semiconductor package substrate according to item 12 of the patent application scope, wherein the unit circuit board is any one of a double-layer circuit board and a multilayer circuit board 0 1 9; if the patent application scope is 12 or 1 The semiconductor package substrate of 3 items, wherein the resistive film is any one of a thick film (Thick fi lm) and a thin film (Thin fi lm) resistive material. 20. The semiconductor package substrate according to item 19 of the scope of patent application, wherein the thick film resistor material is silver powder (S i 1 ver ρ ωwder), carbon particles (Carbon particles) dispersed in the resin, and ruthenium oxide (R u 0 2) and glass powder are dispersed in a binder (B inder), and are formed by coating and curing. 2 1. The semiconductor package substrate according to item 19 of the scope of patent application, wherein the thin film resistor material is nickel-chromium (Ni-Cr), nickel-phosphorus (Ni-P), nickel-tin (Ni-Sn), chromium-aluminum (Cr-Al), and any group of titanium nitride (TaN) alloys. 17098. ptd Page 24 1231020 VI. Patent application scope 2 2 · If the patent application scope is ½ or ½ of the item 4, the capacitor film is made of polymer material and ceramic bismuth 2 substrate, which is filled with a knife and It consists of a mixture of analogs. 2 3 · If the scope of the patent application is complicated, the 12 type 1 heart sounds are all > " * Brother 1 grade 1 4 items + conductor package substrate, where the capacitor film is Barium-titanate, titanium Any of lead-zirconate-titanate, amorphous hydrogenated carbon, and powders thereof are dispersed in a binder. 17098.ptd Page 25