TW560230B - Core substrate with embedded resistors and method for fabricating the same - Google Patents

Abstract

A core substrate with embedded resistors and a method for fabricating the core substrate are provided. An insulating core is formed with at least a cavity or opening thereon for being filled with resistive materials. At least a surface of the insulating core is covered with patterned conductive traces which are partly used as electrodes of resistors to selectively electrically connect the resistive materials within the cavity or opening, so as to fabricate a core substrate with embedded the resistors. Moreover, at least a surface of the core substrate can be formed with a build-up structure thereon to form a multi-layer circuit board with embedded resistors.

Description

560230 V. Description of the invention α) [Technical field to which the invention belongs] The present invention relates to a core board with integrated resistance elements and a manufacturing method thereof, particularly an opening or groove formed in an insulating core board to embed a resistor The modular structure of the material and the manufacturing method of the circuit board using the core board with integrated resistance elements. [Previous technology] Due to the progress of semiconductor manufacturing processes and the continuous improvement of circuit functions on semiconductor wafers, the development of semiconductor devices has become highly integrated. Take the ball grid array (BG A) semiconductor device as an example. Array-type solder balls (Solder Bal 1) implanted on the bottom surface of the substrate to provide a structure for electrically connecting semiconductor wafers and external devices such as printed circuit boards (PCBs), compared to traditional lead frames In a semiconductor device, the ball grid array type semiconductor device can be provided with more output / input connection terminals in the same unit area to accommodate more electronic circuits and semiconductor wafers. However, the integration of semiconductor devices has increased the number of pins in the package structure. As the number of pins increases, the noise also increases. Therefore, in order to eliminate noise, it is generally added to the semiconductor package structure. Passive components, such as resistive, capacitive, and inductive components, eliminate noise and stabilize the circuit so that the packaged semiconductor chip has specific current characteristics. In general, the conventional technology is to place the passive components on a substrate on an unnecessary layout area not occupied by a semiconductor wafer. However, because this integration method requires a larger-sized substrate to implement, it will make the overall package

17173.ptd Page 7 560230 V. Description of the invention (2) The size is large, and the passive components are respectively connected to the substrate, which increases the complexity of wiring and manufacturing. 'Refer to Figure 1 〇' Most passive components 12 are placed on the surface of the substrate 1. The substrate 1 can be a package substrate for a general printed circuit board or a semiconductor wafer. However, to prevent these passive components from obstructing the semiconductor wafer 2丨 丨 Electrical connection with most of the bonding pads ^ (Bonding fingers), traditionally, these passive elements 12 are mostly placed at the corners of the substrate 丨 or the semiconductor wafer . • Limit the flexibility of the passive component i 2 installation line layout (Routability); to the limit, "the development of highly integrated semiconductor devices id :? The number of passive components 12 layout with the high performance of semiconductor packages" to: increase the ground For example, if a conventional method is adopted, the requirements of b and the semiconductor wafer 11 and a large number of surfaces must simultaneously accommodate the majority, and it does not meet the semiconductor package F_2 ', which forces the complexity of the package to increase the volume of the process. The short development trend has also increased :: Legacy? Sub-products are oriented towards high functionality and trends, and the stacking of circuit boards is characterized by high-density development. Mind technology = especially necessary, with thin thickness, The number of layers and thus the development of passive 2 ::: to reduce the space requirements of the circuit board, "multi-layer lightning circuit board, the component stack on the multilayer circuit board: these passive and integrated two kinds Membrane-like passive components are in a multi-core. Several different ways, as shown in Figure η; when the circuit board is integrated and embedded in the multi-layer circuit board 2, the electrical steep element 20a is resistive. Element 2 0 ί

560230 V. Description of the invention (3) Connected on a conductive metal layer 21, the film-shaped resistance element 20a is composed of a thick film and a thin film resistance material, and the thick film resistance material For example, silver powder (S i 1 ver ρ 〇wder) or carbon particles (carb ο η partic 1 e) are dispersed in the resin, and ruthenium oxide (R u 〇 2) and glass powder are dispersed in a binder (B inder). It is formed by coating and curing. The thin-film resistance materials are such as Ni-Cr, Ni-P, Ni-Sn, Cr-A1, and Ni (N). TaN) alloy and the like, which can be formed by means of Sputtering, Electroplating or Electroless plating, etc., and patterning the resistive film and the conductive metal layer 21 on the surface of the resistive film The patterned conductive metal layer includes a plurality of circuit areas as the resistance electrodes 21a, and a resistance element is embedded between the stacked layers of the multilayer circuit board structure. Many materials and methods for forming passive components such as resistors in the laminated structure of the circuit board have attracted much attention. The key point is how to embed such passive components in the circuit board. Relevant patent technologies developed in this field are, for example, U.S. Patent Nos. 3, 8 5 7, 6 8 3, 5, 2 4 3, 3 2 0 and 5, 683, 92 8 etc., which are mostly manufactured in multilayer circuit boards. Before forming a new stack, a resistive passive element is formed on a surface of an organic insulating layer by means of printing and / or photoresist-etching. However, these four methods are easy to achieve high electrical accuracy due to the rough and uneven surface of the insulating layer at the bottom of the passive passive component, or because the insulating layer is too smooth, which weakens the adhesion between the patterned circuit layer and the insulating layer. It is not possible to achieve a better reliability circuit board. In addition, the integration of this passive component will make the overall structure of the substrate and its required manufacturing process more complex.

17173. ptd page 9 560230 5. Description of the invention (4) Miscellaneousness is not cost-effective. In addition, although the placement of film-shaped passive components between the layers of the multilayer circuit board can avoid the problem of the layout limitations of the conventional circuit board surface, the process is tedious and complicated. At the same time, because the passive components are placed between the layers of the circuit board, When different electrical characteristics such as resistance value are required, the multi-layer circuit board must be redesigned and stacked, which results in a significant increase in manufacturing costs, and also causes troubles in material management and increases in material inventory costs. Therefore, under the current trend of electronic products requiring thinness, thinness, short size, multifunction, and high electrical properties, how to provide an effective number of passive components in a semiconductor packaging unit to enhance the electrical functions of the electronic product without affecting the semiconductor packaging. The circuit layout of the unit and the significant increase in the cost of processes and inventory are really issues that need to be solved at present. [Summary of the Invention] In view of the shortcomings of the conventional technology described above, the main object of the present invention is to provide a core board with integrated resistance elements and a method for manufacturing the same, in which at least one groove or opening is formed in an insulating core board by a simple process. Holes to integrate and store passive component materials in the grooves or openings, so that users can form patterned conductive lines on the surface of the core board according to actual needs, and electrically connect the passive component materials. To complete the core board of the required electrical design. Another object of the present invention is to provide a core board with integrated resistance elements and a manufacturing method thereof, so as to apply a core board with integrated resistance elements to a semiconductor package substrate, increase the number of passive components in a semiconductor device, and increase the semiconductor package. The circuit layout of the substrate is flexible, and the area of the passive component on the substrate surface can be effectively saved.

17173. ptd Page 10 560230 V. Description of the invention (5) In order to achieve the disclosure and other purposes, the core board of the integrated resistance element of the present invention includes: an insulating core board, and at least one recess is formed in the core board. A slot or opening; a resistive material disposed in the opening of the core board; and at least one patterned conductive circuit layer formed on the surface of the core board ^, and the conductive circuit includes on one surface of the core board There are several circuit areas as resistive electrodes, and the resistive material in the groove or opening of the core board is selectively electrically connected to form a core board with integrated resistive elements. After that, a plurality of layered structures can be completed on at least one surface of the core board to form a layered circuit board. The core board manufacturing method of the integrated resistance element mainly provides an insulating core board, and at least one groove or opening is formed in the core board to fill the resistance material; a pattern is formed on at least one surface of the core board A conductive circuit layer, and the conductive circuit includes a plurality of circuit areas as resistance electrodes on one surface of the core board to selectively electrically connect the resistance material in the core board groove or opening to form an integrated resistor The core board of the component. After that, a number of layered structures can be completed on at least one side of the core board, that is, a layered circuit board is formed. In addition, at least one conductive via (C ο nductivevia) may be formed in the core board to electrically conductively connect the conductive lines on the upper surface and the lower surface of the core board with each other. Complete the electrical design of the passive components of the core board to provide the electrical functions required by the user. In the present invention, the core board with integrated resistance elements can be applied to a semiconductor package substrate, and an insulation layer is provided on at least one surface of the core board with integrated passive elements by using a build-up (Bui 1 d-up) technology. Layer to form at least one circuit layer, and the circuit layer is formed by conductive blind holes formed in the insulating layer

17173. ptd Page 11 56〇230 V. Description of the invention (6) md Via) Electrically connect to the conductive line and resistance of the surface of the board to form a circuit board, and the multilayer circuit board can be Used in Flip Chip semiconductor package substrates, or general wire-type semiconductor package substrates, to increase the number of components in a semiconductor device, 1 to increase the flexibility of the circuit layout of the substrate, and effectively named passive components Use area on substrate surface. User: The core board of the integrated resistance element invented by U can not only provide the function of Raco and electronic devices (such as semiconductor package substrates and printed circuits with the same patterning function), and the core board with embedded resistance material The surface is formed unexpectedly. After finishing the electrical circuit, the electrical design required for the electrical connection between the resistance material substrate and the g brush formed in the core board is applied to the semiconductor package-like passive component circuit board to avoid It is known that the resistance value of the film placed between the layers of the multi-layer circuit board is complicated due to the complicated process, and the circuit board responds to different design requirements. When 11 characteristics are caused, the manufacturing cost of the multilayer electrical inventory cost must be redesigned and stacked. The problem of material management and the quantity of materials, and you add. At the same time, improve the substrate surface of the passive components in the semiconductor device: increase the flexibility of the layout of the substrate circuit, and effectively save the passive components in the photo plastic basin = use area to improve electronic products Electrical function, but does not have line layout. No two: The embodiment further describes the present invention in detail, but the present invention is not, She further embodiment i is limited only drawings of the present invention is simple in each of said levels:. Ϊ actual size unreacted i.e. the H # - two of said multilayer substrate structure consistent actual size, be thoroughly applied stating embodiment] L shell.

560230 V. Description of the invention (7) Please refer to FIG. 6, which is a schematic cross-sectional view of the core board of the integrated resistance element of the present invention. As shown in the figure, the core board 3 of the integrated resistance element mainly includes an insulating core board 31, and at least one opening 32 or groove is formed in the core board 31, and the resistance element 3 3 is disposed in In the opening 32 of the core board 31; and a patterned conductive circuit layer 34, which is covered on at least one surface of the core board 31, and the conductive circuit 34 is in one of the core boards 31 The surface contains several circuit areas as resistance electrodes 3 4 a to selectively electrically connect the resistance material in the core plate 3 1 openings 3 2 or grooves to form a core plate 3 with integrated resistance elements 3 3 . The material of the insulating core plate 31 may be an insulating organic material or a ceramic material, such as epoxy resin (E ρ ο X yresi η), polyethylenimine (P ο 1 yimide), and bismaleimide diimide. / Triazine-based resin, or its composite material of glass fiber (G 1 asffber), of course, the insulating core board is not limited to being formed of a single organic material, but also < Layers of different insulation materials. The insulating core plate 3 1 has an upper surface 3 1 a and an opposite lower surface 3 1 b, and at least 〆 is formed in the core plate 3 and penetrates the core plate surface 3 1 a and the lower surface 3 1 b. The openings 3 2 are filled with a resistive material. The resistive element 3 3 contained in the core plate opening 32 is selected from a thick film (Thickfi 1 m) and a thin film (Thinfi 1 m) resistive material. The thick film resistive material is, for example, silver powder. Or carbon particles (Carbon part 1 e) are dispersed in the resin, and ruthenium oxide (ru 〇 2) and glass powder are dispersed in / binder coating and then solidified; the thin film resistor material

560230 V. Description of the invention (8) Materials such as nickel chromium (N i-C r), nickel scale (N i-P), nickel tin (N i-S η), chromium alloy (Cr-Al), and nitrogen Titanium (TaN) alloy or the like is placed in the core board opening 32, and when the conductive circuit layer 34 on the surface of the insulating core board 3 1 is subsequently formed, it also includes a resistance electrode 3 4 a to conduct the resistance material. , 俾 Complete the setting of the resistance element 3 3. As shown in Figs. 1 to 9, it is a schematic cross-sectional view of a manufacturing process of a core board with integrated resistance elements of the present invention and subsequent use of the core board to form a multilayer circuit board. Referring to FIG. 1, a core plate 31 is provided. The core plate 31 has an upper surface 3a and a lower surface 31b. Please refer to FIGS. 2A and 2B, at least one opening 3 2 is formed in the core plate 31 penetrating the upper surface 3 1 a and the lower surface 3 1 b of the core plate 31 (as shown in FIG. 2 A); Or at least one groove 3 2 a is formed on at least one surface of the core plate 31, and the groove 3 2 a does not penetrate the lower surface of the core plate (as shown in FIG. 2B). The size of the opening 32 or the groove 3 2 a of the core plate can be changed, and it is used to store resistance materials of different sizes. Please refer to Figures 3 A and 3 B, and then fill a resistive material into the opening 3 2 of the core plate 31 (as shown in Figure 3 A), or fill the groove of the core plate 31 Within 32a (as shown in Figure 3B). The resistive material may be any of the thick-film or thin-film resistive materials previously described. Furthermore, since the resistive material is provided in the opening 3 2 or the groove 3 2 a of the core board, it can provide the same resistance effect, so the following description will be based on the opening of the core board 31 only. The hole 32 is formed of a resistive material as an illustration. Please refer to Figs. 4A and 5A, a patterned resistance electrode is formed on the surface of the core plate in which a resistance material is embedded for selective electrical conduction.

17173. ptd Page 14 560230 V. Description of the invention (9) The resistive material in the opening of the flip board can be formed by the conductive circuit area by etching. 'A metal layer 34b is first laid on the surface of the core board 31. A patterned resist 3 5 'is formed on the metal layer 3 4 b by a developing technique (deve 10 ping). The resist layer may be a photoresist or a dry film to cover the patterned conductive lines and For the circuit area of the resistance electrode (as shown in FIG. 4A), a conventional process such as an etching technique (Etching) for forming a circuit is used to remove the metal layer outside the conductive circuit area to leave a patterned The conductive circuit layer 34 (as shown in FIG. 5A). Another clear tea is shown in Figures 4B and 5B. Patterned resistance electrodes are formed on the surface of the core plate embedded with the resistance material for selective electrical conduction of the resistance material formed in the opening of the cross plate. It is also possible to use electroplating to form a conductive circuit region (as shown in FIG. 4B), which is formed by first laying a resist layer 3 5 on the surface of the core board 3, the resist layer may be a photoresist or a dry film, and The resist layer 3 5 is formed with a plurality of openings 3 5 a by a development technique (Deve 1 ping), and the surface of the core board 3 1 is to be exposed with a patterned conductive circuit and a circuit area to be used as a resistance electrode. Then, a thin conductive metal layer 36 is formed on the surface of the resistance layer 35 and the exposed core plate as a conductive path for the subsequent key metal layer. A patterned conductive circuit layer is formed by electroplating in the opening 35a of the resistance layer 35. 3 4 (as shown in Figure 5B). The conductive metal thin layer 36 may be composed of a metal, an alloy, or a stack of several metal layers, and may be selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, or tin-tallium alloy. It can be formed by physical vapor deposition (PVD), chemical vapor deposition (QCVD), no electric clock or chemical deposition; temples, such as spu 11 ering, evaporation, arc vapor deposition ( arc vapor

17173. ptd Page 15 560230 V. Description of the invention (ίο) deposition), ion beam sputtering (laser bonding), laser ablation deposition, plasma-assisted chemical vapor deposition or organic Chemical vapor deposition of metals. Please refer to FIG. 6, which is the development and etching method in FIG. 5A to remove the metal layer outside the area of the non-conducting circuit, and then remove the resistive layer 3 5 formed on the anger plate 3 1 'or In FIG. 5B, after the metal layer is deposited in the conductive circuit region by using the electric money deposition method, the resist layer 3 5 formed on the core board 3! Is removed, and then it is pressed on the surface of the core board 31. A patterned conductive circuit layer 34 (Pattern Circuit) is formed, and the conductive circuit layer 34 includes a plurality of circuit areas on one of the surfaces of the nucleus 31 as a Λ 4 4 resistance electrode 34 a for selective electrical conduction. The materials embedded in the core board 31 are made of materials such as,,,,, and so on to form a core board 3 integrated with electric power and components 3 3. Previously, in the Chinese style, it was only shown that conductive lines were formed on the upper surface of the plate. Of course, conductive lines were also formed on the upper and lower surfaces of the plate. Please refer to Figure 7 at the same time. You can use the circuit board layering technology. &Gt; The surface of the core board 3 of the under-resistance element 3 3 forms at least one insulation; 4 &amp; has an insulation layer 3 7 At least one opening 3a is formed to be exposed outside ^, and the conductive lines under the layer 37 are formed in the insulating layer 37 to rush to the insulation 3 8a, to provide subsequent formation of _ on the surface of the insulating layer 37 When the blind holes are counted, the conductive holes of the circuit layer 3 8 can be covered by the conductive blind holes 3 8 a (as shown in FIG. 8). ; Under the side insulation layer Please also refer to FIG. 9, of course, it is also possible to space the insulation layer 3 7 from the upper and lower surfaces of the core board 3 3 at the same time to form = there are resistors

Layer 38, and by forming at least ~ at least one circuit in the insulating layer 37 ~ blind hole 38a to electrically 17173. ptd page 16 560230 V. Description of the invention (11) The core board is electrically connected to form a multilayer circuit A patterned copper-layered organic material or particles of the present invention which are entirely filled with a resistance material are determined. This has at least one conductive surface on the core board and completes the electrical process of the core board, and the entire (B ui 1 d-u ρ) technical edge layer is formed to form a multilayer of conductive lines at least on the conductive surface of the insulating layer Circuit board. Chip (semiconductor packaging) The number of layouts of semiconductor components, passive components on the substrate. Therefore, the present invention is based on the required electronic electrical functions, with the structure of the conductive circuit layer 34 and the resistance electrode 34a on the 3 surface, and the structure of the plate 30. . The layered circuit layer 38 may be made of an electrically insulating material such as a reinforced organic material. The core board incorporating the resistance element is an insulating core board, and the resistance value of the resistance material can be filled with the resistance filled in the opening or groove of the core board. Through the conductive vias in the insulating core board, the conductive lines on the lower surface are mutually electrically conductive, and the simple and convenient "connectivity design" is used to provide users with the required electricity. The core board of the resistive element can be used to do the conventional operation ^ in order to gate the conductive circuit on the surface of the core board] 21 circuit layers, and the increased circuit layer is borrowed from 22, blind holes (B1 ind Via) to electrically connect / complex the conductive circuit including a resistance electrode, &quot; in which the multilayer circuit board can be used to form a [substrate, or general hiccup ★, Japanese and Japanese (FHp ί Breaking the substrate to improve the semiconductor, surface use area. ^ Li Ju Sui, and effectively save the integration of integrated resistance elements (such as semiconductor sealing beauty "e can provide users

Han Quyang forms different patterns

560230 V. Description of the invention (12) The conductive circuit layer can be used in semiconductor packaging substrates and printed circuit boards to form a multi-layer circuit board after completing the required electrical design, avoiding being familiar with multi-layer circuit boards. When the film-shaped passive components are placed between layers, the manufacturing process is cumbersome, and the electrical characteristics such as resistance values according to different design requirements must be redesigned and stacked. The multilayer circuit board must be redesigned and stacked. Increase in material inventory costs. At the same time, the number of passive components in the semiconductor device can be increased, and the flexibility of the layout of the substrate circuit can be increased, which effectively saves the area of the passive components on the substrate surface, so as to achieve the goal of thin, light and short semiconductor devices. In the previous drawings, only some of the resistance elements are shown. In fact, the number and relative position of the resistance elements are designed according to the actual process requirements and embedded in the openings or grooves of the core board. The specific embodiments described above are only used to illustrate the features and effects of the present invention, rather than to limit the implementable scope of the present invention. Any application without departing from the spirit and technical scope of the present invention is disclosed. Equivalent changes and modifications made by the disclosure of the present invention shall still be covered by the scope of patent application described below.

17173. ptd Page 18 560230 Brief description of the drawings [Simplified description of the drawings] Figure 1 is a schematic cross-sectional view of an insulating core board in the present invention; Figure 2 A is a cross-sectional schematic view of an opening formed in the insulating core board in the present invention FIG. 2B is a schematic cross-sectional view of a groove formed in an insulating core board in the present invention, and FIG. 3A is a cross-sectional schematic view of filling a resistive material in an opening of an insulating core board in the present invention; FIG. 3B is a view in the present invention A schematic cross-sectional view of an insulating core plate filled with a resistive material; FIG. 4A is a cross-sectional view of forming a metal layer and a resistance layer on the surface of the insulating core plate in the present invention, and FIG. 4B is an insulating core plate in the present invention. A schematic cross-sectional view of a resist layer and a conductive metal layer formed on the surface; FIG. 5A is a schematic cross-sectional view of a metal layer removed by developing and etching in the present invention; FIG. 5B is a partial metal layer deposited by electroplating in the present invention The cross-section is not intended. Figure 6 is a schematic cross-sectional view of a conductive circuit layer formed on the surface of a core board embedded with a resistance material in the present invention. Figures 7 to 9 are core boards with integrated resistance elements in the present invention. A schematic view of the line circuit layer by layer; a first graph 10 conventional passive element disposed on a semiconductor wafer a schematic view of the area of the outer contact areas of the board opposed additional layout; and

17173. ptd Page 19 560230 Brief description of the drawings Figure 11 is a schematic cross-sectional view of the conventional method of placing a film resistance element between layers of a multilayer circuit board. 1 Substrate 2, 30 Multi-layer circuit board 3 Core board 11 Semiconductor wafer 12 Passive element 20a, 33 Resistive element 21, 34 Conductive circuit layer 21a, 34a Resistive electrode 31 Insulated core board 31a Upper surface 31b Lower surface 32 Opening hole 32a Groove 34b Metal layer 35 Resistive layer 36 Conductive metal layer 37 Insulating layer 37a Insulating layer opening 38 Circuit layer 38a Conductive blind hole

17173.ptd Page 20

Claims (1)

560230 6. Scope of patent application 1. A core board with integrated resistance elements, comprising: an insulating core board with at least one recess formed in the core board; a resistive material filled in the recess of the core board; And a patterned conductive circuit layer is formed on at least one surface of the core board, and the conductive circuit includes a resistance electrode on any surface of the core board, and selective electrical conduction is filled in the recess of the core board. Resistive materials. 2. For example, the core board of the integrated resistance element of the scope of the patent application, wherein the recess is an opening penetrating the surface of the core board. 3. For example, the core board of the integrated resistance element of the scope of patent application, wherein the recess is a groove formed on the surface of the core board. 4. For example, the core board of the integrated resistive element in the scope of the patent application, wherein the resistive material is any one of a thick film and a thin resistive material. 5. For example, the core board of the integrated resistance element in the scope of the patent application, wherein the thick film resistance material is silver powder (S i 1 ver ρ 〇wder), carbon particles (C arb ο npartic 1 e) are dispersed in the resin In addition, ruthenium oxide (R u 0 2) and glass powder are dispersed in a binder (B inder) and coated with solid dagger. 6. If the core board of the integrated resistance element is applied for item 4 of the patent scope, wherein the thin film resistance material is nickel chromium (N i-C r), nickel structure (N i-P), nickel tin (Ni-Sn ), Chrome-aluminum (Cr-Al), and titanium nitride (TaN) alloys. 7. If the core board of the integrated resistance element is applied for in the scope of patent application, the 17173.ptd Page 21 560230 6. In the scope of patent application, the resistance value of the resistance element can be determined according to the size of the resistance material used and the resistance material filled in the recess of the core board. 8. For example, the core board of the integrated resistive element of the scope of the patent application, wherein the core board is formed with at least one conductive via (conductive v i a) to provide electrical conduction between the upper and lower surfaces of the core board. 9. For example, the core board of the integrated resistance element of the scope of the patent application, wherein the core board can form at least one circuit with an insulating layer on at least one surface thereof by a build-up (Bui 1 d-up) technology. Layers to form a multilayer circuit board. 10. If the core board of the integrated resistive element is applied for item 9 of the scope of the patent application, the multilayer circuit board can be applied to a flip-chip semiconductor package substrate and a wiring semiconductor package substrate. Either. 1 1. A method for manufacturing a core plate for integrating resistance elements, comprising: providing an insulating core plate, and forming at least one recess in the core plate; filling the recess portion of the core plate with a resistance material; and at least one of the core plate A patterned conductive circuit layer is formed on the surface, and the conductive circuit includes a resistive electrode on any surface of the core board, and the conductive material filled in the recess of the core board is selectively electrically conductively connected. 1 2. The method of manufacturing a core plate of an integrated resistive element according to item 11 of the patent application scope, wherein the recess is an opening penetrating the surface of the core plate. 1 3. The method for manufacturing a core plate of an integrated resistance element according to item 11 of the patent application scope, wherein the recess is a groove formed on a surface of the core plate. 17173. ptd, page 22, 560230 6. Application for patent scope 1 4. For the core board manufacturing method of integrated resistive element according to item 11 of the patent scope, where the resistive material is thick film (T hickfi 1 m) and thin film (Thin fi lm) Any of resistive materials. 1 5. According to the core board manufacturing method of integrated resistance element according to item 14 of the scope of patent application, wherein the thick film resistance material is silver powder (S i 1 ver ρ 〇wder), carbon particles (C arb ο npartic 1 e) It is formed by spreading in resin, and spreading and curing any one of ruthenium oxide (R u 0 2) and glass powder with a binder (B inder). 16. According to the core board manufacturing method of integrated resistance element according to item 14 of the scope of patent application, wherein the thin film resistance material is nickel chromium (Ni-Cr), nickel phosphorus (Ni-P), nickel tin (Ni -Sn), chrome-aluminum (Cr-Al), and titanium nitride (TaN) alloys. 1 7. According to the core board manufacturing method of integrated resistance element according to item 11 of the scope of patent application, the resistance value of the resistance element can be determined according to the size of the resistance material used and the size of the resistance material filled in the recess of the core plate. Decide. 1 8. According to the core board manufacturing method of the integrated resistance element according to item 11 of the patent application scope, at least one conductive via is formed in the core board to provide mutual electrical properties between the core board and the lower surface. Lead. 19. According to the method for manufacturing a core plate of an integrated resistance element according to item 11 of the scope of patent application, wherein the method of forming the conductive circuit region is to lay a metal layer on the surface of the core plate, and form a metal layer on the metal layer. Patterned resistive layer to cover the patterned conductive lines and 17173.ptd Page 23 560230 6. The scope of the patent application is the circuit area of the resistance electrode, and an etching process is performed to form the circuit to remove the metal layer outside the conductive circuit area, leaving a patterned Conductive circuit layer. 2 0. According to the method of manufacturing a core board for integrated resistance elements according to item 11 of the patent application, where the method of forming the conductive circuit region is to lay a resistance layer on the surface of the core board, and form a majority of the resistance layer. Outside the opening, the surface of the core plate where a patterned conductive circuit is to be formed and a circuit area to be used as a resistance electrode are exposed, and then a thin conductive metal layer is formed on the exposed surface of the resistance layer and the core plate to be used as the conductivity of the subsequent plating metal layer In one approach, a patterned conductive circuit layer is formed by electroplating in the openings of the resist layer. 2 1. According to the core board manufacturing method of the integrated resistance element of item 11 of the scope of patent application, the layered insulation (B ui 1 d-up) technology can be used to separate insulation on at least one surface of the core board of the integrated resistance element. The layers form at least one circuit layer to form a multilayer circuit board. 2 2. If the core board manufacturing method of the integrated resistance element according to item 21 of the patent application scope, wherein the multilayer circuit board can be applied to a flip-chip type (F 1 ip Ch ip) semiconductor package substrate and a wiring type (Wireb ο nding) ) Any one of the semiconductor package substrates. 2 3. If the core board manufacturing method of the integrated resistive element according to item 19 or 20 of the patent application scope, wherein the resist layer is any one of a photoresist and a dry film. 17173.ptd Page 24