CN105895583A - 半导体器件和方法 - Google Patents
半导体器件和方法 Download PDFInfo
- Publication number
- CN105895583A CN105895583A CN201510464823.4A CN201510464823A CN105895583A CN 105895583 A CN105895583 A CN 105895583A CN 201510464823 A CN201510464823 A CN 201510464823A CN 105895583 A CN105895583 A CN 105895583A
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- semiconductor element
- semiconductor
- semiconductor device
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- device chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 311
- 238000000034 method Methods 0.000 title claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 37
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 15
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- 239000004020 conductor Substances 0.000 description 9
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- -1 SOI Chemical compound 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
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- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 108010022579 ATP dependent 26S protease Proteins 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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Abstract
提供了半导体器件和制造方法。在实施例中,在半导体晶圆内形成第一半导体器件和第二半导体器件,并且图案化第一半导体器件和第二半导体器件之间的划线区。然后,在划线区内利用分割工艺以将第一半导体器件与第二半导体器件分割开。然后将第一半导体器件和第二半导体器件接合至第二半导体衬底并且被减薄以从第一半导体器件和第二半导体器件去除延伸区。本发明涉及半导体器件和方法。
Description
技术领域
本发明涉及半导体器件和方法。
背景技术
通常通过利用半导体衬底和在半导体衬底内或在半导体衬底的顶部上制造器件来制造半导体器件。一旦制造了这些器件,通过在单独的器件上方和在半导体衬底上方制造一个或多个金属化层来电连接单独的器件。这些一个或多个金属化层可以包括通过介电层分隔开的不但将单个器件彼此连接而且也连接至外部器件的导电层。
然而,不单独地制造单独的半导体管芯。相反,在单个半导体晶圆上形成多个半导体管芯。一旦已经形成管芯,分割半导体晶圆,从而使得单独的管芯彼此分离,并且可以被单独地利用。
不幸的是,分割工艺充满了可能导致灾难性的后果的潜在的危害。当将管芯分隔开时,在分离单独的管芯中可能涉及的物理和热应力可能损坏单独的管芯,使它们具有缺陷,在最坏的情况下,无法使用。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种制造半导体器件的方法,所述方法包括:在第一半导体管芯和第二半导体管芯之间的第一半导体晶圆中形成第一开口,所述第一开口具有与所述第一半导体晶圆的主要表面平行的第一宽度;分割所述第一半导体晶圆以形成第二开口,其中,所述第一开口和所述第二开口将所述第一半导体管芯与所述第二半导体管芯分隔开,所述第二宽度具有与所述第一半导体晶圆的主要表面平行的第二宽度,所述第二宽度小于所述第一宽度;以及减薄所述第一半导体管芯,直到所述第一半导体管芯具有笔直侧壁。
在上述方法中,还包括:在减薄所述第一半导体管芯之前,将所述第一半导体管芯接合至半导体衬底上。
在上述方法中,还包括:在减薄所述第二半导体管芯之前,将所述第二半导体管芯接合至所述半导体衬底上。
在上述方法中,至少部分地使用化学机械抛光工艺实施减薄所述第一半导体管芯。
在上述方法中,减薄所述第一半导体管芯去除了位于所述第一半导体管芯上的延伸区。
在上述方法中,形成所述第一开口也使所述第一半导体管芯的拐角变圆。
在上述方法中,至少部分地使用干蚀刻工艺实施形成所述第一开口。
根据本发明的另一方面,还提供了一种制造半导体器件的方法,所述方法包括:在半导体衬底内至少部分地形成第一半导体管芯和第二半导体管芯;去除所述半导体衬底的第一部分,其中,所述第一部分位于所述半导体衬底的划线区内;以及使用锯片去除所述半导体衬底的第二部分,其中,去除所述半导体衬底的第一部分和去除所述半导体衬底的第二部分将所述第一半导体管芯与所述第二半导体管芯分隔开并且也在所述第一半导体管芯上形成半导体材料延伸件。
在上述方法中,还包括:从所述第一半导体管芯去除所述半导体材料延伸件。
在上述方法中,去除所述半导体材料延伸件还包括对所述第一半导体管芯实施减薄工艺。
在上述方法中,至少部分通过化学机械抛光工艺实施所述减薄工艺。
在上述方法中,还包括:在所述减薄工艺之前,将所述第一半导体管芯接合至半导体晶圆。
在上述方法中,去除所述半导体衬底的第一部分还包括:在所述第一半导体管芯上方形成掩模;以及通过所述掩模实施干蚀刻以去除所述半导体衬底的第一部分。
在上述方法中,去除所述第一部分在所述半导体衬底上形成至少部分地弯曲的侧壁。
根据本发明的又一方面,还提供了一种制造半导体器件的方法,所述方法包括:在第一半导体管芯和第二半导体管芯之间的第一半导体晶圆内形成第一开口,其中,至少部分利用蚀刻工艺实施形成所述第一开口;在所述第一半导体管芯和所述第二半导体管芯之间的所述第一半导体晶圆内形成第二开口,其中,至少部分利用锯切工艺实施形成所述第二开口,并且其中,所述第二开口比所述第一开口具有更小的宽度,并且所述第一开口和所述第二开口将所述第一半导体管芯与所述第二半导体管芯分割开;将所述第一半导体管芯和所述第二半导体管芯接合至第二半导体晶圆;以及在接合所述第一半导体管芯和所述第二半导体管芯之后,减薄所述第一半导体管芯和所述第二半导体管芯,其中,减薄所述第一半导体管芯和所述第二半导体管芯从所述第一半导体管芯和所述第二半导体管芯去除延伸区。
在上述方法中,至少部分通过化学机械抛光工艺实施所述减薄工艺。
在上述方法中,形成所述第一开口将所述第一半导体管芯的拐角图案化成圆形形状。
在上述方法中,至少部分通过湿蚀刻工艺实施形成所述第一开口。
在上述方法中,还包括:在形成所述第一开口之后并且在形成所述第二开口之前,减薄所述第一半导体管芯和所述第二半导体管芯。
在上述方法中,在形成所述第一开口之后并且在形成所述第二开口之前,至少部分利用化学机械抛光工艺实施减薄所述第一半导体管芯和所述第二半导体管芯。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的位于半导体衬底内和半导体衬底上的第一半导体器件、第二半导体器件和第三半导体器件。
图2示出了根据一些实施例的光刻胶在半导体衬底上方的放置。
图3示出了根据一些实施例的通过光刻胶的半导体衬底的图案化。
图4A至图4B示出了根据一些实施例的光刻胶的去除。
图5示出了根据一些实施例的保护层的放置。
图6示出了根据一些实施例的半导体衬底的分割。
图7示出了根据一些实施例的将第一半导体器件、第二半导体器件和第三半导体器件接合至半导体晶圆。
图8示出了根据一些实施例的第一半导体器件、第二半导体器件和第三半导体器件的减薄。
具体实施方式
应当理解,以下公开内容提供了许多用于实现本发明的不同特征的许多不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在第二部件上方或者之上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和字符。这种重复是为了简化和清楚的目的,并且其本身并不表示所论述的实施例和/或结构之间的关系。
另外,为便于描述,本文中可以使用诸如“在…之下”、“在…下方”、“下”、“在…之上”、“上”等的空间相对位置术语,以描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的方位外,空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且因此可以对本文中使用的空间相对位置描述符同样作相应的解释。
现在参考图1,示出了第一晶圆101,第一晶圆101具有在第一晶圆101内形成的第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107。在实施例中,第一晶圆101包括第一衬底109、第一有源器件层111、第一金属化层113、第一钝化层114、和第一接触焊盘115。第一衬底109可以包括掺杂或未掺杂的块状硅、或绝缘体上硅(SOI)衬底的有源层。通常,SOI衬底包括诸如硅、锗、锗硅、SOI、绝缘体上锗硅(SGOI)或它们的组合的半导体材料的层。可以使用的其他衬底包括多层衬底、梯度衬底、玻璃衬底、陶瓷衬底、或混合取向衬底。
第一有源器件层111可以包括诸如晶体管、电容器、电阻器、电感器等的各种各样的有源器件和无源器件,其可以用于生成期望用于第一晶圆101的设计的期望的结构和功能。可以在第一衬底109内或在第一衬底109上使用任何合适的方法形成第一晶圆101内的有源器件。
第一金属化层113形成在第一衬底109以及第一有源器件层111内的有源器件上方并且可以用于使例如第一有源器件层111内的有源器件互连。在实施例中,第一金属化层113由介电材料和导电材料的交替层形成并且可以通过诸如沉积、镶嵌、双镶嵌等的任何适合的工艺形成。在实施例中,可能有四个金属化层,但是介电材料和导电材料的层的确切数量取决于第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107的设计。
第一钝化层114可以由诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物、它们的组合等的一种或多种合适的介电材料制成。可以通过诸如化学汽相沉积(CVD)的工艺形成第一钝化层114,但是可以利用任何合适的工艺,并且第一钝化层114可以具有在约0.5μm和约5μm之间的厚度,诸如约
第一接触焊盘115可以形成在第一金属化层113上方并且与第一金属化层113电接触以为第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107提供外部连接。第一接触焊盘115由诸如铝的导电材料形成,但是可以可选地利用诸如铜、钨等的其他合适的材料。可以使用诸如CVD的工艺形成第一接触焊盘115,但是可以可选地利用其他合适的材料和方法。一旦已经沉积用于第一接触焊盘115的材料,可以使用例如光刻掩蔽和蚀刻工艺将材料成形为第一接触焊盘115。
在实施例中,第一半导体器件芯片103、第二半导体器件芯片105、和第三半导体器件芯片107形成在第一晶圆101内并且通过划线区(在图1中由标记为117的虚线表示)分隔开,第一晶圆101沿着划线区将被分隔开以形成单独的第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107。划线区117并不是通过将功能结构(诸如有源器件)放置在旨在用于划线区117的区域内形成的。可以将诸如用于平坦化的测试焊盘或伪金属的其他结构放置在划线区117内,但是一旦第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107已经彼此分离,诸如用于平坦化的测试焊盘或伪金属的其他结构对于第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107的功能将不是必须的。划线区117可以形成为具有在约10μm和约200μm之间的第一宽度W1,诸如约80μm。
图2示出了光刻胶201在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107上方的放置。在实施例中,光刻胶201是光敏材料并且可以使用例如旋涂技术放置在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107上以具有在约0.5μm和约15μm之间的高度,诸如约5μm。一旦放置在合适的位置,然后可以通过将光刻胶201暴露于图案化的能量源(例如,图案化的光源)以引发化学反应,从而诱导在暴露于图案化的光源的光刻胶201的那些部分中的物理变化来图案化光刻胶201。然后将显影剂应用于曝光的光刻胶201以利用物理变化和取决于所期望的图案而选择性地去除光刻胶201的曝光部分或光刻胶201的未曝光部分。
在实施例中,图案化光刻胶201以形成暴露出划线区117的第一开口203。因此,第一开口203可以形成为具有划线区117的第一宽度W1,诸如介于约10μm和约150μm之间,诸如约80μm。然而,可以可选地利用任何其他合适的宽度。
图3示出了一旦已经在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107上方放置并且图案化光刻胶201,可以实施第一蚀刻工艺(在图3中通过标记为301的箭头表示)以使第一开口203延伸穿过第一钝化层114、第一金属化层113、第一有源器件层111并且进入第一衬底109内。在实施例中,例如,第一蚀刻工艺可以是一个或多个反应离子蚀刻工艺,其利用一种或多种蚀刻剂以定向地蚀刻穿过第一金属化层113、第一有源器件层111并且进入第一衬底109内。
从而,虽然利用的精确的蚀刻剂和工艺条件将至少部分取决于选择用于每一层的材料,在第一衬底109是硅的实施例中,当蚀刻第一衬底109时,第一蚀刻工艺301可以利用诸如F-化学物质或O2的蚀刻剂,以及任选地,诸如氩气的载气,但是可以可选地利用任何合适的蚀刻剂。
此外,用于反应离子蚀刻的RF功率可以设置为介于约100W和约4000W之间,诸如约2500W,并且偏置电压可以设置为介于约10V和约500V之间,诸如约200V。最后,蚀刻腔室的压力可以设置为在约10毫托和约200毫托之间,诸如约90毫托,并且工艺的温度可以控制为在约-20℃和约50℃之间,诸如约0℃。然而,这些条件旨在用于说明,可以可选地利用任何合适的蚀刻条件,并且所有这些工艺条件预期完全包括在该实施例的范围内。
在实施例中,可以利用第一蚀刻工艺301以使第一开口203至少部分地延伸至第一衬底109内。例如,可以利用第一蚀刻工艺301以使第一开口203延伸至第一衬底109内的第一深度D1处,第一深度D1在约5μm和约100μm之间,诸如约30μm。可以可选地利用任何其他合适的深度。
然而,虽然可以利用以上描述的干蚀刻工艺以图案化第一衬底109,但是该描述旨在仅为说明性的并且不旨在限制该实施例。例如,可以可选地使用可形成弯曲侧壁的湿蚀刻工艺,在湿蚀刻工艺中,第一晶圆101浸没在诸如处于约室温和约80℃之间的温度下的HF基溶液或TMAH的液体蚀刻剂中并且持续约1分钟和约30分钟之间的时间段。可以使用图案化第一衬底109的任何合适的方法,并且所有这些方法预期完全包括在该实施例的范围内。
图4A示出了去除光刻胶201和去除后清洗工艺。在实施例中,例如,可以利用灰化工艺去除光刻胶201,由此光刻胶201的温度升高直到光刻胶201经历热分解并且可以被很容易地去除。然而,可以可选地利用任何其他适合的去除工艺。
一旦已经实施灰化,可以使用第一清洗工艺清洗该结构以协助去除光刻胶201。在实施例中,第一清洁工艺可以包括将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107浸渍在蚀刻剂内以确保在随后处理之前,光刻胶201的任何剩余部分均从第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107去除。例如,第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107可以浸渍在诸如HF的蚀刻剂内并且持续约1秒和约100秒的时间,诸如约60秒。
图4B示出了在图4A中示出的实施例的自顶向下的视图。在该实施例中,划线区117被示出为在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107之间。然而,在该自顶向下视图中可以看出,可以利用第一蚀刻工艺301(上文结合图3描述)以形成用于每个第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107的圆形拐角(在图4B中通过标记401的圆形虚线表示)。具体地,在实施例中,第一半导体器件芯片103可以具有在约1mm和约30mm之间的第二宽度W2,诸如约4mm,和在约1mm和约30mm之间的第一长度L1,诸如约4mm,弯曲的拐角可以具有在约50μm和约500μm之间的圆弧半径R1,诸如约250μm。然而,可以可选地利用任何合适的圆弧半径。
通过使用第一蚀刻工艺301以在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107的拐角处形成圆形拐角401,第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107能够更好地承受在分割工艺期间(下文结合图6进一步描述)所涉及的应力。具体地,圆形拐角401可以分布和承受锯片物理切割和分离第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107的应力。因此,在分割工艺期间将发生更少的缺陷。
图5示出了保护膜501在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107上方的放置和第一衬底109的背侧的减薄。在实施例中,保护膜501可以是背侧研磨带(BG带),它可以用来保护第一衬底109的图案化的一侧以免在第一衬底109的减薄期间被研磨成碎片。可以使用例如滚筒(未在图5中单独示出)在第一开口203上方应用保护膜501。
然而,虽然保护膜501被描述为BG带,这旨在为说明性的并且不旨在限制本实施例。相反,可以可选地利用保护第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107(包括第一开口203)的图案化的表面的任何合适的方法。所有这些保护层预期完全包括在本实施例的范围内。
一旦第一开口203已经得到保护,例如利用第一减薄工艺(在图5中通过标记为501的旋转滚筒表示)来减薄第一衬底109。在实施例中,例如,可以使用化学机械抛光来减薄第一晶圆101,由此,利用化学反应物和研磨料的组合以及一个或多个研磨垫以去除与第一接触焊盘115相对的第一衬底109的部分。然而,可以可选地利用诸如物理研磨工艺、一个或多个蚀刻工艺、这些的组合等的任何其他合适的工艺。在实施例中,将第一晶圆101减薄至在减薄后具有在约100μm和约500μm之间的第一厚度T1,诸如约200μm。
图6示出了将第一晶圆101分割成第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107。在实施例中,在分割之前,首先去除保护膜501并且将第一晶圆101附接至支撑衬底601。例如,支撑衬底601可以是诸如通常已知的蓝胶带的胶带,并且用作控制第一晶圆101的放置的工具。因此,虽然在本文中将支撑衬底601称为胶带,支撑衬底601不限制于胶带,并且可以是根据期望提供第一晶圆101的放置的任何其他介质,诸如载体晶圆、载体玻璃、金属板或陶瓷板。
一旦附接至支撑衬底601,可以通过以下步骤来实施分割:通过使用锯片(在图6中通过标记为603的虚线框表示)来切割穿划线区117以穿过第一半导体器件芯片103和第二半导体器件芯片105之间以及第二半导体器件芯片105和第三半导体器件芯片107之间的第一衬底109而形成第二开口605。
在实施例中,利用锯片603以在第一半导体器件芯片103和第二半导体器件芯片105之间以及第二半导体器件芯片105和第三半导体器件芯片107之间切割第一衬底109而不需要从第一开口203的侧壁去除额外的材料。因此,第二开口605可以形成为具有第三宽度W3,第三宽度W3小于第一宽度W1,诸如在约10μm和约300μm之间,诸如约50μm。然而,任何合适的尺寸可用于第三宽度W3。因此,第一衬底延伸件607留在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107上。
此外,本领域普通技术人员会认识到,利用锯片分割第一晶圆101仅仅是一个说明性实施例,并且不旨在用于限制。可以可选地利用用于分割第一晶圆101的可选方法,诸如利用一次或多次蚀刻以将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107分隔开。可以可选地利用这些方法和任何其他合适的方法以分割第一晶圆101。
图7示出了以晶圆上芯片(CoW)接合配置将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107接合至第二晶圆701。第二晶圆701可以包括第二衬底703、第二有源器件层705、第二金属化层707、第二钝化层708和第二接触焊盘709,其可以分别类似于第一衬底109、第一有源器件层111、第一金属化层113、第一钝化层114和第一接触焊盘115。第二衬底703、第二有源器件层705、第二金属化层707、第二钝化层708和第二接触焊盘709可以形成第四半导体器件芯片711、第五半导体器件芯片713和第六半导体器件芯片715(通过第二划线区717分隔开),将利用第四半导体器件芯片711、第五半导体器件芯片713和第六半导体器件芯片715以分别与第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107结合操作。
例如,可以利用熔融接合工艺将第一半导体器件芯片103接合到第二晶圆701。在实施例中,可以通过对第二晶圆701的期望接合的位置首先实施清洗工艺来引发熔融接合工艺。在特定的实施例中,可以使用例如诸如SC-1或SC-2清洗工序的湿清洗工序来清洗第二晶圆701以形成亲水性表面。一旦被清洗,将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107对准在第二晶圆701上的它们的相应的期望位置内并且亲水性表面放置成与第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107物理接触以开始接合工序。一旦已经将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107与第二晶圆701接触,可以利用热退火以增强接合。
然而,上文描述的熔融接合的说明仅仅是可以利用以将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107接合至第二晶圆701的一种类型的工艺的实例,并且不旨在限制该实施例。相反,可以可选地利用任何合适的接合工艺以将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107接合至第二晶圆701,并且所有这些工艺预期完全包括在本实施例的范围内。
图8示出了在已将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107接合至第二晶圆701之后,用于将第一衬底延伸件607从第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107去除的第二减薄工艺(在图8中通过标记为801的旋转滚筒表示)。在实施例中,例如,可以使用化学机械抛光减薄第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107,从而利用化学反应物和研磨料的组合以及一个或多个研磨垫以去除与第一接触焊盘115相对的第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107的部分。然而,可以可选地利用任何其他合适的工艺,诸如物理研磨工艺、一个或多个蚀刻工艺、这些的组合等。在实施例中,将第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107减薄至足以去除第一衬底延伸件607的厚度,诸如减薄至诸如在约10μm和约250μm之间的第二厚度T2,诸如约25μm。然而,可以可选地使用任何合适的厚度。
通过在分割第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107之前,利用第一蚀刻工艺301以图案化划线区117,可以更好地松弛来自分割工艺的应力,并且可以最小化任何切割引起的碎片。因此,在第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107以及第二晶圆701之间可以获得更好的界面。因此,可以实现更好的管芯-晶圆熔融接合,从而导致更强的接合和较少的缺陷。
一旦第一半导体器件芯片103、第二半导体器件芯片105和第三半导体器件芯片107已经接合至第二晶圆701并且被减薄,可以对第二晶圆701实施额外的处理。例如,可以分割第二晶圆701自身以形成准备使用的半导体器件。
根据一个实施例中,提供了一种制造半导体器件的方法,该方法包括在第一半导体管芯和第二半导体管芯之间的第一半导体晶圆中形成第一开口,第一开口具有与第一半导体晶圆的主要表面平行的第一宽度。分割第一半导体晶圆以形成第二开口,其中,第一开口和第二开口将第一半导体管芯与第二半导体管芯分隔开,第二宽度具有与第一半导体晶圆的主要表面平行的第二宽度,第二宽度小于第一宽度。减薄第一半导体管芯直到第一半导体管芯具有笔直侧壁。
根据另一个实施例中,提供了一种制造半导体器件的方法,该方法包括:在半导体衬底内至少部分地形成第一半导体管芯和第二半导体管芯。去除半导体衬底的第一部分,其中,第一部分位于半导体衬底的划线区内。使用锯片去除半导体衬底的第二部分,其中,去除半导体衬底的第一部分和去除半导体衬底的第二部分将第一半导体管芯与第二半导体管芯分隔开并且也形成位于第一半导体管芯上的半导体材料延伸件。
根据又一个实施例中,提供了一种制造半导体器件的方法,该方法包括:在第一半导体管芯和第二半导体管芯之间的第一半导体晶圆内形成第一开口,其中,至少部分利用蚀刻工艺实施形成第一开口。在第一半导体管芯和第二半导体管芯之间的第一半导体晶圆内形成第二开口,其中,至少部分利用锯切工艺实施形成第二开口,并且其中,第二开口比第一开口具有更小的宽度,并且第一开口和第二开口延伸为将第一半导体管芯与第二半导体管芯分割开。将第一半导体管芯和第二半导体管芯接合至第二半导体晶圆。在接合第一半导体管芯和第二半导体管芯之后,减薄第一半导体管芯和第二半导体管芯,其中,减薄第一半导体管芯和第二半导体管芯从第一半导体管芯和第二半导体管芯去除延伸区。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种制造半导体器件的方法,所述方法包括:
在第一半导体管芯和第二半导体管芯之间的第一半导体晶圆中形成第一开口,所述第一开口具有与所述第一半导体晶圆的主要表面平行的第一宽度;
分割所述第一半导体晶圆以形成第二开口,其中,所述第一开口和所述第二开口将所述第一半导体管芯与所述第二半导体管芯分隔开,所述第二宽度具有与所述第一半导体晶圆的主要表面平行的第二宽度,所述第二宽度小于所述第一宽度;以及
减薄所述第一半导体管芯,直到所述第一半导体管芯具有笔直侧壁。
2.根据权利要求1所述的方法,还包括:在减薄所述第一半导体管芯之前,将所述第一半导体管芯接合至半导体衬底上。
3.根据权利要求2所述的方法,还包括:在减薄所述第二半导体管芯之前,将所述第二半导体管芯接合至所述半导体衬底上。
4.根据权利要求1所述的方法,其中,至少部分地使用化学机械抛光工艺实施减薄所述第一半导体管芯。
5.根据权利要求1所述的方法,其中,减薄所述第一半导体管芯去除了位于所述第一半导体管芯上的延伸区。
6.根据权利要求1所述的方法,其中,形成所述第一开口也使所述第一半导体管芯的拐角变圆。
7.根据权利要求1所述的方法,其中,至少部分地使用干蚀刻工艺实施形成所述第一开口。
8.一种制造半导体器件的方法,所述方法包括:
在半导体衬底内至少部分地形成第一半导体管芯和第二半导体管芯;
去除所述半导体衬底的第一部分,其中,所述第一部分位于所述半导体衬底的划线区内;以及
使用锯片去除所述半导体衬底的第二部分,其中,去除所述半导体衬底的第一部分和去除所述半导体衬底的第二部分将所述第一半导体管芯与所述第二半导体管芯分隔开并且也在所述第一半导体管芯上形成半导体材料延伸件。
9.根据权利要求8所述的方法,还包括:从所述第一半导体管芯去除所述半导体材料延伸件。
10.一种制造半导体器件的方法,所述方法包括:
在第一半导体管芯和第二半导体管芯之间的第一半导体晶圆内形成第一开口,其中,至少部分利用蚀刻工艺实施形成所述第一开口;
在所述第一半导体管芯和所述第二半导体管芯之间的所述第一半导体晶圆内形成第二开口,其中,至少部分利用锯切工艺实施形成所述第二开口,并且其中,所述第二开口比所述第一开口具有更小的宽度,并且所述第一开口和所述第二开口将所述第一半导体管芯与所述第二半导体管芯分割开;
将所述第一半导体管芯和所述第二半导体管芯接合至第二半导体晶圆;以及
在接合所述第一半导体管芯和所述第二半导体管芯之后,减薄所述第一半导体管芯和所述第二半导体管芯,其中,减薄所述第一半导体管芯和所述第二半导体管芯从所述第一半导体管芯和所述第二半导体管芯去除延伸区。
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US20160240439A1 (en) | 2016-08-18 |
US11688639B2 (en) | 2023-06-27 |
TWI579971B (zh) | 2017-04-21 |
KR101784655B1 (ko) | 2017-10-11 |
TW201630117A (zh) | 2016-08-16 |
US20200118879A1 (en) | 2020-04-16 |
US10510604B2 (en) | 2019-12-17 |
KR20170054357A (ko) | 2017-05-17 |
DE102015106064A1 (de) | 2016-08-18 |
US20190122930A1 (en) | 2019-04-25 |
US10163709B2 (en) | 2018-12-25 |
KR20160100178A (ko) | 2016-08-23 |
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