TW201630117A - 半導體裝置之製造方法 - Google Patents
半導體裝置之製造方法 Download PDFInfo
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- TW201630117A TW201630117A TW104126338A TW104126338A TW201630117A TW 201630117 A TW201630117 A TW 201630117A TW 104126338 A TW104126338 A TW 104126338A TW 104126338 A TW104126338 A TW 104126338A TW 201630117 A TW201630117 A TW 201630117A
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Classifications
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Abstract
本揭露係關於一種半導體裝置之製造方法。一種半導體裝置之製造方法包括形成一第一開口於一第一半導體晶圓中,第一開口位於一第一半導體晶粒與一第二半導體晶粒之間,第一開口具有一第一寬度平行於第一半導體晶圓的一主要表面。切割第一半導體晶圓以形成一第二開口,其中第一開口以及第二開口將第一半導體晶粒與第二半導體晶粒分離,第二開口具有一第二寬度平行於第一半導體晶圓的主要表面且小於第一寬度。薄化第一半導體晶粒直到第一半導體晶粒具有一筆直的側壁。
Description
本發明係有關於一種半導體裝置之製造方法,特別有關於一種具有切割道的半導體裝置及其製造方法。
半導體裝置通常利用一半導體基板來製造,並且在半導體基板之中或之上製造這些裝置。一旦這些裝置製造完成,藉由於半導體基板上製造一或多個金屬化層以電性連接各個裝置。這些一或多個金屬化層可包括由介電層分開的導電層,其不只將各個裝置彼此連接,也將其連接至外部裝置。
然而,各個半導體晶粒並不是被單獨製造的。相反地,多個半導體晶粒形成於單一的半導體晶圓上。一旦晶粒被形成,會切割該半導體晶圓,使得獨立的晶粒彼此分離並且可以單獨利用。
不幸的是,切割的過程充滿可能會有損失慘重的結果的潛在的危險。分離獨立晶粒時伴隨的物理以及熱應力可能在晶粒被分離時對其造成傷害,使它們出現缺陷並且,在最糟的情況下使其無法運作。
本揭露包括一種半導體裝置之製造方法,包括:形成一第一開口於一第一半導體晶圓中,第一開口位於一第一半導體晶粒與一第二半導體晶粒之間,第一開口具有一第一寬
度平行於第一半導體晶圓的一主要表面。切割第一半導體晶圓以形成一第二開口,其中第一開口以及第二開口將第一半導體晶粒與第二半導體晶粒分離,第二開口具有一第二寬度平行於第一半導體晶圓的主要表面且小於第一寬度。薄化第一半導體晶粒直到第一半導體晶粒具有一筆直的側壁。
本揭露亦包括一種半導體裝置之製造方法,包括:形成一第一半導體晶粒以及一第二半導體晶粒之至少部分於一半導體基板中。移除半導體基板的一第一部分,其中第一部分位於半導體基板的一切割區域中。使用一鋸片移除半導體基板的一第二部分,其中半導體基板的第一部分的移除以及半導體基板的第二部分的移除將第一半導體晶粒與第二半導體晶粒分離並且形成第一半導體晶粒上的複數半導體材料延伸。
本揭露亦包括一種半導體裝置之製造方法,包括:形成一第一開口於一第一半導體晶圓中,第一開口位於一第一半導體晶粒與一第二半導體晶粒之間,其中第一開口的形成至少部分是藉由一蝕刻製程實施。形成一第二開口於第一半導體晶圓中,第二開口位於第一半導體晶粒與第二半導體晶粒之間,其中第二開口的形成至少部分是藉由一切割製程實施且其中第二開口具有一寬度小於第一開口並且第一開口及第二開口將第一半導體晶粒自第二半導體晶粒切割。接合第一半導體晶粒以及第二半導體晶粒至一第二半導體晶圓。在接合第一半導體晶粒以及第二半導體晶粒後,薄化第一半導體晶粒以及第二半導體晶粒,其中第一半導體晶粒以及第二半導體晶粒的薄化自第一半導體晶粒以及第二半導體晶粒移除複數延伸區域。
101‧‧‧第一晶圓
103‧‧‧第一半導體裝置晶片
105‧‧‧第二半導體裝置晶片
107‧‧‧第三半導體裝置晶片
109‧‧‧第一基板
111‧‧‧第一主動裝置層
113‧‧‧第一金屬化層
114‧‧‧第一鈍化層
115‧‧‧第一接觸墊
117‧‧‧虛線/切割道
201‧‧‧光阻
203‧‧‧第一開口
301‧‧‧箭號/蝕刻製程
401‧‧‧圓化角落
501‧‧‧保護薄膜/第一薄化製程/旋轉平台
601‧‧‧支撐基板
603‧‧‧虛線方框/鋸片
605‧‧‧第二開口
607‧‧‧第一基板延伸部
701‧‧‧第二晶圓
703‧‧‧第二基板
705‧‧‧第二主動裝置層
707‧‧‧第二金屬化層
708‧‧‧第二鈍化層
709‧‧‧第二接觸墊
711‧‧‧第四半導體裝置晶片
713‧‧‧第五半導體裝置晶片
715‧‧‧第六半導體裝置晶片
717‧‧‧第二切割道
801‧‧‧第二薄化製程/旋轉平台
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
D1‧‧‧第一深度
L1‧‧‧第一長度
R1‧‧‧弧半徑
T1‧‧‧第一厚度
T2‧‧‧第二厚度
第1圖根據一些實施例,繪示一第一半導體裝置、一第二半導體裝置以及一第三半導體裝置於一半導體基板之中以及之上。
第2圖根據一些實施例,繪示光阻的設置於半導體基板上。
第3圖根據一些實施例,繪示半導體基板經由光阻進行圖案化。
第4A-4B圖根據一些實施例,繪示光阻的移除。
第5圖根據一些實施例,繪示一保護層的設置。
第6圖根據一些實施例,繪示半導體基板的一切割製程。
第7圖根據一些實施例,繪示將第一半導體裝置、第二半導體裝置及第三半導體裝置接合至一半導體晶圓。
第8圖根據一些實施例,繪示第一半導體裝置、第二半導體裝置及第三半導體裝置的一薄化製程。
本說明書的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵部件。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化發明的說明。當然,這些特定的範例並非用以限定本發明。例如,若是本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方,即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例,亦包含
了尚可將附加的特徵形成於上述第一特徵部件與上述第二特徵部件之間,而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。再者,本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述外觀結構之間的關係。
另外,在空間上的相關用語,例如“之下”、“以下”、“下方”、“之上”、“上方”等等係用以容易表達出本說明書中的部件或特徵部件與其他部件或特徵部件的關係。這些空間上的相關用語除了涵蓋了圖式所繪示的方位外,還涵蓋裝置於使用或操作中的不同方位。裝置可具有不同方位(旋轉90度或其他方位),則在此使用的空間相關詞也可依此相同解釋。
現在請參照第1圖,其繪示一第一晶圓101,其具有一第一半導體裝置晶片103、一第二半導體裝置晶片105以及一第三半導體裝置晶片107形成於第一晶圓101中。在一實施例中第一晶圓101包括一第一基板109、一第一主動裝置層111、一第一金屬化層113、一第一鈍化層114以及第一接觸墊115。第一基底109可包括塊狀矽、摻雜或未摻雜、或具有一主動層的一絕緣層上覆矽(silicon-on-insulator,SOI)基板。通常,一絕緣層上覆矽基板包括一層半導體材料例如矽、鍺、矽鍺、絕緣層上覆矽、絕緣層上覆矽鍺(silicon germanium on insulator,SGOI),或其組合。也可使用其他基板包括多層基板、梯度基板(gradient substrate)、玻璃基板、陶瓷基板,或混合定向基板
(hybrid orientation substrate)。
第一主動裝置層111可包括各種不同的主動裝置與被動裝置,例如電晶體、電容器、電阻器、感應器以及類似的裝置,其可用來產生第一晶圓101的設計上需要的結構或功能需求。可使用任何適合的方法形成主動裝置於第一晶圓101之中或之上,或形成在第一基板109之中或之上。
第一金屬化層113形成於第一基板109與位於第一主動裝置層111中的主動裝置上,並且可用於內連接,例如位於第一主動裝置層111中的主動裝置。在一實施例中,第一金屬化層113由介電材料與導電材料交替的層膜形成且可以藉由任何適合的製程(例如沉積製程、鑲嵌製程、雙鑲嵌製程等)形成。在一實施例中,有四層金屬化層,但是確切的介電材料與導電材料的層膜數量取決於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107的設計。
第一鈍化層114可由一或多個適合的介電材料形成,例如氧化矽、氮化矽、低介電常數介電質(例如,碳摻雜之氧化物)、超低介電常數介電質(例如,多孔碳摻雜之二氧化矽)、聚合物(例如聚醯亞胺(polyimide))、其組合或與其相似的材料。第一鈍化層114可藉由如化學氣相沉積(chemical vapor deposition)等製程形成,雖然也可使用其他適合的製程,且第一鈍化層114可具有介於0.5μm至5μm的一厚度,例如約0.925μm。
第一接觸墊115可形成於第一金屬化層113上並且與之電性接觸以提供第一半導體裝置晶片103、第二半導體裝
置晶片105以及第三半導體裝置晶片107外部連結。第一接觸墊115由導電材料形成,例如鋁,雖然也可以使用其他適合的材料,例如銅、鎢或與其相似的材料。第一接觸墊115可藉由如化學氣相沉積等製程形成,雖然也可使用其他適合的材料或方法。一旦沉積第一接觸墊115的材料,可使用光微影遮罩以及蝕刻製程,將此材料圖案化為第一接觸墊115之形狀。
在一實施例中,形成第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107於第一晶圓101中,並且被沿著第一晶圓101的切割道(由第1圖的標號117之虛線所示)分隔開而分離以形成單獨的第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107。切割道117是藉由不要放置功能性的結構(例如主動裝置)進入預定要用做切割道117的區域來形成。其他結構(例如,測試墊,或用於平坦化的虛置金屬)可放置進入切割道117中,然而一旦第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107彼此分離,這些結構將對第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107不具功能性。切割道117可形成且具有介於10μm至200μm的一第一寬度W1,例如約80μm。
第2圖繪示一光阻201放置於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107上。在一實施例中,光阻201係一感光性材料且可使用例如一旋轉塗佈技術形成光阻201而放置於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107上,光阻201
具有介於0.5μm至15μm的一高度,例如5μm。一旦放置好,光阻201可接著藉由暴露至一圖案化能量源(例如,圖案化光源)進行圖案化以誘發一化學反應,進而導致暴露在圖案化光源的光阻201的部分發生一物理變化。接著根據需要的圖案,使用一顯影液(devoloper)於曝光的光阻201以利用其物理變化且選擇性移除光阻201曝光的部分或是未曝光的部分。
在一實施例中圖案化光阻201以形成第一開口203,其暴露出切割道117。因此的第一開口203可形成以具有切割道117的第一寬度W1,其可以是介於10μm至150μm,例如約80μm。然而,也可使用其他適合的寬度。
第3圖繪示,一旦將光阻201於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107放置好,並圖案化後,可實施一第一蝕刻製程(如第3圖中標號301的箭號所示),使第一開口203延伸穿過第一鈍化層114、第一金屬化層113、第一主動裝置層111,且進入第一基板109。在一實施例中第一蝕刻製程可以是一或多個反應性離子蝕刻製程,其使用一或多個蝕刻劑進行方向性蝕刻以穿過第一金屬化層113、第一主動裝置層111,且進入第一基板109。
如此,雖然所使用的特定蝕刻劑及製程條件至少部份是取決於每個膜層選定的材料,但在一實施例中,第一基板109是矽,當第一蝕刻製程301進行蝕刻第一基板109時,可使用一蝕刻劑例如含氟化學物(F-chemicals)或氧氣(O2),與一載體氣體如氬氣,雖然也可使用任何適合的蝕刻劑。
此外,用於反應性離子蝕刻的射頻功率(PF power)
可設定為介於100W至4000W,例如約1500W,以及偏壓功率可設定為介於10V至500V,例如約200V。最後,蝕刻腔體的壓力可設定為介於10mTorr至200mTorr,例如約90mTorr,以及製程的溫度可控制在介於-20℃至50℃,例如約0℃。然而,這些條件係用以說明,可使用任何適合的蝕刻條件,並且所有的製程條件都完全包含於實施例的範疇內。
在一實施例中可使用第一蝕刻製程301使第一開口203至少部份延伸進入第一基板109。舉例來說,可使用第一蝕刻製程301使第一開口203延伸進入第一基板109至一第一深度D1,其介於5μm至100μm,例如約30μm。然而可使用任何其他適合的深度。
然而,當使用上述的乾蝕刻製程以將第一基板109圖案化,此敘述只是用以描述而非用以限定此實施例。舉例來說,一濕蝕刻製程可形成一曲面的側壁,在第一晶圓101浸於一液體蝕刻劑中,例如可使用氟化氫基底(HF-based)溶液或氫氧化四甲基胺(Tetramethylammonium hydroxide,TMAH),在介於室溫至80℃的溫度於介於1分鐘至30分鐘的時間。可使用任何適合的方法圖案化第一基板109,且所有此種的製程條件都被視為完全包含於實施例的範疇內。
第4A圖繪示光阻201的移除以及後移除清潔製程。在一實施例中可使用例如一灰化(ashing)製程,藉由提升光阻201的溫度直到光阻201產生一熱裂解並且使之容易移除。然而,可使用任何適合的移除製程。
實施灰化製程後,可使用一第一清潔製程以清潔
該結構,以幫助光阻201的移除。在一實施例中第一清潔製程可包括將第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107浸入一蝕刻劑以確保在接下來的製程前任何光阻201的餘下部份可自第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107上移除。舉例來說,可使第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107浸入一蝕刻劑如氟化氫介於1秒至100秒,例如約60秒。
第4B圖繪示如第4A圖繪示之實施例的俯視圖。在此實施例中繪示的切割道117位於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107之間。然而,如俯視圖中可見,可使用第一蝕刻製程301(於第3圖所示)以於每個第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107形成圓化角落(如第4B圖以標號401之虛線的圓所示)。特別是,在此實施例中,第一半導體裝置晶片103可具有介於1mm至30mm的一第二寬度W2,例如約4mm,以及具有介於1mm至30mm的一第一長度L1,例如約4mm,而曲狀角落可具有介於50μm至500μm的一弧半徑R1,例如約250μm。然而,可使用任何適合的弧半徑。
藉由使用第一蝕刻製程301以在第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107的角落形成圓化角落,使得第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107於切割製程中較能抵抗伴隨而來的應力(於第6圖中加以描述)。特別是,圓
化角落401可分散以及抵抗鋸片的物理切割的應力並使第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107分離。如此,在切割製程中會產生較少的缺陷。
第5圖繪示設置一保護薄膜501於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107上以及薄化第一基板109的背側。在一實施例中保護薄膜501可為一背部研磨膠帶(backgrindnig tape,BG tape),其可用來保護第一基板109的圖案化側邊於第一基板的薄化時免於研磨碎屑(grinding debris)的傷害。可藉由例如,一滾柱(roller),將保護薄膜501設置於第一開口204上(未分開繪示於第5圖)。
然而,雖然上述的保護薄膜501作為一背部研磨膠帶,此敘述只是用以描述而非用以限定此實施例。反之,可以使用任何適合的方法保護第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107的圖案化表面,包括第一開口203。所有的保護層膜都完全包含於實施例的範疇內。
第一開口203被保護後,使用一第一薄化製程(如第5圖中標號501之旋轉平台所表示)薄化第一基板109。在一實施例中可使用一化學機械研磨(chemical mechanical polishing)製程以薄化第一晶圓101,藉由化學反應物與研磨料的組合以及一或多個研磨墊以移除部分的第一基板109相對於第一接觸墊115的部分。然而,可使用任何適合的製程,例如一物理研磨(physical grinding)製程、一或多個蝕刻製程、其組合或與其相似的製程。在一實施例中薄化第一晶圓101以在薄化後具有介
於100μm至500μm的一第一厚度T1,例如約200μm。
第6圖繪示第一晶圓101的一切割製程進入第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107。在一實施例中切割製程前最初先移除保護薄膜501,且將第一晶圓101貼附於一支撐基板601。支撐基板601可為一膠帶,例如熟知的藍膠帶,且用以控制第一晶圓101的放置位置。如此,雖然支撐基板601在此可視為一膠帶,支撐基板601並不限於膠帶,且可以是任何其他的媒介,例如一承載晶圓、一承載玻璃、一金屬平板或一陶瓷平板,其可提供第一晶圓101的放置所需。
貼附於支撐基板601後,可藉由一鋸片(如第6圖中標號603的虛線方框所示)實施切割製程以切割並穿過切割道117以形成第二開口605,其穿過位於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107之間的第一基板109。
在一實施例中,使用鋸片603來切割位於第一半導體裝置晶片103與第二半導體裝置晶片105之間以及於第二半導體裝置晶片105與第三半導體裝置晶片107之間的第一基板109,而並未從第一開口203的側壁移除多餘的材料。如此,第二開口605可形成具有小於第一寬度W1的一第三寬度W3,例如介於10μm至300μm,例如約50μm。然而,第三寬度W3可以使用任何適合的尺寸。因此,第一基板延伸部607餘留於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107上。
此外,本技術領域具通常知識者可知,使用一鋸片切割第一晶圓101僅是一繪示的實施例,且並不限於此。切割第一晶圓101的替代方法,例如可使用一或多個蝕刻以將第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107分離。可使用這些方法及任何其他適合的方法以切割第一晶圓101。
第7圖繪示將第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107以晶片堆疊晶圓(chip on wafer,CoW)的接合製程的方式接合至一第二晶圓701。第二晶圓701可包括一第二基板703、一第二主動裝置層705、第二金屬化層707、第二鈍化層708以及第二接觸墊709,分別類似於第一基板109、第一主動裝置層111、第一金屬化層113、第一鈍化層114以及第一接觸墊115。第二基板703、第二主動裝置層705、第二金屬化層707、第二鈍化層708以及第二接觸墊709可形成一第四半導體裝置晶片711、一第五半導體裝置晶片713以及一第六半導體裝置晶片715(由第二切割道717分開),其可以各自與第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107一同操作。
第一半導體裝置晶片103可使用例如一熔融接合(fusion bonding)製程接合至第二晶圓701。在一實施例中,熔融接合製程可藉由於第二晶圓701需要接合處上實施一初始清潔(initial cleaning)製程而開始。在一特別實施例中,可於第二晶圓701實施一濕清潔程序(wet clean procedure)如SC-1或SC-2清潔程序以形成一親水表面。進行清潔後,第一半導體裝置晶
片103、第二半導體裝置晶片105以及第三半導體裝置晶片107對準至第二晶圓701上各自與第二晶圓701所需之部份對準,以及第二晶圓701的親水表面與第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107進行物理接觸以開始接合程序。第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107接觸至第二晶圓701後,使用一熱退火以加強接合。
然而,上述的熔融接合僅是製程中一個類型的例示,其用來使第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107接合至第二晶圓701,並非用以限定本實施例。反之,可使用任何適合的接合製程將第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107接合至第二晶圓701,且所有的製程都完全包含於實施例的範疇內。
第8圖繪示在第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107接合至第二晶圓701後,使用一第二薄化製程(如第8圖中標號801的旋轉平台所示)以自第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107移除第一基板延伸部607。在一實施例中第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107的薄化可使用例如一化學機械研磨,藉由化學反應物與研磨料及一或多個研磨墊的組合以移除第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107相對於第一接觸墊115的部份。然而,可使用任何
適合的製程,例如一物理研磨製程、一或多個蝕刻製程、其組合或與其相似的製程。在一實施例中第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107薄化至一厚度以足夠移除第一基板延伸部607,例如薄化至介於10μm至250μm的一厚度T2,例如約25μm。然而,可使用任何適合的厚度。
藉由使用第一蝕刻製程以圖案化切割道117以切割第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107,在切割製程產生的應力將會得到較佳的釋放,且任何切片導致的碎屑也會最小化。如此,將於第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107之間得到較佳的界面。如此,可達到較佳的一晶粒-晶圓熔融接合,導致具有較少缺陷的較強接合。
第一半導體裝置晶片103、第二半導體裝置晶片105以及第三半導體裝置晶片107接合至第二晶圓701且進行薄化後,可於第二晶圓701上實施額外的製程。舉例來說,可切割第二晶圓701以形成可使用的半導體裝置。
根據本揭露一實施例,一種半導體裝置之製造方法,包括形成一第一開口於第一半導體晶圓內且位於一第一半導體晶粒與一第二半導體晶粒之間,第一開口具有一第一寬度,其平行於第一半導體晶圓的一主要表面。切割第一半導體晶圓以形成一第二開口,其中第一開口與第二開口將第一半導體晶粒與第二半導體晶粒分離,第二開口具有一第二寬度,其平行於第一半導體晶圓的主要表面且小於第一寬度。薄化第一半導
體晶粒直到半導體晶粒具有筆直的一側壁。
根據本揭露另一實施例,一種半導體裝置之製造方法包括至少一第一半導體晶粒以及一第二半導體晶粒之部分形成於一半導體基板中。移除半導體基板的一第一部分,其中第一部分位於半導體基板的一切割區域中。使用一鋸片移除半導體基板的一第二部分,其中半導體基板的第一部分的移除以及半導體基板的第二部分的移除將第一半導體晶粒與第二半導體晶粒分離並且形成第一半導體晶粒上的複數半導體材料延伸部。
根據本揭露又另一實施例,一種半導體裝置之製造方法包括形成一第一開口於一第一半導體晶圓中,第一開口位於一第一半導體晶粒與一第二半導體晶粒之間,其中第一開口的形成至少部分是藉由一蝕刻製程實施。形成一第二開口於第一半導體晶圓中,第二開口位於第一半導體晶粒與第二半導體晶粒之間,其中第二開口的形成至少部分是藉由一切割製程實施且其中第二開口具有一寬度小於第一開口並且第一開口及第二開口將第一半導體晶粒自第二半導體晶粒切割。接合第一半導體晶粒以及第二半導體晶粒至一第二半導體晶圓。在接合第一半導體晶粒以及第二半導體晶粒後,薄化第一半導體晶粒以及第二半導體晶粒,其中第一半導體晶粒以及第二半導體晶粒的薄化自第一半導體晶粒以及第二半導體晶粒移除複數延伸區域。
以上概略說明了本揭露數個實施例的特徵部件,使所屬技術領域中具有通常知識者對於後續本揭露的詳細說
明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到本說明書可輕易作為其它結構或製程的變更或設計基礎,以進行相同於本揭露實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本揭露之精神和保護範圍內,且可在不脫離本揭露之精神和範圍內,當可作更動、替代與潤飾。
101‧‧‧第一晶圓
103‧‧‧第一半導體裝置晶片
105‧‧‧第二半導體裝置晶片
107‧‧‧第三半導體裝置晶片
109‧‧‧第一基板
111‧‧‧第一主動裝置層
113‧‧‧第一金屬化層
114‧‧‧第一鈍化層
115‧‧‧第一接觸墊
203‧‧‧第一開口
601‧‧‧支撐基板
603‧‧‧虛線方框/鋸片
605‧‧‧第二開口
607‧‧‧第一基板延伸部
W3‧‧‧第三寬度
Claims (12)
- 一種半導體裝置之製造方法,包括:形成一第一開口於第一半導體晶圓內,且該第一開口位於一第一半導體晶粒與一第二半導體晶粒之間,該第一開口具有一第一寬度,其平行於該第一半導體晶圓的一主要表面;切割該第一半導體晶圓以形成一第二開口,其中該第一開口與該第二開口將該第一半導體晶粒與該第二半導體晶粒分離,該第二開口具有一第二寬度,其平行於該第一半導體晶圓的該主要表面且小於該第一寬度;以及薄化該第一半導體晶粒直到該半導體晶粒具有筆直的一側壁。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,更包括在薄化該第一半導體晶粒前,接合該第一半導體晶粒至一半導體基板上,以及在薄化該第二半導體晶粒前,接合該第二半導體晶粒至該半導體基板上。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該第一半導體晶粒的薄化至少一部份是使用一化學機械研磨製程實施。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該第一半導體晶粒的薄化移除該第一半導體晶粒上的延伸區域。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該第一開口的形成也圓化該第一半導體晶粒的一角落。
- 如申請專利範圍第1項所述之半導體裝置之製造方法,其中該第一開口的形成至少部份使用一乾蝕刻製程。
- 一種半導體裝置之製造方法,包括:形成一第一半導體晶粒以及一第二半導體晶粒之至少部分於一半導體基板中;移除該半導體基板的一第一部分,其中該第一部分位於該半導體基板的一切割區域中;以及使用一鋸片移除該半導體基板的一第二部分,其中該半導體基板的該第一部分的移除以及該半導體基板的該第二部分的移除將該第一半導體晶粒與該第二半導體晶粒分離並且形成該第一半導體晶粒上的複數半導體材料延伸部。
- 如申請專利範圍第7項所述之半導體裝置之製造方法,更包括自該第一半導體晶粒移除該等半導體材料延伸部,其中該半導體材料延伸部的移除包括於該第一半導體晶粒上實施一薄化製程。
- 如申請專利範圍第7項所述之半導體裝置之製造方法,其中移除該半導體基板的該第一部分更包括:形成一遮罩於該第一半導體晶粒上;以及實施一乾蝕刻製程經由該遮罩以移除該半導體基底的該第一部分。
- 如申請專利範圍第7項所述之半導體裝置之製造方法,其中該第一部分的移除形成一側壁於半導體基板上,該側壁至少部分是曲面的。
- 一種半導體裝置之製造方法,包括: 形成一第一開口於一第一半導體晶圓中,該第一開口位於一第一半導體晶粒與一第二半導體晶粒之間,其中第一開口的形成至少部分是藉由一蝕刻製程實施;形成一第二開口於該第一半導體晶圓中,該第二開口位於該第一半導體晶粒與該第二半導體晶粒之間,其中該第二開口的形成至少部分是藉由一切割製程實施且其中該第二開口具有一寬度小於該第一開口並且該第一開口及該第二開口將該第一半導體晶粒自該第二半導體晶粒切割;接合該第一半導體晶粒以及該第二半導體晶粒至一第二半導體晶圓;以及在接合該第一半導體晶粒以及該第二半導體晶粒後,薄化該第一半導體晶粒以及該第二半導體晶粒,其中該第一半導體晶粒以及該第二半導體晶粒的薄化自該第一半導體晶粒以及該第二半導體晶粒移除複數延伸區域。
- 如申請專利範圍第11項所述之半導體裝置之製造方法,更包括在形成該第一開口後以及在形成該第二開口前,薄化該第一半導體晶粒以及該第二半導體晶粒,其中在形成該第一開口後以及在形成該第二開口前,該第一半導體晶粒以及該第二半導體晶粒的薄化至少部分是使用一化學機械製程。
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