CN105474354B - 半导体基板的制造方法 - Google Patents

半导体基板的制造方法 Download PDF

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Publication number
CN105474354B
CN105474354B CN201480038163.7A CN201480038163A CN105474354B CN 105474354 B CN105474354 B CN 105474354B CN 201480038163 A CN201480038163 A CN 201480038163A CN 105474354 B CN105474354 B CN 105474354B
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China
Prior art keywords
layer
amorphous layer
amorphous
substrate
single crystal
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CN201480038163.7A
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Chinese (zh)
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CN105474354A (zh
Inventor
今冈功
小林元树
内田英次
八木邦明
河原孝光
八田直记
南章行
坂田丰和
牧野友厚
高木秀树
仓岛优
仓岛优一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
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Toyota Industries Corp
National Institute of Advanced Industrial Science and Technology AIST
Sicoxs Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/126Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates characterised by the composition of the bonding layer, e.g. dopant concentration or stoichiometry
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
CN201480038163.7A 2013-07-05 2014-07-03 半导体基板的制造方法 Active CN105474354B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013-142151 2013-07-05
JP2013142151A JP6061251B2 (ja) 2013-07-05 2013-07-05 半導体基板の製造方法
PCT/JP2014/067777 WO2015002266A1 (ja) 2013-07-05 2014-07-03 半導体基板の製造方法

Publications (2)

Publication Number Publication Date
CN105474354A CN105474354A (zh) 2016-04-06
CN105474354B true CN105474354B (zh) 2018-04-17

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CN201480038163.7A Active CN105474354B (zh) 2013-07-05 2014-07-03 半导体基板的制造方法

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US (1) US9761479B2 (enExample)
EP (1) EP3018696B8 (enExample)
JP (1) JP6061251B2 (enExample)
KR (1) KR101846299B1 (enExample)
CN (1) CN105474354B (enExample)
WO (1) WO2015002266A1 (enExample)

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JP6515757B2 (ja) 2015-09-15 2019-05-22 信越化学工業株式会社 SiC複合基板の製造方法
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CN107958839B (zh) * 2016-10-18 2020-09-29 上海新昇半导体科技有限公司 晶圆键合方法及其键合装置
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JP2019210161A (ja) * 2018-05-31 2019-12-12 ローム株式会社 半導体基板構造体及びパワー半導体装置
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CN109986191A (zh) * 2019-04-15 2019-07-09 上海交通大学 一种应用于金属/高分子连接的表面处理方法
JP6737378B2 (ja) * 2019-05-09 2020-08-05 信越化学工業株式会社 SiC複合基板
JP6955302B2 (ja) * 2019-06-18 2021-10-27 大学共同利用機関法人自然科学研究機構 光学素子の製造方法及び光学素子
KR20230004728A (ko) 2020-06-01 2023-01-06 미쓰비시덴키 가부시키가이샤 복합 기판, 복합 기판의 제조 방법, 반도체 장치 및 반도체 장치의 제조 방법
JP7625248B2 (ja) * 2021-01-20 2025-02-03 国立研究開発法人理化学研究所 接合体の製造方法および接合体
JP2023061509A (ja) 2021-10-20 2023-05-02 株式会社サイコックス 多結晶炭化珪素基板の製造方法
JP2023068782A (ja) * 2021-11-04 2023-05-18 株式会社サイコックス 半導体基板とその製造方法
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JP2023178892A (ja) * 2022-06-06 2023-12-18 株式会社サイコックス 陰極、高速原子ビーム線源、接合基板の製造方法、および、陰極の再生方法
JP2024025064A (ja) 2022-08-10 2024-02-26 株式会社サイコックス SiC単結晶転写用複合基板、SiC単結晶転写用複合基板の製造方法、およびSiC接合基板の製造方法
JP2024073797A (ja) 2022-11-18 2024-05-30 株式会社サイコックス 研磨組成物
FR3146237A1 (fr) 2023-02-24 2024-08-30 Mersen France Gennevilliers Plaque en SiC polycristallin dopé à planéité et conductivité électrique améliorées, et procédé de fabrication d’une telle plaque
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Also Published As

Publication number Publication date
EP3018696A4 (en) 2017-03-15
JP2015015401A (ja) 2015-01-22
US20160204023A1 (en) 2016-07-14
KR101846299B1 (ko) 2018-05-18
EP3018696B1 (en) 2021-11-17
KR20160040565A (ko) 2016-04-14
JP6061251B2 (ja) 2017-01-18
WO2015002266A1 (ja) 2015-01-08
EP3018696A1 (en) 2016-05-11
US9761479B2 (en) 2017-09-12
CN105474354A (zh) 2016-04-06
EP3018696B8 (en) 2022-02-23

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