CN105428366B - 薄膜晶体管阵列基板、其制造方法和显示装置 - Google Patents

薄膜晶体管阵列基板、其制造方法和显示装置 Download PDF

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CN105428366B
CN105428366B CN201510585342.9A CN201510585342A CN105428366B CN 105428366 B CN105428366 B CN 105428366B CN 201510585342 A CN201510585342 A CN 201510585342A CN 105428366 B CN105428366 B CN 105428366B
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electrode
source
layer
drain
gate electrode
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CN105428366A (zh
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金广海
金容周
李旻炯
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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  • Thin Film Transistor (AREA)

Abstract

公开了薄膜晶体管阵列基板、其制造方法和显示装置。所述薄膜晶体管(TFT)阵列基板包括至少一个TFT，所述至少一个TFT包括：半导体层，包括在基板上且具有第一掺杂浓度的源极区和漏极区、在源极区和漏极区之间且具有第二掺杂浓度的沟道区以及从源极区和漏极区延伸的非掺杂区，第二掺杂浓度低于第一掺杂浓度；栅极绝缘层，在半导体层上；栅电极，在栅极绝缘层上并且与沟道区至少部分叠置；源电极和漏电极，与栅电极绝缘并且分别电连接到源极区和漏极区。

Description

薄膜晶体管阵列基板、其制造方法和显示装置
通过引用将于2014年9月15日在韩国知识产权局提交的并且名称为“Thin-FilmTransistor Array Substrate,Method of Manufacturing the Same,and DisplayDevice(薄膜晶体管阵列基板、其制造方法和显示装置)”的第10-2014-0122043号韩国专利申请的全部内容包含于此。
技术领域
一个或更多个示例性实施例涉及薄膜晶体管(TFT)阵列基板、其制造方法和采用TFT阵列基板的显示装置。
背景技术
诸如有机发光显示设备或液晶显示设备的平板显示设备可包括薄膜晶体管(TFT)、电容器和连接TFT和电容器的布线。
发明内容
实施例可通过提供一种薄膜晶体管(TFT)阵列基板来实现，所述TFT阵列基板包括至少一个TFT，所述至少一个TFT包括：半导体层，包括在基板上且具有第一掺杂浓度的源极区和漏极区、在源极区和漏极区之间且具有第二掺杂浓度的沟道区以及从源极区和漏极区延伸的非掺杂区，第二掺杂浓度低于第一掺杂浓度；栅极绝缘层，在半导体层上；栅电极，在栅极绝缘层上并且与沟道区至少部分叠置；源电极和漏电极，与栅电极绝缘并且分别电连接到源极区和漏极区。
TFT阵列基板还可包括电容器，所述电容器包括：下电极，在非掺杂区延伸的半导体层上；上电极，与下电极绝缘并且与下电极至少部分叠置。
栅电极的厚度可比下电极的厚度薄。
下电极可包括第一电极层和第二电极层，第一电极层可由与栅电极相同的材料形成。
第一电极层的厚度可比第二电极层的厚度薄，栅电极的厚度可与第一电极层的厚度相同。
上电极可包括与源电极或漏电极相同的材料。
栅电极可包括透明导电材料。
栅电极的厚度可以是大约
Figure BDA0000802654920000021
至大约
Figure BDA0000802654920000022
TFT阵列基板还可包括平坦化膜，所述平坦化膜覆盖TFT并且包括部分暴露源电极或漏电极的开口。
所述TFT阵列基板还可包括焊盘电极，焊盘电极包括与源电极和漏电极相同的材料并且电连接到TFT以将电流传输到TFT。
实施例可通过提供一种显示设备来实现，所述显示设备包括：目前公开的薄膜晶体管(TFT)阵列基板；像素电极，电连接到源电极和漏电极；对电极，面对像素电极。中间层可位于像素电极和对电极之间，并且可包括有机发射层或液晶层。
实施例可通过提供一种制造薄膜晶体管(TFT)阵列基板的方法来实现，所述方法包括：在基板的整个表面上形成非掺杂半导体层；在非掺杂半导体层上形成栅极绝缘层；在栅极绝缘层上形成TFT的预备-栅电极和电容器的下电极；形成层间绝缘层，所述层间绝缘层覆盖下电极并且具有暴露将变成TFT的沟道区和源极-漏极区的部分的开口；通过在非掺杂半导体层中形成源极-漏极区来执行第一掺杂工艺；形成连接到源极-漏极区的源电极和漏电极以及与下电极叠置的上电极；通过在非掺杂半导体层上形成沟道区来执行第二掺杂工艺。
执行第一掺杂工艺的步骤可包括使用预备-栅电极和层间绝缘层作为掩模来注入掺杂剂。
预备-栅电极可包括栅电极和位于栅电极上的上栅电极，所述方法还可包括在执行第二掺杂工艺之前去除上栅电极，第二掺杂工艺可包括使用源电极和漏电极作为掩模来注入掺杂剂。
在第二掺杂工艺期间注入的掺杂剂可通过栅电极被掺杂在非掺杂半导体层上。
上栅电极可包括与源电极和漏电极相同的材料，可在形成源电极和漏电极的同时执行去除上栅电极的步骤。
栅电极可包括透明导电材料，并且栅电极的厚度可以是大约
Figure BDA0000802654920000023
至大约
Figure BDA0000802654920000024
源极-漏极区的掺杂浓度可高于沟道区的掺杂浓度。
栅极绝缘层可包括暴露源极-漏极区的一部分的接触孔，可在半色调掩模工艺期间与层间绝缘层的开口同时地形成接触孔。
所述方法还可包括形成平坦化膜，所述平坦化膜覆盖源电极、漏电极和上电极，并且包括暴露源电极或漏电极的一部分的开口。
附图说明
通过参照附图详细描述示例性实施例，特征对于本领域技术人员而言将变得明显，在附图中：
图1示出根据示例性实施例的薄膜晶体管(TFT)阵列基板的剖视图；
图2示出根据示例性实施例的TFT阵列基板的剖视图；
图3A至图3F示出用于描述根据示例性实施例的制造TFT阵列基板的方法的剖视图；以及
图4至图6示出根据示例性实施例的应用TFT阵列基板的显示设备的剖视图。
具体实施方式
现在，在下文中将参照附图更充分地描述示例实施例；然而，这些实施例可以不同的形式实施并且不应该被解释为局限于在此阐述的实施例。相反地，提供这些实施例使得本公开将是彻底的和完整的，并且将把示例性实施方式充分地传达给本领域技术人员。
在附图中，同样的附图标记始终指示同样的元件并且将不重复重叠的描述。
将理解的是，尽管这里可使用术语“第一”、“第二”等来描述各种组件，但是这些组件不应受这些术语限制。这些术语仅用于将一个组件与另一个组件区分开。
如在此使用的，单数形式“一个”、“一种(者)”和“该(所述)”也旨在包括复数形式，除非上下文另行清楚指示。
还将理解的是，这里使用的术语“包括”和/或其变型指明存在叙述的特征或组件，但不排除存在或添加一个或更多个其它特征或组件。
将理解的是，当层、区域或组件被称为“形成在”另一层、区域或组件“上”时，它可直接地或间接地形成在所述另一层、区域或组件上。即，例如，可存在中间层、区域或组件。此外，将理解的是，当层被称为“在”另一层“下方”时，它可直接在其下方，并且还可存在一个或更多个中间层。另外，还将理解的是，当层被称为“在”两个层“之间”时，它可以是这两个层之间的唯一层，或者还可存在一个或更多个中间层。
为了解释方便，可夸大附图中的元件的大小(例如，层和区域的尺寸)。换句话讲，由于为了解释方便而任意示出附图中的组件的尺寸和厚度，因此下面的实施例不限于此。
当特定实施例可不同地实施时，可按与所描述的次序不同的方式执行特定工艺次序。例如，两个连续描述的工艺可基本同时地执行或者以与所描述的次序相反的次序执行。
如这里使用的，术语“和/或”包括一个或更多个相关所列项的任何和全部组合。
图1示出根据示例性实施例的薄膜晶体管(TFT)阵列基板100的剖视图。
TFT阵列基板100可包括规则布置或不规则布置的多个TFT，或者可仅包括一个TFT。
参照图1，TFT阵列基板100可包括至少一个TFT，其中，TFT包括半导体层120、栅极绝缘层130、栅电极141a、源电极161a和漏电极161b。
半导体层120可包括：源极区123a和漏极区123b，具有第一掺杂浓度；沟道区121，设置在源极区123a和漏极区123b之间并且具有第二掺杂浓度；非掺杂区125，从源极区123a和漏极区123b延伸。第二掺杂浓度可低于第一掺杂浓度。在一些实施例中，第二掺杂浓度可比第一掺杂浓度低102至104倍。在一些实施例中，第二掺杂浓度可以是大约1E12/cm3至大约5E12/cm3，第一掺杂浓度可以是大约1E15/cm3至大约5E15/cm3。
可掺杂沟道区121以调节TFT的阈值电压，并且沟道区121和源极-漏极区123的电导率可彼此相同或不同。例如，源极-漏极区123可以是p型半导体，沟道区121可以是n型半导体。在实施例中，源极-漏极区123和沟道区121可具有相同的电导率，但具有不同的掺杂浓度。
TFT阵列基板100还可包括电容器CAP，电容器CAP包括与栅电极141a形成在同一层上的下电极142和与下电极142绝缘的上电极162。
TFT阵列基板100还可包括层间绝缘膜150和/或平坦化膜170。
基板110可由玻璃材料、塑料材料或金属材料形成。基板110可以是柔性基板。缓冲层(未示出)可形成在基板110上。缓冲层可在基板110上提供平坦的表面，且可包含绝缘材料，并且可阻挡外部湿气和外部杂质穿过基板110。在实施例中，可不包括缓冲层。
TFT可设置在基板110上。TFT可包括半导体层120、栅电极141a、源电极161a和漏电极161b。
半导体层120可由包括非晶硅或结晶硅的半导体形成，并且可包括具有第一掺杂浓度的源极区123a和漏极区123b以及设置在源极区123a和漏极区123b之间并且具有第二掺杂浓度的沟道区121。在下文中，源极区123a和漏极区123b可被统称为源极-漏极区123。源极-漏极区123包括源极区123a和漏极区123b。源极-漏极区123和沟道区121可基于是否添加掺杂剂而具有导电性。例如，如果添加诸如硼(B)的三价掺杂剂，则可表现出p型导电性，如果添加诸如磷(P)、砷(As)或锑(Sb)的五价掺杂剂，则可表现出n型导电性。
半导体层120可包括从源极-漏极区123延伸的非掺杂区125。非掺杂区125是未掺杂的区域，并且可围绕沟道区121和源极-漏极区123。非掺杂区125可以是绝缘的，并且TFT可与其它相邻组件电绝缘。层间绝缘膜150可对应地设置在非掺杂区125上方。
半导体层120可形成在基板110的整个表面上，并且可不经由单独的掩模工艺进行图案化。因此，可减少掩模的数量，可实现降低成本并且简化制造工艺。
栅电极141a可在与半导体层120的沟道区121对应的位置处设置在半导体层120上，其中，栅极绝缘层130设置在半导体层120和栅电极141a之间。
栅极绝缘层130可设置在半导体层120上，并且可包括分别暴露源极区123a和漏极区123b的第一接触孔130a和第二接触孔130b。栅极绝缘层130可包括绝缘材料，半导体层120和栅电极141a可彼此电分离。在一些实施例中，栅极绝缘层130可具有无机材料和有机材料的单层或堆叠结构。在一些实施例中，栅极绝缘层130可包括氮化硅(SiNx)和/或氧化硅(SiOx)。
栅电极141a可由一定材料形成并且可具有一定厚度，使得用于掺杂沟道区121的掺杂剂可穿过栅电极141a。在一些实施例中，栅电极141a可由透明导电材料形成。例如，栅电极141a可由氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化铟(In2O3)形成。
栅电极141a可与电容器CAP的下电极142形成在同一层上。栅电极141a的厚度可比下电极142的厚度薄。在一些实施例中，栅电极141a的厚度可以是大约
Figure BDA0000802654920000061
至大约
Figure BDA0000802654920000062
在实施例中，可基于掺杂在沟道区121上的掺杂剂的浓度和注入速度来确定栅电极141a的厚度。
在栅极绝缘层130上，源电极161a和漏电极161b可与栅电极141a分隔开。还可在源电极161a、漏电极161b与栅极绝缘层130之间设置层间绝缘膜150。源电极161a可通过栅极绝缘层130的第一接触孔130a连接到源极区123a。漏电极161b可通过栅极绝缘层130的第二接触孔130b连接到漏极区123b。
可使用相同材料同时形成源电极161a和漏电极161b。源电极161a和/或漏电极161b可同时由与电容器CAP的上电极162相同的材料形成。源电极161a和漏电极161b可包括铝(Al)、钼(Mo)、钛(Ti)或铜(Cu)。在一些实施例中，源电极161a和漏电极161b可具有Ti/Cu、Mo/Al/Mo、Mo/AlGe/Mo或Ti/Al/Ti的堆叠结构。在一些实施例中，源电极161a和漏电极161b的厚度可以均为至少
Figure BDA0000802654920000063
电容器CAP可包括下电极142和上电极162，下电极142设置在TFT的非掺杂区125延伸的半导体层120上，上电极162与下电极142绝缘并且与下电极142至少部分叠置。
下电极142可与栅电极141a形成在同一层上，并且可比栅电极141a厚。在一些实施例中，下电极142可包括第一电极层142a和第二电极层142b。第一电极层142a可同时由与栅电极141a相同的材料形成。第一电极层142a可与栅电极141a具有基本上相同的厚度。第一电极层142a可由透明导电材料形成。例如，第一电极层142a可由ITO、IZO、ZnO或In2O3形成。
第二电极层142b可比第一电极层142a厚。第二电极层142b可由与源电极161a或漏电极161b相同的材料形成。第二电极层142b可包括Al、Mo、Ti或Cu。在一些实施例中，第二电极层142b可具有Ti/Cu、Mo/Al/Mo、Mo/AlGe/Mo或Ti/Al/Ti的堆叠结构。
上电极162可通过层间绝缘膜150与下电极142绝缘，并且上电极162可被设置成与下电极142至少部分叠置。上电极162可由与源电极161a或漏电极161b相同的材料形成。上电极162可包括Al、Mo、Ti或Cu。在一些实施例中，上电极162可具有Ti/Cu、Mo/Al/Mo、Mo/AlGe/Mo或Ti/Al/Ti的堆叠结构。
层间绝缘膜150可设置在下电极142和上电极162之间，并且可对作为用于确定电容器CAP的电容的介电材料进行操作。层间绝缘膜150可由各种绝缘材料中的任一种形成。例如，层间绝缘膜150可由诸如氧化物或氮化物的无机材料或者有机材料形成。在一些实施例中，层间绝缘膜150可具有有机材料和无机材料的单层或堆叠结构。层间绝缘膜150可与半导体层120的非掺杂区125对应地形成。层间绝缘膜150可作为掩模操作，在随后描述的第一掺杂工艺和第二掺杂工艺期间，该掩模防止掺杂剂被注入到非掺杂区125。
平坦化膜170可设置在TFT和/或电容器CAP上。平坦化膜170可由绝缘材料形成，并且可具有无机材料、有机材料或无机/有机化合物的单层或多层。在一些实施例中，平坦化膜170可由有机材料形成。当平坦化膜170由有机材料形成时，平坦化膜170可比当其由无机材料形成时厚，并且可防止寄生电容。在一些实施例中，平坦化膜170可具有大约3μm至大约5μm的厚度并且由于诸如聚丙烯酸酯、聚酰亚胺或苯并环丁烯(BCB)的材料涂覆在其上而具有平坦表面。平坦化膜170可包括暴露源电极161a或漏电极161b的一部分的第一开口170a。TFT可通过第一开口170a电连接到另一装置或布线。
图2示出根据示例性实施例的TFT阵列基板200的剖视图。在图1和图2中，同样的附图标记表示同样的元件，并且不提供重叠的细节。参照图2，TFT阵列基板200可包括至少一个TFT，其中，TFT包括半导体层120、栅极绝缘层130、栅电极141a、源电极161a和漏电极161b。
半导体层120可包括：源极区123a和漏极区123b，具有第一掺杂浓度；沟道区121，设置在源极区123a和漏极区123b之间；非掺杂区125，从源极区123a和漏极区123b延伸。沟道区121与源极区123a和漏极区123b的掺杂浓度和掺杂类型中的至少一个可彼此不同。第二掺杂浓度可不同于第一掺杂浓度，沟道区121和源极-漏极区123可具有不同的电导率。例如，源极-漏极区123可以是p型半导体，沟道区121可以是n型半导体。在实施例中，源极-漏极区123和沟道区121可具有相同的电导率，但具有不同的掺杂浓度。
在一些实施例中，第二掺杂浓度可低于第一掺杂浓度。在一些实施例中，第二掺杂浓度可比第一掺杂浓度低102至104倍。在一些实施例中，第二掺杂浓度可以是大约1E12/cm3至大约5E12/cm3，第一掺杂浓度可以是大约1E15/cm3至大约5E15/cm3。
TFT阵列基板200还可包括电容器CAP，电容器CAP包括与栅电极141a形成在同一层上的下电极142和与下电极142绝缘的上电极162。
TFT阵列基板200还可包括层间绝缘膜150和/或平坦化膜170。
TFT阵列基板200还可包括可电连接到TFT以将电流传输到TFT的焊盘电极163。
焊盘电极163可电连接到供应用于驱动TFT的电流的驱动器集成电路(IC)(未示出)，焊盘电极163可从驱动器IC接收电流并且将电流传输到TFT。焊盘电极163可电连接到TFT。
焊盘电极163可设置在层间绝缘膜150上。焊盘电极163可由与TFT的源电极161a或漏电极161b相同的材料经由同一工艺形成。焊盘电极163可包括Al、Mo、Ti或Cu。在一些实施例中，焊盘电极163可具有Ti/Cu、Mo/Al/Mo、Mo/AlGe/Mo或Ti/Al/Ti的堆叠结构。
平坦化膜170可包括第二开口170b，焊盘电极163可暴露在外部。
图3A至图3F示出用于描述根据示例性实施例的制造TFT阵列基板的方法的剖视图。在当前实施例中，使用该方法制造图1的TFT阵列基板100。参照图3A，可在基板110上连续地形成非掺杂半导体层120'、栅极绝缘层130和第一导电膜(未示出)，然后，可对第一导电膜图案化以形成预备-栅电极141和电容器CAP的下电极142。
首先，可将非掺杂半导体层120'完全沉积在基板110上。非掺杂半导体层120'可以是没有执行人工掺杂的半导体层，并且可以是由具有绝缘性质的半导体形成的层。非掺杂半导体层120'可由包括非晶硅或结晶硅的半导体形成，并且可经由各种沉积方法中的任一种进行沉积。可通过使非晶硅结晶来形成结晶硅。使非晶硅结晶的方法的示例包括快速热退火(RTA)法、固相结晶(SPC)法、准分子激光退火(ELA)法、金属诱导结晶(MIC)法、金属诱导横向结晶(MILC)法和连续横向固化(SLS)法。
可在基板110和非掺杂半导体层120'之间设置缓冲层(未示出)。缓冲层可由绝缘材料形成，并且可经由各种沉积方法中的任一种进行沉积。在实施例中，可省略缓冲层。
根据示例性实施例，可不对非掺杂半导体层120'执行使用掩模的单独图案化工艺，可减少掩模的数量，并且可降低制造成本和时间。
可在非掺杂半导体层120'上形成栅极绝缘层130。栅极绝缘层130可由有机或无机绝缘材料形成。在一些实施例中，栅极绝缘层130可由SiNx、SiO2、氧化铪(Hf)或氧化铝形成。栅极绝缘层130可经由诸如溅射法、化学气相沉积(CVD)法和等离子体增强化学气相沉积(PECVD)法的各种沉积方法中的任一种形成。
然后，第一导电膜可完全形成在栅极绝缘层130上，并且可经由第一掩模工艺对预备-栅电极141和下电极142图案化。
可经由诸如溅射法、CVD法或PECVD法的各种沉积方法中的任一种来形成第一导电膜。
可通过以下步骤执行第一掩模工艺：涂覆光致抗蚀剂，使用第一掩模选择性地将光致抗蚀剂曝光，然后执行诸如显影工艺、蚀刻工艺和剥离或灰化工艺的一系列工艺。蚀刻工艺可包括湿蚀刻工艺、干蚀刻工艺或其组合。
预备-栅电极141可包括栅电极141a和形成在栅电极141a上的上栅电极141b。上栅电极141b可比栅电极141a厚，上栅电极141b可在随后将描述的第一掺杂工艺期间用作掩模。上栅电极141b可由与源电极161a或漏电极161b相同的材料形成。上栅电极141b可包括Al、Mo、Ti或Cu。在一些实施例中，上栅电极141b可具有Ti/Cu、Mo/Al/Mo或Ti/Al/Ti的堆叠结构。
下电极142可具有与预备-栅电极141相同的结构。下电极142可包括第一电极层142a和第二电极层142b。第一电极层142a可由与栅电极141a相同的材料形成，第二电极层142b可由与上栅电极141b相同的材料形成。
参照图3B，可形成第一绝缘膜(未示出)以覆盖预备-栅电极141和下电极142，然后可通过去除待形成TFT的区域来形成开口150a。因此，层间绝缘膜150可在待形成TFT的区域中包括开口150a，并且第一接触孔130a和第二接触孔130b可形成在栅极绝缘层130中。
第一绝缘膜可具有有机绝缘材料和无机绝缘材料的单层或堆叠结构。在一些实施例中，第一绝缘膜可由SiNx、SiO2、氧化铪或氧化铝形成。第一绝缘膜可经由诸如溅射法、CVD法和PECVD法的各种沉积方法中的任一种形成。
然后，可经由第二掩模工艺基于预备-栅电极141去除第一绝缘膜，以形成包括开口150a的层间绝缘膜150。在第二掩模工艺期间，可形成开口150a并且同时地，可使用半色调掩模同时形成栅极绝缘层130的第一接触孔130a和第二接触孔130b。可通过第一接触孔130a和第二接触孔130b暴露非掺杂半导体层120'的一部分。
然后，参照图3C，可执行第一掺杂工艺，以在非掺杂半导体层120'中形成源极-漏极区123。通过执行掺杂工艺，可形成包括源极-漏极区123和非掺杂区125并且具有第一掺杂浓度的预备-半导体层120”。在第一掺杂工艺期间，可通过将p型或n型掺杂剂离子部分注入到非掺杂半导体层120'来形成源极-漏极区123。
在第一掺杂工艺期间，预备-栅电极141和层间绝缘膜150可作为掩模操作。可不需要单独的掩模来形成源极-漏极区123，并且可通过层间绝缘膜150保持具有绝缘性质的非掺杂区125。
栅极绝缘层130可由一定材料形成并且具有一定厚度，使得在第一掺杂工艺期间注入的掺杂剂可穿过栅极绝缘层130，并且可通过栅极绝缘层130将掺杂剂注入到源极-漏极区123。
参照图3D，可形成源电极161a、漏电极161b和电容器CAP的上电极162。
首先，为了形成源电极161a、漏电极161b和电容器CAP的上电极162，可将第二导电膜(未示出)完全形成在基板110上，以覆盖预备-栅电极141和层间绝缘膜150，并且可执行第三掩模工艺。
可经由诸如溅射法、CVD法和PECVD法的各种沉积方法中的任一种来形成第二导电膜。
第二导电膜可包括Al、Mo、Ti或Cu。在一些实施例中，第二导电膜可具有Ti/Cu、Mo/Al/Mo、Mo/AlGe/Mo或Ti/Al/Ti的堆叠结构。在一些实施例中，第二导电膜的厚度可以是至少
Figure BDA0000802654920000101
在一些实施例中，第二导电膜可由与图3C的上栅电极141b相同的材料形成。上栅电极141b可具有与第二导电膜相同的蚀刻速率，可在第三掩模工艺期间对源电极161a、漏电极161b和电容器CAP的上电极162图案化的同时去除上栅电极141b。
可通过以下步骤执行第三掩模工艺：涂覆光致抗蚀剂，使用第三掩模选择性地对光致抗蚀剂曝光，然后执行诸如显影工艺、蚀刻工艺和剥离或灰化工艺的一系列工艺。蚀刻工艺可包括湿蚀刻工艺、干蚀刻工艺或其组合。
如上所述，在第三掩模工艺期间，可形成源电极161a、漏电极161b和电容器CAP的上电极162，并且可从预备-栅电极141去除上栅电极141b。在实施例中，可经由单独的掩模工艺或回蚀工艺执行去除上栅电极141b的过程。
参照图3E，可经由第二掺杂工艺执行沟道掺杂。在第二掺杂工艺期间，源电极161a、漏电极161b和层间绝缘膜150可作为掩模操作。栅电极141a可具有掺杂剂可穿过的厚度，在第二掺杂工艺期间掺杂剂可穿过预备-半导体层120”并且形成沟道区121。
沟道区121具有第二掺杂浓度，第二掺杂浓度可足够低于第一掺杂浓度(其是源极-漏极区123的掺杂浓度)，第二掺杂工艺可几乎不影响源极-漏极区123的掺杂浓度。
第二掺杂浓度可比第一掺杂浓度低大约102至104倍。
可掺杂沟道区121以调节TFT的阈值电压，第一掺杂类型和第二掺杂类型可以彼此相同或不同。
可经由第二掺杂工艺形成沟道区121，可形成包括具有第二掺杂浓度的沟道区121、具有第一掺杂浓度的源极-漏极区123和未掺杂区125的半导体层120。
参照图3F，可形成覆盖TFT和电容器CAP的平坦化膜170。
平坦化膜170可包括绝缘材料，并且可具有无机材料、有机材料或无机/有机材料的单层或多层结构。
在一些实施例中，平坦化膜170可由有机材料形成。当平坦化膜170由有机材料形成时，平坦化膜170可比当其由无机材料形成时厚，并且可防止寄生电容。在一些实施例中，平坦化膜170可具有大约3μm至大约5μm的厚度并且由于诸如聚丙烯酸酯、聚酰亚胺或BCB的材料涂覆在其上而具有平坦表面。平坦化膜170可包括暴露源电极161a或漏电极161b的一部分的第一开口170a。TFT可通过第一开口170a电连接到另一装置或布线。
图4至图6示出根据示例性实施例的应用TFT阵列基板的显示设备的剖视图。
图4和图5示出根据示例性实施例的有机发光显示设备10和20的剖视图。在图1、图4和图5中，同样的附图标记表示同样的元件，并且不提供重叠的细节。参照图4和图5，有机发光显示设备10和20可在TFT阵列基板100上包括有机发光器件(OLED)，该有机发光器件包括像素电极190、包括有机发射层的中间层210和对电极220。有机发光显示设备10和20还可包括像素限定膜180。
像素电极190可形成在平坦化膜170上。像素电极190可电连接到漏电极161b，同时填充平坦化膜170的第一开口170a。像素电极190可以是透明电极或反射电极。当像素电极190是透明电极时，像素电极190可包括ITO、IZO、ZnO或In2O3。当像素电极190是反射电极时，像素电极190可包括由银(Ag)、镁(Mg)、Al、铂(Pt)、钯(Pd)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)或其化合物形成的反射膜和由ITO、IZO、ZnO或In2O3形成的透明膜。在一些实施例中，像素电极190可具有ITO/Ag/ITO结构。
像素限定膜180可限定像素区和非像素区。像素限定膜180可在像素区中包括开口180a，并且可被形成为整体覆盖TFT阵列基板100和200。随后描述的中间层210可形成在开口180a中，开口180a可以是像素区。
像素电极190、中间层210和对电极220可形成OLED。从OLED的像素电极190和对电极220注入的空穴和电子可在中间层210的有机发射层中结合以发光。
中间层210可包括有机发射层。在实施例中，中间层210可包括有机发射层，并且还包括空穴注入层(HIL)、空穴传输层(HTL)、电子传输层(ETL)和电子注入层(EIL)中的至少一个。在实施例中，中间层210可包括有机发射层并且还包括其它各种功能层。
对电极220可形成在中间层210上。对电极220可与像素电极190一起形成电场，并且可从中间层210发光。像素电极190可以按照像素被图案化，并且对电极220可被形成为使得共电压被施加到所有像素。
像素电极190和对电极220可均是透明电极或反射电极。像素电极190可作为阳极操作并且对电极220可作为阴极操作，或反之亦然。
在图4和图5中，仅示出一个OLED，但显示面板可包括多个OLED。可每个OLED形成一个像素，各像素可实现红色、绿色、蓝色或白色。
在实施例中，中间层210可在整个像素电极190内公共形成，而不管像素的位置如何。有机发射层可形成为例如包括彼此垂直堆叠的发射红光、绿光和蓝光的发射材料的层或者形成为彼此混合的发射材料。可组合其它颜色，只要发射白光即可。有机发光显示设备10和20还可包括颜色转换层或滤色器，以将发射的白光转换成特定颜色。
钝化层(未示出)可设置在对电极220上，并且可覆盖并保护OLED。钝化层可以是无机绝缘膜和/或有机绝缘膜。
图5的有机发光显示设备20可包括焊盘电极203。焊盘电极203可电连接到供应用于驱动TFT的电流的驱动器IC(未示出)，焊盘电极203可从驱动器IC接收电流并且将电流传输到TFT。焊盘电极203可电连接到TFT。
焊盘电极203可设置在层间绝缘膜150上。焊盘电极203可包括第一焊盘电极层163'和第二焊盘电极层193。第一焊盘电极层163'可由与TFT的源电极161a或漏电极161b相同的材料并且经由与TFT的源电极161a或漏电极161b同一工艺形成。第一焊盘电极层163'可包括Al、Mo、Ti或Cu。在一些实施例中，第一焊盘电极层163'可具有Ti/Cu、Mo/Al/Mo或Ti/Al/Ti的堆叠结构。第二焊盘电极层193可由与像素电极190相同的材料并且经由与像素电极190同一工艺形成。第二焊盘电极层193可包括ITO、IZO、ZnO、In2O3、Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir或Cr。
平坦化膜170和像素限定膜180可具有暴露焊盘电极203的开口，并且焊盘电极203可暴露于外部。
图6示出根据示例性实施例的应用TFT阵列基板100的液晶显示设备30的剖视图。在图1和图6中，同样的附图标记表示同样的元件，并且不提供重叠的细节。
图6的液晶显示设备30可在图1的TFT阵列基板100上包括像素电极190、包括液晶的中间层310、对电极320和滤色器层(未示出)。
像素电极190可形成在平坦化膜170上。像素电极190可电连接到漏电极161b，同时填充平坦化膜170的开口170a。像素电极190可以是透明电极或反射电极。当像素电极190是透明电极时，像素电极190可包括ITO、IZO、ZnO或In2O3。当像素电极190是反射电极时，像素电极190可包括由Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr或其化合物形成的反射膜和由ITO、IZO、ZnO或In2O3形成的透明膜。在一些实施例中，像素电极190可具有ITO/Ag/ITO结构。
中间层310可包括液晶。中间层310的液晶的排列可根据由像素电极190和对电极320形成的电场而变化。可基于中间层310中的液晶的排列来确定穿过中间层310的光的透射率。
对电极320可形成在中间层310上。对电极320可被形成为使得共电压被施加到所有像素。对电极320可具有各种形状中的任一种，例如，可包括多个隙缝。
还可在对电极320上设置滤色器层。滤色器层可基于像素包括红色滤色器、绿色滤色器或蓝色滤色器。滤色器层可对从TFT阵列基板100下方的背光单元(未示出)照射并且穿过中间层310的光赋予颜色。
在图6中，仅示出一个像素，但显示面板可包括多个像素。
如上所述，根据示例性实施例的TFT阵列基板100可应用于有机发光显示设备10或20或者液晶显示设备30。在实施例中，TFT阵列基板100可应用于诸如等离子体显示设备和电泳显示设备的各种显示设备中的任一种。
以总结和回顾的方式，其上制造有平板显示设备的基板可包括TFT、电容器和布线的微小图案，并且可使用用于使用掩模转印图案的光刻工艺来形成这些微小图案。
根据光刻工艺，可将光致抗蚀剂均匀地涂覆在其上将形成图案的基板上，可使用曝光装置(诸如，步进(曝光)机)将光致抗蚀剂曝光，然后可将光致抗蚀剂显影。在将光致抗蚀剂显影之后，可使用剩余的光致抗蚀剂来蚀刻基板上的图案，然后可在形成图案之后去除不必要的光致抗蚀剂。
当如此使用掩模转印图案时，需要首先制备具有期望图案的掩模，并且如果使用掩模的工艺的数量增加，则用于制备掩模的制造成本增加。
一个或更多个示例性实施例包括薄膜晶体管(TFT)阵列基板、其制造方法和采用TFT阵列基板的显示设备，其中，可减少使用掩模的图案化工艺的数量。如上所述，根据一个或更多个示例性实施例，可不执行半导体层的图案化掩模工艺和沟道掺杂掩模工艺，可减少掩模的数量，可降低制造成本并且可简化制造工艺。
这里已经公开了示例实施例，尽管采用了具体术语，但仅以一般的和描述性的含义而非限制性的目的来使用和解释这些术语。在一些情况下，如对于到提交本申请时为止的本领域技术人员而言将明显的是，可单独使用结合具体实施例描述的特征、特性和/或元件，或者可与结合其它实施例描述的特征、特性和/或元件组合使用，除非另有明确说明。因此，本领域技术人员将理解的是，在不脱离如权利要求书中阐述的本发明的精神和范围的情况下，可以进行形式和细节上的各种变化。

Claims (15)

1.一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括至少一个薄膜晶体管以及电容器，所述至少一个薄膜晶体管包括：
半导体层，包括在基板上且具有第一掺杂浓度的源极区和漏极区、在所述源极区和所述漏极区之间且具有第二掺杂浓度的沟道区以及从所述源极区和所述漏极区延伸的非掺杂区，所述第二掺杂浓度低于所述第一掺杂浓度；
栅极绝缘层，在所述半导体层上；
栅电极，在所述栅极绝缘层上并且与所述沟道区至少部分叠置；
层间绝缘层，对应地设置在所述非掺杂区上方；
源电极和漏电极，与所述栅电极绝缘并且分别电连接到所述源极区和所述漏极区；以及
平坦化膜，覆盖所述薄膜晶体管并且包括部分暴露所述源电极或所述漏电极的开口，
其中，所述层间绝缘层包括与所述沟道区以及所述源极区和所述漏极区对应的开口，
所述电容器，包括：下电极，在所述非掺杂区延伸的所述半导体层上；以及上电极，与所述下电极绝缘并且与所述下电极至少部分叠置，
其中，所述下电极包括第一电极层和第二电极层，
其中，所述第一电极层由与所述栅电极相同的材料形成，
其中，所述半导体层的所述非掺杂区与所述下电极叠置，
其中，所述半导体层设置在所述基板与所述栅电极之间，
其中，所述栅电极的厚度比所述下电极的厚度薄，
其中，所述层间绝缘层的所述开口的侧壁与所述源极区和所述漏极区的侧壁竖直对齐，并且
其中，所述平坦化膜直接接触所述栅电极、所述源电极和所述漏电极。
2.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于：
所述第一电极层的厚度比所述第二电极层的厚度薄，
所述栅电极的厚度与所述第一电极层的厚度相同。
3.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述上电极包括与所述源电极或所述漏电极相同的材料。
4.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述栅电极包括透明导电材料。
5.根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述栅电极的厚度是
Figure FDA0002751831430000021
至
Figure FDA0002751831430000022
6.根据权利要求1所述的薄膜晶体管阵列基板，还包括焊盘电极，所述焊盘电极包括与所述源电极和所述漏电极相同的材料并且电连接到所述薄膜晶体管以将电流传输到所述薄膜晶体管。
7.一种显示设备，包括：
根据权利要求1所述的薄膜晶体管阵列基板；
像素电极，电连接到所述源电极或所述漏电极；以及
对电极，面对所述像素电极，
其中，中间层位于所述像素电极和所述对电极之间，并且包括有机发射层或液晶层。
8.一种制造薄膜晶体管阵列基板的方法，所述方法包括：
在基板的整个表面上形成非掺杂半导体层；
在所述非掺杂半导体层上形成栅极绝缘层；
在所述栅极绝缘层上形成薄膜晶体管的预备-栅电极和电容器的下电极，其中，所述预备-栅电极包括栅电极和位于所述栅电极上的上栅电极；
形成层间绝缘层，所述层间绝缘层覆盖所述下电极并且具有暴露将变成所述薄膜晶体管的沟道区和源极-漏极区的部分的开口；
通过在所述非掺杂半导体层中形成所述源极-漏极区来执行第一掺杂工艺；
形成连接到所述源极-漏极区的源电极和漏电极以及与所述下电极叠置的上电极；
通过在所述非掺杂半导体层上形成所述沟道区来执行第二掺杂工艺；以及
去除所述上栅电极，
所述第二掺杂工艺包括使用所述源电极和所述漏电极作为掩模来注入掺杂剂。
9.根据权利要求8所述的方法，其特征在于，执行所述第一掺杂工艺的步骤包括使用所述预备-栅电极和所述层间绝缘层作为掩模来注入掺杂剂。
10.根据权利要求8所述的方法，其特征在于，在所述第二掺杂工艺期间注入的所述掺杂剂通过所述栅电极被掺杂在所述非掺杂半导体层上。
11.根据权利要求8所述的方法，其特征在于：
所述上栅电极包括与所述源电极和所述漏电极相同的材料，
在形成所述源电极和所述漏电极的同时执行去除所述上栅电极的步骤。
12.根据权利要求8所述的方法，其特征在于：
所述栅电极包括透明导电材料，
所述栅电极的厚度是
Figure FDA0002751831430000031
至
Figure FDA0002751831430000032
13.根据权利要求8所述的方法，其特征在于，所述源极-漏极区的掺杂浓度高于所述沟道区的掺杂浓度。
14.根据权利要求8所述的方法，其特征在于：
所述栅极绝缘层包括暴露所述源极-漏极区的一部分的接触孔，
在半色调掩模工艺期间与所述层间绝缘层的所述开口同时地形成所述接触孔。
15.根据权利要求8所述的方法，还包括形成平坦化膜，所述平坦化膜覆盖所述源电极、所述漏电极和所述上电极，并且包括暴露所述源电极或所述漏电极的一部分的开口。
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