CN105122758A - 高带宽芯片间通信接口方法和系统 - Google Patents

高带宽芯片间通信接口方法和系统 Download PDF

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CN105122758A
CN105122758A CN201480020544.2A CN201480020544A CN105122758A CN 105122758 A CN105122758 A CN 105122758A CN 201480020544 A CN201480020544 A CN 201480020544A CN 105122758 A CN105122758 A CN 105122758A
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布赖恩·霍尔登
约翰·福克斯
彼得·亨特
约翰·凯伊
阿明·肖克罗拉
安德鲁·斯图尔特
朱塞佩·苏尔艾斯
罗杰·乌尔里奇
理查德·辛普森
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Kandou Labs SA
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Abstract

本发明公开了在物理信道中发送数据的系统和方法，该系统和方法可提供以低功耗实现高带宽的集成电路芯片间的低延迟接口，通过使用向量信令码，多条线路上的信令组可实现通信，其中，每条线路具有多于两个信号值的低摆幅信号。

Description

高带宽芯片间通信接口方法和系统
相关申请的交叉引用
本申请要求申请号为61/763,403，申请日为2013年2月11日的美国临时申请的优先权，并通过引用将其内容整体并入本文。
以下参考文献通过引用整体并入本文，以供所有目的之用。
公开号为2011/0268225，申请号为12/784,414，申请日为2010年5月20日，发明人为HarmCronie和AminShokrollahi，名称为《正交差分向量信令》的美国专利申请(下称“CronieI”)；
公开号为2011/0302478，申请号为12/982,777，申请日为2010年12月30日，发明人为HarmCronie和AminShokrollahi，名称为《具有抗共模噪声和抗同步开关输出噪声能力的高引脚利用率、高功率利用率芯片间通信》的美国专利申请(下称“CronieII”)；
申请号为13/030,027，申请日为2011年2月17日，发明人为HarmCronie，AminShokrollahi以及ArminTajalli，名称为《利用稀疏信令码进行抗噪声干扰、高引脚利用率、低功耗通讯的方法和系统》的美国专利申请(下称“CronieIII”)；
临时申请号为61/753,870，申请日为2013年1月17日以及非临时申请号为14/158,452，申请日为2014年1月17日，发明人为JohnFox，BrianHolden，PeterHunt，JohnDKeay，AminShokrollahi，RichardSimpson，AnantSingh，AndrewKevinJohnStewart和GiuseppeSurace，名称为《低同步开关噪声芯片间通信方法和系统》的美国专利申请(下称“FoxI”)。
背景技术
在通信系统中，信息可从某一物理位置传输至另一物理位置。并且对于此类信息传输，人们一般要求其可靠、快速、且消耗的资源最少。串行通信链路为最常见的信息传输手段之一，其可为基于以地面或其他常见参照物为相对参照的单线电路，也可为基于以地面或其他常见参照物为相对参照的多个此类电路，还可为基于相互间互为相对参照的多个电路。
上述后者的一例中使用差分信令(DS)。差分信令的工作原理为，在一条线路上发送一个信号，而且在该线路的配对线路上发送上述信号的相反信号。其中，信号信息由此两条线路之间的差值，而非其相对于地面或其它固定参照物的绝对值表示。相较于单端信令(SES)，差分信令可抵消串扰和其它共模噪声，从而增强原始信号在接收端的恢复能力。现有的多种信令方法可在保持差分信令的有益性能的同时，实现优于差分信令的引脚利用率。许多此类方法的工作原理在于，同时使用多于两条线路，在每条线路上均使用二进制信号，且将信息映射为多组比特。
向量信令是一种信息发送方法。通过向量信令，多条线路中的多个信号在保持每个信号的独立性的同时可视为一个整体。其中，上述整体信号中的每一个均称为分量，所述多条线路的数量称为向量的“维数”。然而，在一些实施方式中，与差分信令对的情况一样，某一线路中的信号完全取决于另一线路中的信号。因此，在某些情况下，所述向量维数指的是多条线路中信号的自由度的数量，而非所述多条线路的数量。
在二进制向量信令中，每一分量具有坐标值(或简称“坐标”)，该坐标值为两个可能取值当中的一个。举例而言，可将8条单端信号线视为一个整体，其中，每个分量/线路的取值为信号周期两值中的一值。那么该二进制向量信令的一个“码字”即对应所述整体分量/线路组的其中一个可能状态。对于一个给定的向量信令编码方案，有效可取码字的集合称为“向量信令码”或“向量信令码集”。“二进制向量信令码”即为将信息比特映射至二进制向量的一种映射方法和/或一组规则。
在非二进制向量信令中，每个分量的坐标值选取自由多于两个的可能取值组成的组。“非二进制向量信令码”则指将信息比特映射至非二进制向量的一种映射方法和/或一组规则。
CronieI，CronieII，CronieIII和FoxI中均描述了向量信令方法的实施例。
发明内容
在至少一种实施方式中，本发明提供在物理信道中发送数据的方法和装置，该方法和装置可提供以低功耗实现高总带宽的高速低延迟接口，从而实现多芯片系统中各集成电路芯片的互连。在一些实施例中，可使用不同的电压、电流等电平实现信令，而且还可使用两个以上的电平，例如，每线信号采用三个值的三进制矢量信令码。
此《发明内容》部分为以下《具体实施方式》中所描述概念的选择性简述，此《发明内容》部分的目的并不在于指出权利要求所述技术方案的关键或必要技术特征，也不在于辅助确定权利要求的范围。通过查阅以下《具体实施方式》的内容以及附图，本领域技术人员可清楚了解本发明的其他目的和/或优点。
附图说明
以下，通过参考附图，描述本发明的各个实施例。其中，本文及附图中通篇以相同的数字标注类似元件或构件。
图1为本发明至少一种实施方式中由发射装置、互连结构及接收装置组成的例示系统框图。
图2为本发明至少一种实施方式中双向芯片接口框图。
图3为在本发明至少一种实施方式中三进制驱动电路示意图。
图4和图4A为本发明的至少一种实施方式中线路接收器电路示意图。
图5为本发明至少一种实施方式中由5b6w-RS编码的系统的眼图。
图6为本发明至少一种实施方式中5b6w编码器示意图。
图7为本发明至少一种实施方式中5b6w解码器示意图。
图8B为本发明的至少一种实施方式中使用TLT(4,1)-RS编码的系统框图。作为比较，图8A为现有多线接口框图。
图9A和9B为本发明至少一种实施方式中三进制低摆幅驱动器和三进制线路接收器电路示意图。
图10为本发明至少一种实施方式中通过硅中介层互连的集成电路装置示意图。
具体实施方式
虽然将多个完整系统集成至单一集成电路的技术能力在不断提高，但是多芯片系统及子系统仍保留着其显著的技术优势。将一个大的系统分割为多个芯片级元件，可允许每个芯片由其自身的最优化工艺制造，从而获得更高的电压容差、更小的漏电率、更高的晶体管增益等优化性能。同时，较小芯片的良品率较高，因此可降低系统成本。此外，少数此类最优化芯片可以以多种方式组合，从而形成多种集成系统，其中，各个芯片可独立修改，而且还允许在系统集成时添加客户专用功能。
上述分割的一大难点在于如何找出子系统间的既能以所期望的方式分割各实施功能又能实现良好定义的可实施界面的分界点。传统工艺中，将需要高带宽和/或低延迟的互连功能的分割方式排除在外。这是因为，此类分割方式对应于复杂的物理接口，该接口需使用成百上千个不同的引脚和导线，而且需使用可造成高功耗的I/O驱动器和接收器。
现今已有多种解决方案可缓解此类制约因素。倒装芯片或穿通芯片的互连结构所使用的微球连接方式允许在每个芯片上形成成百上千个连接点。硅中介层等芯片载体可在每毫米尺寸上提供数百个具有严格控制的信号路径布线以及毫米级芯片间通信距离上稳定的传输线路特性的信号线路。因此，一旦上述接口的功耗、复杂性以及其他在电路实施上的问题得到解决，则可实现可支持高带宽芯片间连接的物理基础结构。
出于说明而非限制目的，假设此处描述的本发明至少一些方面的例示性实施方式的系统环境具有：
●连接至少两个集成电路(IC)芯片的至少一个通信接口，其中，所述芯片至少形成一个发射器和一个接收器，在一些实施例中，所述通信接口由具有100条或更少线路的互连结构所支持；
●至少连接所述两IC芯片的硅中介层器件，其中，所述硅中介层器件使用微凸点或微球阵列连接体，所述连接体具有约为100线/mm的布线密度以及可控阻抗、可控偏移(controlled-scew)、毫米级的器件间信号路径；
●至少约500GB/秒的上述通信接口总带宽；
●在如通用40纳米集成电路工艺的中等水平工艺技术节点中，小于约250毫瓦的所述通信接口发射器及接收器工作状态下的总功耗。
图10为本发明在上述系统环境中至少一种实施方式下连接至少两个集成电路芯片的例示硅中介层的示意图。硅中介层101包括用于连接至硅芯片11002和硅芯片21004的微凸点1006。硅中介层1010可包括用于连接至与封装衬底1014相连接的倒装芯片凸点1012的硅通孔(TSV)。
应该注意的是，对于阻抗匹配式“传输线路”方案和高阻抗非端接总线方案而言，都存在着合适的带宽、引脚数及通信距离的组合。如下文所述，本发明的至少一种实施方式采用低摆幅电流模式逻辑引脚驱动器和与发射器和接收器均端接的互连线。同样如下文所述，本发明的至少一种实施方式采用CMOS式引脚驱动器和高阻抗非端接互连线。
不失一般性而言，此处将器件间的物理接口描述为集成电路器件之间的点对点接线连接，而且可选地包括多个器件的多分支总线互连。在一种实施方式中，采用硅中介层实现芯片间连接。在另一种实施方式中，采用高密度低阻抗印刷电路板实现芯片间连接。
其他实施方式采用具有通孔键合或倒装芯片键合的芯片间直接连接方式。另外其他的实施方式可采用不同的信令电平、连接拓扑结构、端接方式，和/或其他物理接口，包括光学式、电感式、电容式或电气式互连。类似地，虽然为了描述的清晰性，只给出了从发射器至接收器的单向通信的实施例，但使用组合发射器-接收器的实施方式以及使用双向通信的实施方式同样属于本发明的范围之内。
假设
出于描述而非限制目的，除非另有说明，还假设本发明的至少一些方面的例示实施方式进一步具有如下特征：
●技术：台积电通用40纳米工艺(TSMC40GP)或同等中等水平工艺
●Vdd＝0.9V
●最小接口：
○前向时钟结构
○8G/秒线速
○时钟恢复/常规锁相环(PLL)结构
○4:1多路复用器结构
○仅在启动时间(或链路空闲时间)时钟对齐
●信道假设：
○短程(约1毫米)低损耗低偏移跟踪
○与40μm间距微凸点以及约100线/mm布线密度相兼容，
○寄生效应(静电放电(ESD)100fF，100pH电感，微凸点10fF)
○Rx输入端50fF负载
○50-80欧姆连接阻抗
图1为本发明至少一种实施方式中具有发射器、器件间互连结构及接收器的互连系统总体框图。
端接传输线路实施方式
图2所示为本发明至少一种实施方式中双向芯片接口的顶层架构。作为一种示例，图中所示为支持8G/秒线速的4GHz4:1多路复用器结构。此实施方式采用源端和终端均端接的低信号摆幅电流模式逻辑驱动器，该驱动器使用基于由6个三进制码符组成的码字的向量信令码。对于所述编码器、传输驱动器、接收比较器和解码器所做的任何描述均适用于整个接口中的所有六线子系统。
编码技术
为了上述通信系统的设计目的，需要使用运行于少数线路上的向量信令码，该向量信令码具有小尺寸的极低功率检测器以及高的引脚利用率。上述设计可通过多种方式实现，但每种方式所能达到的效果不尽相同。
由于上述链路为短程链路，无需使用用于实施时钟和数据恢复等大量均衡化任务的高功耗元件，因此该链路的主要功耗大部分产生于线路驱动器以及线路接收器或检测器，小部分产生于编码器和解码器。其中，如图3所示，所述驱动器消耗的功率可通过降低摆幅以及使用电流模式逻辑拓扑结构的方式降低。当信道条件良好且预期不会发生许多眼闭状况时，还可在此类应用中优选使用非二进制编码。这是因为，此类编码基于由于线路所传输的码符大小不同，因此所需功耗不同的事实可进一步降低驱动器功耗。此外，使用非二进制编码还可增加经线路发送的比特的数目，从而提高引脚利用率。在众多的非二进制编集中，由标记为-1、0和+1的三个码元组成的三进制编集具有如下的额外优点：只需在线路上驱动三个值，因此相对而言较为简单，以及可使用当驱动所述三个状态之中的一个状态时无需任何功耗的发送方法。出于本次公开的目的，我们仅专注于三进制编码的情况。然而，应当注意的是，此限制仅在于说明目的。
检测器的功率主要消耗于其对各线路实施的比较操作中。其中，最为简单的拓扑结构为仅以成对方式对线路进行比较。全三进制排列调制码，即包括三进制向量的所有不同排列方式的排列调制码，通常需要的成对比较次数为N×(N-1)/2，其中，N为所使用线路数。因此，举例而言，3条线路需使用3个比较器，4条线路需使用6个比较器，5条线路需要10个比较器，以此类推。要想达到1或1以上的引脚利用率，必须使用6线或更多线路的三进制向量信令码，因此必须使用至少15个比较器，即每个接收比特平均对应5/3个比较器。对于上述具体应用而言，此数目可能显得过大。因此，虽然可能会略微降低引脚利用率，但仍需要采用其他技术，以大幅减少每个输出比特所需的比较器数目。
此类编码方案一般可通过离散数学工具获得，尤其是离散优化工具。假设C是一个向量信令排列调制码(三进制码或非三进制码)，其具有M个码字，每个码字的长度为N，如上文所述，最多需要N×(N-1)/2次成对比较即可涵盖所有码字。为了减少比较次数，可选择一定数量(设为L)的比较器，而且制作所谓的可区别性图表，该图表的各个节点分别对应各个码字。在该图表中，将上述所选比较器无法区分的两个节点相互连接起来。也就是说，在这两个码字中，以及对于所有所选比较器而言，要么在给定的比较器下各位的排序相同，要么在此两个码字的至少一个码字中两值相同。例如，当所述比较器对长度为3的向量信令码中的1位和2位，1位和3位，1位和4位，以及2位和4位进行比较，那么(0,0,-1,1)和(-1,0,1,0)两个码字将不可区分。
一旦区分性图表制好后，接下来的任务就是找出此图表中的最大独立集，即没有两个节点(即码字)相连接(即不可区分)的最大节点集。有多种方法可用于找出此类独立集。离散数学领域的技术人员在阅读此公开内容时可理解的是，上述问题可编制为可由标准方法解出(即在码字数目不大的情况下，在合理的时间内解出)的整数线性程序。当上述问题较大时，可也采用试探法与整数线性编程相结合的方式实现上述目的。
为了满足前述系统要求，所使用的比较器数目和所传输的比特数目之间的一个较好的折衷方案可以为，比较器数目比传输比特数大1。通过添加此约束条件，上述区分性图表理论方案的一个具体实施方式可解出如下代码。
当线路数目为3时，由码字(1,-1,0)，(0,1,-1)，(0,-1,1)和(-1,0,1)组成的代码使用两个比较器：第一个比较器比较1位和2位，第二个比较器比较1位和3位。此编码的每比特(其值为1)所对应比较器数目极其高效，而且引脚利用率为2/3。
当线路数目为4时，任何可传输3个或更多比特且使用不多于3个比较器的代码均将导致不可区分性，因此应避免使用。当仅使用4个比较器来传输3个比特的代码时可避免上述不可区分性。以下8个向量给出了一种可行的此类代码：
(1,0,0,1)，(1,-1,0,0)，(0,1,-1,0)，(0,0,1,-1)，
(0,0,-1,1)，(0,-1,1,0)，(-1,1,0,0)，(-1,0,0,1)
上述4个比较器对1位和2位，1位和3位，1位和4位，以及2位和3位进行比较。平均而言，每个输出比特对应4/3个比较器，而且此代码的引脚利用率为75％。
当线路数目为5且比较器数目也为5时，上述优化程序所找出的最佳代码具有14个码字，比可编码4个比特的代码少2个码字。对于许多应用而言，该代码的引脚利用率欠佳。
当线路数目为6且比较器数目为5时，上述程序给出的代码具有24个码元，比可编码5个比特的代码少8个码元。
当比较的次数升至6次时，上述程序给出了一种使用价值非常高的编码方案。此代码称为5b6w代码，其描述如下。
5b6w-RS码
此节对通过与本发明多电平低摆幅电流模式逻辑接口共用而以低功耗实现高链路特性的代码进行描述。此代码在本说明书中描述为5b6w-RS码，其作用于5个二进制输入，以生成由6条线路传输的信号值。为了实现所需的处理能力，上述接口总体包含多个此码组。在一个实施例中，上述码组的数目为13，信号线总数目为78，共编码多达65个二进制数据比特。
所述5b6w向量信令码设计为在每个六线组上发送2个“+”信号，两个“-”信号，两个“0”信号。由此可见，此代码为每组具有相同数量“+”值和“-”值的“平衡”码。有相关知识的从业人员可注意到的是，在没有其他制约条件的情况下，基于在每个六线组上发送2个“+”信号及两个“-”信号方式的代码共有90种不同组合，足以编码6个而非5个比特。然而，出于使编码器/解码器保持较低复杂度从而减小实施面积的考虑，以及出于实现低功耗接收器结构的考虑，我们选择使用这些组合的由以下32个码字组成的特定子集：
(+1，0，-1，-1，+1，0)，(+1，-1，0，+1，-1，0)，(-1，+1，0，-1，0，+1)，(-1，0，+1，0，+1，-1)
(+1，-1，0，0，-1，+1)，(+1，0，-1，+1，0，-1)，(-1，0，+1，-1，+1，0)，(-1，+1，0，+1，-1，0)
(0，+1，-1，-1，0，+1)，(0，+1，-1，+1，-1，0)，(-1，0，+1，-1，0，+1)，(-1，+1，0，+1，0，-1)
(-1，0，+1，0，-1，+1)，(+1，0，-1，0，-1，+1)，(+1，-1，0，0，+1，-1)，(0，-1，+1，-1，+1，0)
(-1，0，+1，+1，-1，0)，(+1，-1，0，-1，+1，0)，(0，+1，-1，+1，0，-1)，(-1，+1，0，0，-1，+1)
(-1，0，+1，+1，0，-1)，(+1，-1，0，-1，0，+1)，(+1，0，-1，0，+1，-1)，(-1，+1，0，0，+1，-1)
(0，-1，+1，-1，0，+1)，(0，-1，+1，+1，-1，0)，(+1，0，-1，-1，0，+1)，(+1，-1，0，+1，0，-1)
(-1，+1，0，-1，+1，0)，(0，-1，+1，+1，0，-1)，(0，+1，-1，-1，+1，0)，(+1，0，-1，+1，-1，0)
用于区分这些码字的比较器对1位和2位，2位和3位，1位和3位，4位和5位，5位和6位，以及4位和6位进行比较。此外，此编码方式还可保证免受同步开关输出(SSO)噪声的影响。
上述名称中的“-RS”部分表示已编码组的线路信今使用低摆幅信号值。其中，“+”信号可由相对于参考电平为+200mV的值表示，“0”信号可由相对于参考电平为+100mV的值表示，“-”信号可由相对于参考电平为0mV的值表示。这些信号电平只作为示例，并不具有限制性。而且，这些信号电平表示自额定参考电平逐级增加的信号值。
发送驱动器
根据本发明的至少一种实施方式，图3为用于一个六线组Out1至Out6的发送驱动器示意图。电压源Vt及发送终端电阻器305提供补偿信号电平或静态信号电平且在在每个接收线路终端产生一已知电流，从而产生所期望的表示“0”信号的接收信号电平。当在电阻器310、311和312上施加相应输入A1，B1或C1时，可分别在相应所选输出Out1、Out2或Out3中增加电流301，从而使该线路产生“+”信号电平。类似地，当在电阻器313、314和315上施加相应输入A2、B2或C2时，可分别从相应所选输出Out1、Out2或Out3中移除电流302，从而使相应线路产生“-”信号电平。基线参考电平及各级信号水平由Vt和电流源301和302的值，以及所述已知终端电阻值控制。
线路Out4、Out5及Out6的驱动器以同样的方式工作。其中，输入D1、E1和F1控制“+”电平，输入D2、E2和F2控制“-”电平。
每个三线子组Out1/Out2/Out3和Out4/Out5/Out6中，均严格具有一个“+”信号，一个“0”信号，以及一个“-”信号。因此，每个三线子组的驱动器所消耗的电流为恒定值，从而不增加系统的同步开关输出噪声。
线路接收器
根据本发明的至少一种实施方式，图4为使用5b6w-RS码的六线组线路接收器示意图。每一六线组使用六个差分比较器401至406，用于执行(In1-In2)、(In2-In3)、(In1-In3)、(In4-In5)、(In5-In6)及(In4-In6)这六种比较，以分别产生一个数字输出OutA至OutF。由此可见，此接收器为无参照接收器，并可提供抗共模噪声效应。
如图所示，每个输入In1至In6均由相应电阻器410至415端接于终端电压Vt。在一种实施方式中，Vt为系统接地电压。
图4A和图4的区别只在于上述终端电阻器的连接方式不同。在图4A所示实施方式中，电阻器410、411和412连接于一共有节点。三线子组{In1，In2，In3}中的单个“+”信号和单个“-”信号的合并接收电流在所述共有节点上产生一已知电压，作为“0”信号电平的虚拟源。此外，电阻器413、414和415同样采用此共有终端连接方式。
图5所示为此信令方法的例示眼图。其中，图5A所示为源端和终端端接电阻均为100欧姆且互连线路为1μm条件下的模拟接收电平；图5B所示为互连线路为3μm时的相同系统模拟结果。其中，所示各电压为与基线参考电平的差值。
5b6w-RS编码及解码
根据本发明的至少一种实施方式，通过例如查询表或组合逻辑，使用数据值与码字之间的简单的一对一映射，可实现将5比特的二进制数据编码成6个向量信令码字信号。在高速应用中，组合逻辑编码器实施时所需资源较少，因此耗电量及操作延迟较低。在另一实施方式中，如图6所示例示组合逻辑编码器，In[4:0]的五个输入比特产生编码输出I0w0[1:0]、I0w1[1:0]、I0w2[1:0]、I1w0[1:0]、I1w1[1:0]和I1w2[1:0]，以对六条线路的输出驱动器实施控制。由于输出线路信号为三进制信号，因此每个三进制输出驱动器信号(例如，图3所示信号A1，A2，B1，B2，C1，C2)的控制需要使用两个二进制编码器输出。
根据本发明的至少一种实施方式，可同样使用查询表或组合逻辑确定出接收信号(例如，图4所示OutA至OutF)所表示的5比特二进制数据值。同样的，在高速应用中，由于组合逻辑解码器实施时所需资源较少，因此耗电量及操作延迟较低。图7为根据本发明的至少一种实施方式的例示组合逻辑解码器。
根据计算，在所述例示系统配置中，一种使用5b6w-RS码的发送器和接收器的例示实施方式所需的功耗为169mW(通常情况下)和253mW(最差情况下)，在所述例示实施工艺中的所需电路面积约为0.37mm2。
5b6w-RS编码的其他已知变体的实施例见参考文献CronieI、CronieII、CronieIII和FoxI。
非端接互连实施方式
此节描述满足所述系统要求的另一解决方案，该方案使用电压模式CMOS式驱动器以及非端接互连布线方式。
在本发明的至少一种实施方式中，使用一种称为“跃迁限幅三进制4-线1-跃迁低摆幅码”，或称为“TLT(4,1)-RS码”的跃迁限幅码。在一种实施方式中，其使用小型有限脉冲响应(FiniteImpulseResponse，FIR)滤波器，用于使4条线路上发送的跃幅最小化。其中，所述4条线路中的每一条均使用三电平(三进制)接口。
驱动器选择
在低电容、中等频率以及/或者跃迁限幅的接口应用中，非端接CMOS式驱动器的功耗可比前述实施例中所使用的电流模式逻辑驱动器更小。此节中所述解决方案采用CMOS式驱动器。
非端接CMOS式驱动器的一个特点在于，其功耗主要产生于跃迁中。因此，无论采用何种编码技术，CMOS式驱动器总会产生一定的SSO噪声。由于在使用CMOS式驱动器的情况下不可能完全消除SSO噪声，因此我们的目标在于大幅降低SSO噪声以及I/O接口的功耗。
本文SSO噪声及功耗的计算中，作如下假设：
1.由于使用CMOS驱动器，因此大部分的供电只消耗于从低电压值向高电压值的跃迁，而且功耗大小与跃迁量成正比。
2.由于驱动器中反相器链等的作用，极小部分的功耗产生于从高电压值向低电压值的跃迁。
3.单条线路从x值跃迁至y值时对总SSO噪声的贡献为x-y的绝对值。
4.总SSO噪声为所有线路的SSO噪声贡献总和。
5.下文中SSO噪声与功耗均以数字示出，这些数字应视作与以同等跃迁速度驱动同等负载的单端CMOS驱动器所产生的数字相关联。
三进制电平
如上所述，本文提倡在每条传输线上使用3电平信令，我们将此编码方案称为“三进制编码”。在此例中，上述电平与线路上的电压电平相对应，而所述线路上的电压电平又取决于系统的Vdd以及信号的摆幅。为了在描述中消除电压的因素，以及为了实现与单端信令的公平比较，此处示例中假设：
●对于全摆幅单端(SE)二进制信令而言，电压电平的乘数为0和1(即，电压电平对应于0×Vdd以及1×Vdd)
●对于低摆幅(RS)三进制编码，电压电平乘数为0、1/4和1/2。
上述假设值的目的在于描述说明，并不表明任何限制。
线路状态
下文中，为了编码算法描述的简单性，两个二进制状态表示为0和1，三个三进制状态表示为0、1和2。这些状态与上述用于状态传输的电压电平乘数无关。
噪声类型
对于用于解决上述系统限制的示例实施方式而言，可认为，与热噪声和其他噪声源相比，同步开关输出(SSO)噪声为最主要的噪声源。
降低功耗及SSO噪声的技术
在本发明的至少一种实施方式中，描述了两种接口改进技术。这两种技术既可单独使用，也可为了达到最大的效果而同时使用。
如下节所述，第一个改进技术在于增设跃迁限幅编码方案。
第二个改进技术在于降低接口摆幅。在宽的高带宽接口中同时降低功耗及SSO噪声的一种重要技术在于降低该接口的摆幅。下述三进制接口的低摆幅形制可使峰值SSO噪声以及平均功耗进一步降低。
跃迁限幅编码
由于对于非端接CMOS驱动器而言，跃迁非常重要。因此，通过跃迁编码信息是极其合理的。如果在线路上使用二进制状态，则无法在降低SSO噪声的同时，保持引脚的完全利用率，即在每一时钟周期内在每条线路上传输一个比特的性能。因此，本文所述应用中降低SSO噪声的方法中可使用三进制编码。如本文公开内容所述，此类代码可将峰值SSO噪声降至约为单端信令峰值SSO噪声的12.5％。
所述SSO噪声降低码中的一种在本文中称为TLT(4,1)-RS码，该码为只使用4条线路的小型有效代码。因此，在一种满足上述例示系统要求的实施方式中，采用多套此类四线子系统，以满足总体处理能力要求。
此处描述一种基于相加对3取余法(mod-3addition)的跃迁编码方案。此运算先将0/1/2三个整数中的一个与另一个此类整数相加，然后求出此相加结果除以3后的余数。此外，该运算还可描述为下表：
TLT(4,1)-RS码
TLT(4,1)码运行于每一周期允许一个跃迁的四线接口上，即使用时钟周期间的状态跃迁已通过每一周期内只允许一条线路上的值发生变化而最小化的四线组。该码为三进制码，也就是说，每条线路可取三个值(此处标记为0、1和2)中的一个。由于相继的已编码TLT(4,1)输出之间只允许发生一个线路变化，因此由所有可能的跃迁方式组成的编码空间大小为9(即无跃迁，以及四条线路中的一条向两条新线路中的任意一条跃迁)。从而可知，每个TLT(4,1)码可直接对三比特输入数据字的变化进行编码，例如，对由当前输入数据字与前一输入数据字之间的三比特差值表示的三比特输入数据字变化进行编码。
相应编码器可包含前述相加对3取余法以及简易FIR滤波器。此FIR滤波器保留一个历史时钟，并将待传输数据变化编码为相对于该历史数据的变化量。对于编码器而言，其对每条线路的状态所实施的操作越少，则越有效。
操作时，编码器可以下述方式运行：对于给定的三个比特a,b,c以及历史向量(x[0],x[1],x[2],x[3])，其中，该向量的各个元素为三进制值且可从集合{0,1,2}中选取，如果(a,b,c)不为(0,0,0)，编码器将值x[a+2×b]变为(x[a+2×b]+(c+1))对3取余后的余数，而如果(a,b,c)＝(0,0,0)，则不使该值发生任何变化。在使用低摆幅的情况下，当线路值从状态0变化至状态2(或相反)时产生最差状况下SSO噪声，此时其电压从0*Vdd变化至Vdd/2。此情况下的最差状况下SSO噪声相当于在线路中使用全摆幅非端接CMOS驱动器时的最差状况下SSO噪声的一半。由于上述情况只发生于四条线路中的一条，因此所述低摆幅编码技术中的最差状况下SSO噪声为全摆幅非端接CMOS驱动器的最差状况下SSO噪声的八分之一。当然，当进一步减小摆幅时，还可进一步降低每线最大SSO噪声。
此外，在平均线路功耗方面，所述低摆幅TLT(4,1)码(简称TLT(4,1)-RS码)同样大大优于全摆幅CMOS驱动器。全摆幅CMOS驱动器的平均线路功耗为C×Vdd2×f/4，其中，C为各线路电容，f为时钟频率。对于TLT(4,1)-RS码而言，当线路发生跃迁时，其平均线路功耗为C×Vdd2×f/6，否则为零。由于在四线组中，当输入比特序列不为(0,0,0)时，严格只有一条线路发生跃迁，而其他线路不发生跃迁，因此可得出TLT(4,1)-RS码的平均每线功耗为7×C×Vdd2×f/(6×8×4)＝7×C×Vdd2×f/192，约为非端接全摆幅CMOS驱动器平均每线功耗的14.6％。
在TLT(4,1)码的低摆幅形制(即TLT(4,1)-RS码)中，峰值每线SSO噪声为单端信令峰值每线SSO噪声的1/8，即12.5％。
已知已有等同于所述TLT(4,1)-RS编码器的其他实施方式，例如采用其他数据跃迁-编码值映射方式以及/或者采用其他确定数据跃迁方式的实施方式。
跃迁码重置
跃迁码的使用还存在两个相关议题。第一个议题在于，当总线的使用频率较低时，如何保证其两端所用历史值之间的协调性。第二个议题在于当总线闲置时，如何保证线路中跃迁的最小化。
对于持续运行的总线而言，保证总线两端历史值为相同值不成为一个问题。有多种通过将FIR的历史值重置为已知值的解决方案用于解决跃迁码数据总线闲置时的问题。
使用跃迁码时的所述第二个议题在于如何很好地控制闲置/无操作总线上的值。由于使用跃迁码的重点在于使总线上的跃迁最小化，因此保证闲置总线上不发生跃迁非常重要。由于多数总线大部分时间处于所述闲置/不运行状态，所以此状态下消耗的功耗对于系统总功耗而言是首当其冲的。
TLT(4,1)-RS框图
图8B为TLT(4,1)-RS接口的框图。作为比较，图8A为现有多线接口框图。
应当注意的是，TLT(4,1)-RS中用于组成FIR滤波器(或同等的跃迁编码逻辑电路)的额外历史触发器位于主数据路径的外部，因此并不额外产生任何数据路径延迟。因此，例如图8B所示TLT(4,1)-RS的实施方式同样适用于与例如图8A所示现有接口相同的通用系统配时计划。虽然图8B所示TLT(4,1)-RS的实施方式需要额外的时序容限，但无需其他时钟周期。
在至少一种实施方式中，作为图8B所示接收器的一种变体，解码器紧邻三进制接收器设置于其下游。
启动算法
本文所公开技术的直接应用可能会导致历史值初始化时产生时钟延迟问题。此问题可通过如下方式获得缓解：例如在每次总线进入闲置状态或每次多分支总线系统中新的处于工作状态下的发送器和/或接收器被选中时的系统重置过程中，将发送器和接收器的历史值均初始化为已知状态。
TLT(4,1)-RS发送驱动器和三进制接收器
在本发明的至少一种实施方式中，发送驱动器例如使用NMOS晶体管驱动低电平。对于低摆幅TLT(4,1)-RS的中间电平和高电平，通过使用源极跟随器NMOS晶体管来达到参考电压。图9A为此类驱动器一实施例示意图。
在接收器端，需要对每条线路的高信号电平、中间信号电平或低信号电平进行检测。在本发明的至少一种实施方式中，每条线路可使用两个比较器，以将该线路的信号电平与已知参考电压进行比较。图9B为一种结构更为简单和紧凑的实施方式示意图，其使用四个晶体管和一个参考电压构成所需要的两个信号电平指示器。此电路可在所使用的半导体工艺可实现足够低的晶体管阈值电压时使用。
低摆幅电平的值通常为0、Vdd/4和Vdd/2。根据具体使用的系统电压以及半导体工艺，可通过调整这些例示值以优化系统性能。
在芯片上生成上述中间电平Vdd/4及高电平Vdd/2并非易事。这是因为所生成的电平必须具有精确、波动小、功耗小的特点，而且必须在其整个负载范围内都维持这些特性。线性稳压器虽然精确性较好，但是其功耗性能不佳。开关稳压器只有在使用高质量的无源器件时才能在芯片上实现上述目的。在一种实施方式中，上述各电压由外部提供。在另一种实施方式中，先由外部提供所述Vdd/2电压，而后由线性稳压器在芯片上生成所述Vdd/4电压，从而在电压提供方式的复杂性和由于线性稳压器的使用而产生的额外功耗之间取得平衡。
根据计算，在所述例示系统配置中，一种使用TLT(4,1)-RS的发送器和接收器例示实施方式需要的功耗为167mW(通常状况下)以及305mW(快速工作状态下)。
虽然此处实施例描述了向量信令码在点对点或多分支总线芯片间互连中的应用，然而其不应以任何方式视为对本发明范围构成限制。本申请中所公开的方法还可以同等效果适用于其他互连拓扑结构以及其他通信媒介，包括用于光通信、电容性通信、感应式通信以及无线通信的媒介。因此，此处所使用的描述性词语，如“电压”和“信号电平”应视为包括其在其他度量系统中的同等概念，如“光强”、“射频调制”等。此处所用词语“物理信号”包括可传送信息的物理现象的所有适用形态和属性。此外，物理信号可以为有形的非暂时性信号。

Claims (9)

1.一种用于集成电路器件互连的系统，其特征在于，包括：
一互连结构，位于至少两个集成电路器件之间且包括一个或多个互连线组，每个互连线组对表示向量信令码的码字的信号进行传输；
一编码器，用于将发送数据字转化为所述向量信令码的发送码字；
一发送驱动器，在所述一个或多个互连线组中的一个互连线组的互连线上发出与所述发送码字的码元对应的物理信号；
一接收器，用于对由所述发送驱动器使用的所述互连线上的物理信号进行检测，其中，所述物理信号为所述向量信令码的接收码字的码元；以及
一解码器，用于将所述接收码字译码为接收数据字，从而实现所述至少两个集成电路器件之间的互连。
2.如权利要求1所述系统，其特征在于，所述向量信令码为平衡码且包括由至少三个不同值构成的组中的码元。
3.如权利要求2所述系统，其特征在于，所述发送驱动器使得在互连线组上发送的所述平衡码的码元在交互中以被动方式生成所述互连线组的所述物理信号值中的至少一个。
4.如权利要求1所述系统，其特征在于，所述编码器用于将所述发送数据字与前一发送数据字之间的差值编码至所述发送码字中，所述解码器用于将所述接收码字译码为使其表示待施加至前一接收数据字以获得所述接收数据字的差值。
5.如权利要求4所述系统，其特征在于，还包括一存储器，用于将所述接收数据字保存为用于下一轮的前一发送数据字，其中，所述存储器由与一预选码字相等的一初始值配置。
6.一种在集成电路器件之间使用向量信令码传输二进制数据字的方法，其特征在于，包括：
将所述二进制数据字编码为至少一个向量信令码字，所述向量信令码字包括由三个或更多不同值组成的码集中的码符；
在连接一个发送集成电路器件以及至少一个接收集成电路器件的至少一个线组上发送所述至少一个向量信令码字；
通过所述至少一个接收集成电路器件接收所述至少一个向量信令码字；
将所述至少一个向量信令码字解码为接收二进制数据字；以及
通过所述至少一个接收集成电路器件使用所述接收二进制数据字。
7.如权利要求6所述方法，其特征在于，所述向量信令码为平衡码。
8.如权利要求7所述方法，其特征在于，基于所述向量信令码为平衡码，所述被发送向量信令码字的码符中的至少一个在传输过程中以被动方式生成。
9.如权利要求6所述方法，其特征在于，将所述二进制数据字编码包括：对当前的二进制数据字以及前一二进制数据字之间的差值进行编码。
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