CN104992979A - 具有自对准外延源和漏的多栅半导体器件 - Google Patents

具有自对准外延源和漏的多栅半导体器件 Download PDF

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CN104992979A
CN104992979A CN201510416064.4A CN201510416064A CN104992979A CN 104992979 A CN104992979 A CN 104992979A CN 201510416064 A CN201510416064 A CN 201510416064A CN 104992979 A CN104992979 A CN 104992979A
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A.卡佩拉尼
T.加尼
K-Y.沈
A.S.墨菲
H.戈麦斯
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Intel Corp
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Abstract

本发明涉及一种具有自对准外延源和漏的多栅半导体器件。具有低寄生电阻的沟道应变多栅晶体管及其制造方法。栅叠层可在具有栅耦合侧壁高度(Hsi)的半导体翼片之上形成，蚀刻速率控制掺杂剂可注入与栅叠层相邻的半导体翼片的源/漏区中以及注入半导体翼片的源/漏扩展区中。可蚀刻掺杂翼片区，以便去除在沟道区附近至少等于Hsi的厚度的半导体翼片，并且形成源/漏扩展底切。材料可在暴露半导体衬底上生长，以便形成再生长源/漏翼片区，从而填充源/漏扩展底切区。

Description

具有自对准外延源和漏的多栅半导体器件
背景技术
为了提高性能，常常期望减少衬底上的互补金属氧化物半导体(CMOS)器件(例如半导体衬底上的集成电路(IC)晶体管等)中使用的N型金属氧化物半导体(NMOS)器件沟道区中的电子和P型MOS器件(PMOS)沟道区中的带正电空穴的渡越时间。沟道长度的减小是减少渡越时间的有利方式，但是因为这类减小引起短沟道效应，所以研制了多栅器件，其中沟道区是非平面半导体主体的一部分或者由栅叠层所覆盖的“翼片”。对于这类多栅器件，晶体管能够由栅叠层通过侧壁以及翼片的顶面来选通以获得更好的选通控制。
随着改进的选通控制通过多栅设计变成可能，翼片的尺寸可缩放到这样的程度：与翼片的接触引起能够严重限制多栅器件的操作性能的寄生电阻Rexternal。降低总电阻的一种方法是掺杂翼片源/漏区。例如，掺杂剂可注入源/漏区中，并且可执行退火以激活掺杂剂并且使掺杂剂向沟道区扩散。
在使用注入和扩散方法的情况下，控制翼片内的掺杂剂浓度和位置的能力有限。此外，MOS器件的其它部分的尺寸，例如翼片周围的隔离物的存在，也能够极大地阻碍Rexternal的减小。
此外，由于翼片结构摆脱了周围的衬底，所以过去对平面器件证明是有利的应变感应迁移率增强技术可能不易适用于多栅器件。没有经由应变(例如单轴或双轴)来增强沟道迁移率的能力，从可能的较小沟道长度得到的多栅器件中的性能改进会至少部分被比较低的沟道迁移率抵销。因此，需要改进的方法和结构来克服源/漏翼片区中的这些限制。
附图说明
通过参照以下结合附图来阅读的详细描述，可最佳地理解本发明的实施例的组织和操作方法连同其目的、特征和优点，附图中：
图1是示出按照本发明的一个实施例、形成多栅器件中的源和漏外延扩展的方法的流程图；
图2A是按照本发明的一个实施例、与图1中的操作106对应的多栅器件的制造中的一个阶段的等距视图；
图2B是图2A中所示的器件的截面图；
图3A是按照本发明的一个实施例、与图1中的操作108对应的多栅器件的制造中的一个阶段的等距视图；
图3B是图3A中所示的器件的截面图；
图4A是按照本发明的一个实施例、与图1中的操作110对应的多栅器件的制造中的一个阶段的等距视图；
图4B是按照本发明的一个实施例、沿图4A中所示器件的B-B’平面的截面的视图；
图4C是按照本发明的一个实施例、沿图4A中所示器件的B-B’平面的截面的视图；
图5A是按照本发明的一个实施例、与图1中的操作112对应的多栅器件的制造中的一个阶段的第一截面图；
图5B是按照本发明的一个实施例、与图1中的操作112对应的多栅器件的制造中的一个阶段的与图5A中视图垂直的第二截面图；
图6A是按照本发明的一个实施例、与图1中的操作114对应的多栅器件的制造中的一个阶段的第一截面图；
图6B是按照本发明的一个实施例、与图1中的操作114对应的多栅器件的制造中的一个阶段的与图6A中视图垂直的第二截面图；
图7是按照本发明的一个实施例、与图1中的操作116对应的多栅器件的制造中的一个阶段的截面图；
图8是按照本发明的一个实施例、与图1中的操作118对应的多栅器件的制造中的一个阶段的截面图；以及
图9是按照本发明的一个实施例、与图1中的操作120对应的多栅器件的制造中的一个阶段的截面图。
将会理解，为了说明的简洁和清楚起见，图中所示的元件不一定按比例绘制。例如，为了清楚起见，一部分元件的尺寸可相对于其它元件经过放大。此外，在认为适当的情况下，附图之中重复参考标号，以指示对应或相似的元件。
具体实施方式
本文所描述的是形成多栅MOS器件(例如“finfet”)中的外延源和漏扩展的系统及方法。在以下描述中，将使用本领域的技术人员通常用于向本领域的其他技术人员传达其工作实质的术语来描述说明性实现的各种方面。然而，本领域的技术人员清楚，仅通过所述方面中的一部分也可实施本发明。为了便于说明，提出具体数量、材料和配置，以便透彻地理解说明性实施例。但是，本领域的技术人员清楚，即使没有这些具体细节也可实施本发明。在其它情况下，省略或简化众所周知的特征，以免使说明性实施例晦涩难懂。
各种操作将按照最有助于理解本发明的说明性实施例的方式依次被描述为多个分立操作；但是，描述的顺序不应当被理解为暗示这些操作必然是顺序相关的。具体来说，这些操作不需要按照陈述的顺序来执行。
本文所公开的是一种多栅器件，其中包括在沟道附近的垂直厚度大致等于Hsi的外延源和漏翼片区，并且还可包括再生长以布置在晶体管的栅电介质层之下的外延源和漏翼片区的一部分。图1是示出按照包括源和漏外延扩展的本发明的一个实施例、形成这类再生长源/漏区的方法100的流程图。图2-9示出方法100在执行时的特定操作之后的多栅器件。
方法100从离子注入操作106开始，执行该操作106以形成与布置在半导体翼片上的栅叠层相邻的半导体翼片的掺杂区。掺杂区将在为所形成的多栅MOS晶体管再生长源和漏区的准备过程中被去除。当暴露于适当的蚀刻剂时，掺杂区具有比周围衬底和沟道半导体材料的蚀刻速率更高的蚀刻速率，这实现蚀刻剖面的优异控制，从而允许再生长源和漏区的整形以获得最佳翼片下(sub-fin)泄漏特性和沟道应变。
图2A是按照本发明的一个说明性实施例、在图1中的操作106所提供的半导体翼片之上形成的栅叠层的等距视图。图2B表示沿图2A中所示的A-A’参考线截取的图2的多栅晶体管的截面图。如图2A和图2B所示，衬底202之上的非平面半导体主体形成具有平行六面体形状的翼片，翼片具有侧壁高度为Hsi的侧壁207以及延伸到超过相邻隔离区210的顶面211。顶面211和侧壁207被分配到非平面源区215和非平面漏区216，其间是栅叠层217所覆盖的沟道区。对于多栅晶体管，沟道至少通过侧壁207将是电容地可控的，使得Hsi表示栅耦合沟道侧壁高度。顶面211也可以是由覆盖栅叠层电容地可控的，以获得更大的阈值以下控制。在示范实施例中，栅叠层217是牺牲的，并且后来为了置换金属栅过程被去除。但是，本文所述的方法还可适合其中栅叠层217不牺牲、而是保留在最终多栅器件中的实施例。
在示范实施例中，衬底202是块硅或者绝缘体上硅底层结构。但是，半导体衬底202还可使用可以或者可以不与硅相结合的备选材料来形成，备选材料包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓。虽然描述了可形成衬底的材料的几个示例，但是可作为构建半导体器件的基础的本领域已知的任何材料落入本发明的精神和范围之内。
如图所示，栅叠层217包括栅电介质212、栅电极213和栅帽214。栅电介质212可以是二氧化硅、氮化硅、氧氮化硅或者介电常数大于10(即“高k”)的电介质材料。可使用的高k栅电介质材料的示例包括但不限于氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。栅电极213可以是多晶硅、多晶锗、金属或者它们的组合。栅帽214可以是任何常规的硬掩模电介质材料，诸如氧化硅、氮化硅等等。
图2B示出第一非平面主体250和第二非平面主体225可如何在掺杂翼片区208的相对侧上形成。第二非平面主体225可以是另一个功能晶体管的基础，或者只是提供控制第一非平面主体250的制造的一个或多个方面的手段的伪结构。因此，图2B示出掺杂翼片区208的两个不同示范界面：与隔离区210的界面以及与第二非平面半导体主体的界面。应当理解，掺杂翼片区208可具有远离第一非平面主体250、邻接这两个界面中任一个的端部。
离子注入操作106中使用的掺杂剂基于其增加它被注入其中的半导体翼片材料的蚀刻速率的能力来选择。因此，具体掺杂剂可基于衬底材料以及掺杂翼片的后续蚀刻中使用的蚀刻剂来改变。示范掺杂剂增加硅、锗或锑化铟的蚀刻速率。在特定实施例中，具体掺杂剂包括但不限于碳、磷和砷。例如，可按照范围从1×1014至1×1016个原子/cm3的剂量来使用碳。可按照范围从1×1014至5×1015个原子/cm3的剂量来使用磷。可按照范围从1×1014至5×1015个原子/cm3的剂量来使用砷。离子注入可在基本垂直方向(即，垂直于衬底的方向)上执行。但是，在一些实施例中，离子注入过程的至少一部分可在成角度的方向进行，以便将离子注入栅叠层217之下。对于非置换栅实施例，栅帽214可形成足够的厚度以防止栅电极213的掺杂。通过半导体翼片中存在的蚀刻剖面控制掺杂剂，可执行退火以完成操作106。退火将掺杂剂进一步驱动到半导体翼片中，并且降低离子注入期间衬底所承受的任何损坏。示范退火在700℃与1100℃之间进行至多一分钟的持续时间，例如，五秒钟的持续时间。
掺杂翼片区208的尺寸(包括深度)可基于所形成的多栅MOS晶体管的要求来改变。如图2A和图2B所示，在注入操作106之后，接近沟道区205的掺杂翼片区208延伸到半导体翼片的不大于高度Hsi的深度。在图2B所示的示范实施例中，掺杂翼片区208形成与沟道区205的基本上垂直的侧壁界面209A。基本上垂直的侧壁界面209A贯穿高度为Hsi的半导体翼片的大致整个厚度。在一个实施例中，掺杂翼片区208还形成与下方半导体衬底202的底部界面209B，底部界面209B与隔离区210的顶面基本上是平面的。在另一个实施例中，掺杂翼片区208形成与下方半导体衬底202的底部界面209C，底部界面209C低于隔离区210的顶面某个量DR。在任一种情况下，可存在横向倾斜离开栅叠层217的过渡界面245，其中过渡界面245优选地在栅电介质212之下不大于Hsi的距离开始。如图2A和图2B进一步所示，掺杂翼片区208的部分位于栅叠层217之下或下方有某个量XIM。在示范实施例中，掺杂翼片区208重叠栅叠层217的量对于高度Hsi(沿界面209A)是基本上恒定的，其中重叠的量在大于Hsi的深度处减小(形成过渡界面245)。
回到图1，在操作108，在栅叠层和半导体翼片的任一侧上形成隔离物。隔离物可使用常规电介质材料(包括但不限于氧化硅或氮化硅)形成。隔离物的宽度可基于所形成的多栅晶体管的设计要求来选择。图3A和图3B示出在栅叠层217的侧壁上形成的栅叠层隔离物319。栅叠层隔离物319的形成还在半导体翼片的侧壁上形成翼片隔离物318，具体来说，与掺杂翼片区208相邻，并且布置在隔离区210上。
回到图1，在操作110执行蚀刻过程以蚀刻掺杂翼片区。在特定实施例中，这种蚀刻过程还可形成栅叠层之下的空腔，其中随后可形成再生长源/漏区。蚀刻操作110使用补充离子注入过程中使用的掺杂剂的蚀刻剂，以便增加掺杂区的蚀刻速率。这使蚀刻过程能够以比未掺杂(或更轻掺杂)衬底的其余部分更快的速率去除掺杂翼片区。因此，通过蚀刻速率的适当增加，蚀刻过程能够有选择地去除基本上整个半导体翼片(即，整个沟道宽度Wsi上的整个高度Hsi，如图3A所示)，并且以良好剖面和深度控制仅保留沟道区。这包括底切栅叠层隔离物和栅电介质的掺杂区的部分，由此限定多栅晶体管的自对准源/漏翼片扩展。
按照本发明的一个示范实施例，蚀刻操作110包括与用作运载气体的NF3、HBr、SF6和Ar或He中的至少一个相结合使用氯化化学的干蚀刻。活性蚀刻剂种类的流率可在50与200标准立方厘米/分钟(SCCM)之间改变，而运载气体的流率可在150与400SCCM之间改变。可以范围从700W至1100W的功率使用高能量等离子体，其中具有小于100W的零或RF偏置。反应器压强的范围可从大约1帕斯卡(Pa)至大约2Pa。在其它实施例中，蚀刻操作110还包括湿蚀刻以便清洁并且进一步蚀刻半导体衬底202，其中去除了掺杂翼片区208。可使用本领域已知的用于清洁硅和氧化物材料的常规湿蚀刻化学。例如，可使用能够沿其结晶面去除硅的湿蚀刻化学。
图4A、图4B和图4C示出执行蚀刻操作110之后的多栅器件。在示范实施例中，以底切量XUC来蚀刻源/漏扩展空腔421，基于注入剖面XIM将底切量XUC控制为在大致等于Hsi的蚀刻深度上基本上恒定。在特定实施例中，对于15至40nm的栅长度范围，XUC的范围能够从大于0至12nm，而整个栅耦合沟道高度Hsi之上的栅叠层长度(平行于XUC的维)例如大约为25nm。在将采用传统尖注入并且再生长源/漏没有与沟道直接交界的一个备选实施例中，XUC为0。蚀刻源/漏翼片区并且形成在Hsi上大致恒定的源/漏扩展底切量XUC，这使比源/漏扩展空腔421具有小于Hsi的深度时或者底切量XUC减小(例如对于尖注入实施例为0)时更大量的应力能够施加到沟道区205。更大应力的施加具有增大多栅晶体管的Id,sat的效果。将源/漏翼片区向下蚀刻到Hsi还使可供随后再生长的源/漏区接触的沟道区205的面积最大化，以获得降低的Rexternal。
但是还发现，翼片下泄漏(沟道区205之下的源-漏泄漏)是接近沟道区205的翼片蚀刻深度的函数，这种泄漏在底切量XUC对于大于Hsi(从栅电介质212的界面测量)的深度未减小的情况下显著增加。因此，翼片蚀刻的深度和剖面应当在应力与沟道泄漏之间优化。因此，在提供基本上平底蚀刻剖面的一个实施例中，在蚀刻操作110期间被去除的掺杂翼片区208的厚度不应当大于Hsi，使得源/漏空腔420和源/漏扩展空腔421都与布置在栅叠层217(图2A)之下的相邻隔离区210基本上是平面的或齐平的。在某些实施例中，作为制造过程的结果，没有被栅叠层217覆盖的隔离区210的表面是凹进的。
对于注入和/或蚀刻被设计成提供远离沟道区205的锥形或倾斜剖面的实施例，在蚀刻操作110期间被去除的掺杂翼片区208的厚度在远离沟道区205的点可大于Hsi。对于这种实施例，使源/漏空腔420凹进(虚线422)在隔离区210的栅叠层保护面积以下的某个量，而接近沟道区205的源/漏扩展空腔421的一部分与布置在栅叠层之下(对应于大致等于Hsi的源/漏凹进深度)的隔离区210的面积基本上是平面的或齐平的。对于这个实施例，源/漏扩展空腔421的底切量XUC作为大于Hsi的阈值蚀刻深度的蚀刻深度的函数来减小(如422中的斜线所示)。
在操作112，去除翼片隔离物318。取决于实施例，隔离物去除操作112在掺杂翼片蚀刻操作110之前、在掺杂翼片蚀刻操作110期间或者在掺杂翼片蚀刻操作110之后执行。在图4A、图4B和图4C所示的实施例中，源/漏蚀刻操作110对于电介质材料是选择性的(例如，保持栅电极213的电介质封装)，并且栅叠层隔离物319和翼片隔离物318在蚀刻操作110之后都保留。在这种实施例中，翼片隔离物318保持为包围源/漏空腔420的电介质遮盖物。对于源/漏蚀刻操作110对电介质材料具有较小选择性的一个实施例，翼片隔离物318可能在掺杂翼片蚀刻操作110期间被部分或完全去除(在这种情况下，图1的操作110和112同时执行)。
对于翼片隔离物318的至少某个部分在操作110之后保留的实施例，翼片隔离物318按照保留栅叠层隔离物319和栅帽214的方式相对半导体衬底202优先被去除，如图5A和图5B进一步所示。在一个实施例中，各向同性蚀刻过程(干或湿)用于蚀刻翼片隔离物318。对于这类实施例，翼片隔离物318可从隔离区210的表面被蚀刻掉，而栅叠层隔离物319和栅帽214仅部分薄化。由于栅电极213在去除翼片隔离物318之后保持被封装，栅电极在后续源/漏再生长期间没有提供籽表面。
回到图1，在操作114，使用选择性外延沉积过程为包括源/漏扩展空腔421的源/漏空腔420填充材料，以便形成再生长源/漏翼片。在一个实施例中，如图6A和图6B所示，形成源/漏翼片618的材料在沟道区205上引起应变。按照特定实施例，形成再生长源/漏翼片618的材料包含硅，并且沿用衬底202的结晶度，但是具有与衬底202的晶格间距不同的晶格间距。晶格间距的差异在MOS晶体管的沟道区中引起拉伸或压缩应力，该应力通过在源和漏扩展空腔421中沉积硅合金来加强。如本领域的技术人员已知的，判定是引起拉伸应力还是压缩应力将取决于形成NMOS还是PMOS晶体管。
因此，外延沉积操作114在一个过程中再生长源/漏区和源/漏扩展。对于再生长源/漏区填充具有大于0的XUC的底切的实施例，外延再生长源/漏翼片618可具有比采用尖注入将掺杂剂放在至沟道的界面处的实施例(例如XUC为0)要陡的界面609A。换言之，外延再生长源/漏翼片618与沟道区205之间的界面609A由再生长过程明确限定。在界面609A的一侧上是外延沉积掺杂硅材料，而在界面609A的另一侧上是构成沟道区205的衬底材料。再生长源/漏翼片618中的掺杂剂可扩散到沟道区205中，但是这种扩散通过控制XUC维的位置(即，与沟道区205的界面209A的位置)以及通过优化EPI沉积和后续热处理的温度来设计。这使再生长源/漏区能够相对于常规技术使重掺杂源/漏材料非常接近沟道区205(即，底切量XUC可广泛地重叠栅叠层)。本领域的技术人员将会理解，这又使沟道长度能够缩小，而无需减小栅叠层的尺寸。
在一个实施例中，源/漏区再生长到至少Hsi的厚度。在另一个实施例中，源/漏区再生长到至少Wsi的宽度，并且优选地再生长到大于Wsi的宽度，如图6B所示。在高度Hsi并且比较接近沟道区205来形成再生长源/漏翼片618在沟道上给予大的流体静应力。如前面所述，这个应力增加沟道区205内的应变，由此增大沟道中的迁移率并且增大驱动电流。在去除了翼片隔离物318的示范实施例中，源/漏区无缺陷地或者以比采用侧壁生长限制可能的缺陷明显更少的缺陷来再生长。在翼片隔离物318不存在的情况下，再生长源/漏翼片618的横向外延生长是畅通无阻的，由此允许{111}小面的形成以及{111}平面上的持续生长，从而在隔离区210的一部分之上延伸，如图6A进一步所示。当然，外延生长小面与基础衬底202的晶体取向相关，使得不同衬底取向将得到不同外延小面。因此，再生长源/漏翼片618的宽度大于被去除的掺杂翼片区208的宽度。因此，沟道区205具有小于再生长源/漏翼片618的宽度的宽度Wsi。例如，再生长源/漏翼片618的宽度可以比Wsi要宽10%至100%之间，以便优化性能。在一个实施例中，再生长源/漏翼片618的宽度沿高度Hsi的至少一半大于Wsi。换言之，当形成再生长源/漏翼片618时，它到再生长源/漏厚度大约为1/2 Hsi时达到比Wsi要大的宽度。相对较宽的再生长源/漏翼片618提供其上可制作金属化触点的较大表面面积，由此相对于宽度等于Wsi的源/漏区减小Rexternal。再生长源/漏翼片618的较大宽度还增加置于沟道区205上的应变量。
在某些实施例中，硅合金用于再生长源/漏翼片618。合金可在沟道区205上给予应变。取决于实施例，合金可以是就地硼掺杂硅锗(例如，对于具有压缩应变沟道的PMOS多栅晶体管)、就地碳和磷掺杂硅(例如，对于具有拉伸应变沟道的NMOS多栅晶体管)或者就地磷掺杂硅。在备选实现中，可使用其它硅合金。例如，可使用的备选硅合金材料包括但不限于硅化镍、硅化钛、硅化钴，并且可采用硼和/或铝中的一个或多个来掺杂。在又一些实施例中，采用非硅材料(例如纯锗、锗酸盐等)。
对于一个NMOS晶体管实施例，再生长源/漏翼片618可填充有碳掺杂硅。可以外延地并且有选择地沉积碳掺杂硅。在其它实现中，碳掺杂硅还可采用磷来就地掺杂。碳浓度的范围可从0.5原子百分率至5.0原子百分率。磷浓度的范围可从5×1019/cm3至3×1021/cm3。碳掺杂硅的厚度的范围可从400                                                至1200。碳和磷掺杂硅可表示为(C,P)ySi(1-y)。掺杂(C,P)ySi(1-y)源和漏区的沉积可在化学汽相沉积反应器中使用共流(co-flown)或循环沉积和蚀刻顺序过程来执行。在一个示例中，通过基于硅烷(SiH4)、二甲基二氯硅烷(diclholorosilane)、乙硅烷、PH3、CH3SiH3和氯(Cl2)或HCl化学的循环沉积和蚀刻来形成膜。
对于一个PMOS晶体管实施例，再生长源/漏翼片618可填充有硅锗。可外延沉积硅锗。锗浓度的范围可从10原子百分率至80原子百分率。在其它实现中，硅锗还可采用硼来就地掺杂。硼浓度的范围可从2×1019/cm3至2×1021/cm3。硅锗的厚度的范围可从40至1500。掺杂硅锗的沉积可在CVD反应器、LPCVD反应器或者超高真空CVD(UHVCVD)中执行。反应器温度可处于600℃与800℃之间，并且反应器压力可处于1与760托之间。运载气体可由流率范围在10与50SLM之间的氢或氦来组成。
本领域的技术人员将会理解，多栅MOS晶体管可经过进一步处理，诸如置换栅氧化物过程、置换金属栅过程、退火或硅化(salicidation)过程，它们可进一步修改晶体管和/或提供必要的电互连。例如，在再生长源/漏翼片618的外延沉积之后，在操作116(图1)，层间电介质(ILD)可在多栅器件之上沉积和平面化，如图7进一步所示。由于去除了翼片隔离物318，所以ILD 723直接沉积在再生长源/漏翼片618的侧壁上，并且因此与栅叠层隔离物319的侧壁以及与再生长源/漏翼片618的位于高度Hsi之内的侧壁部分都接触。ILD 723可使用已知适用于集成电路结构的电介质层中的材料(例如低k电介质材料)来形成。这类电介质材料包括但不限于诸如二氧化硅(SiO2)和碳掺杂氧化物(CDO)之类的氧化物、氮化硅、诸如过氟化环丁烷或聚四氟乙烯之类的有机聚合物、氟硅酸盐玻璃(FSG)以及诸如硅倍半氧烷、硅氧烷或有机硅酸盐玻璃之类的有机硅酸盐。电介质层723可包括小孔或其它空隙，以便进一步降低其介电常数。
随后，对于使用置换金属栅过程的本发明的实施例，在操作118使用蚀刻过程去除栅叠层217，以便暴露在扩展空腔421中填充的再生长漏/源扩展618A。用于去除栅叠层217的层的方法是本领域中众所周知的。在备选实现中，仅去除栅电极213和栅帽214，以便暴露栅电介质212。图8示出在蚀刻掉栅叠层时形成的沟槽开口。
回到图1，如果去除了栅电介质层，则新栅电介质层可在操作120沉积到沟道区205之上的沟槽开口中。在这里可使用上述高k电介质材料，例如氧化铪。还可使用相同的沉积过程。栅电介质层的置换可用于解决可能在应用干和湿蚀刻过程期间对原始栅电介质层已发生的任何损坏。然后，金属栅电极层可沉积在栅电介质层之上。常规金属沉积过程可用于形成金属栅电极层，诸如CVD、ALD、PVD、非电解镀层或电镀。图9示出高k栅电介质层924和栅电极层926，它们已被沉积到沟槽开口中，使得再生长漏/源扩展618A布置在栅电介质层924之下(在与栅电极层926的侧壁和栅叠层隔离物319相接触的栅电介质层924的一部分下方，或者在布置于栅电极926下方的栅电介质层924的一部分之下)。
栅电极层926可由P型功函数金属或N型功函数金属组成，取决于晶体管是PMOS还是NMOS晶体管。在一些实现中，PMOS晶体管被形成，并且可用于形成P型功函数金属层的材料包括但不限于钌、钯、铂、钴、镍和导电金属氧化物(例如氧化钌)。P型金属层将使得能够形成功函数在大约4.9eV与大约5.2eV之间的PMOS栅电极。备选地，在一些实现中，NMOS晶体管被形成，并且可用于形成N型功函数金属层的材料包括但不限于铪、锆、钛、钽、铝及其合金，例如，包括这些元素的金属碳化物，即，碳化铪、碳化锆、碳化钛、碳化钽和碳化铝。N型金属层将使得能够形成功函数在大约3.9eV与大约4.2eV之间的NMOS栅电极。在一些实现中，可沉积两个或更多金属栅电极层。例如，可沉积功函数金属，接着是金属栅电极填充金属(例如铝金属)。当然，按照本领域的惯例也可采用掺杂多晶硅、硅化硅(silicided silicon)等。
因此，公开了一种具有自对准外延再生长源/漏区的多栅晶体管，这些外延再生长源/漏区减小了多栅晶体管的总电阻，并且由于与减小的沟道硅体积相结合的增加的掺杂硅体积(例如硼掺杂硅锗体积)而增加了沟道应变。外延源和漏扩展大致延伸了整个翼片高度Hsi，形成沟道区与源/漏区之间的陡边界，并且具有更易于控制的掺杂浓度，从而产生更优化的源-漏剖面。
包括“摘要”中所述内容的本发明的说明性实施例的以上描述并不是要穷举或者将本发明局限于所公开的精确形式。虽然本文为了便于说明而描述本发明的具体实现和示例，但是相关领域的技术人员会知道，在本发明的范围内各种等效修改是可能的。本发明的范围完全由以下权利要求来确定，权利要求将按照权利要求释义的已制定原则来解释。

Claims (10)

1.一种多栅晶体管，包括：
栅叠层，所述栅叠层包括栅电介质以及布置在从半导体衬底延伸的半导体翼片的沟道区之上的栅电极，所述沟道区具有栅耦合沟道侧壁高度Hsi；
布置在所述衬底上的再生长源/漏半导体翼片，所述再生长源/漏半导体翼片包括与所述沟道区相邻的源/漏扩展区，其中所述源/漏扩展区和所述沟道区沿等于侧壁高度Hsi的高度形成界面，其中所述源/漏扩展区沿垂直于晶体管沟道宽度Wsi的维底切所述栅叠层跨Hsi基本上恒定的量，并且其中所述源/漏扩展区在接近所述沟道区处具有大约等于侧壁高度Hsi的深度，并且在远离所述沟道区处具有大于Hsi的深度。
2.根据权利要求1所述的多栅晶体管，其中，所述源/漏扩展区底切所述栅叠层，沿垂直于晶体管沟道宽度Wsi的维具有底切长度XUC，所述晶体管沟道宽度Wsi跨侧壁高度Hsi是恒定的。
3.根据权利要求2所述的多栅晶体管，其中，所述源/漏扩展区比Hsi更深地底切所述栅叠层，底切长度小于所述底切长度XUC。
4.根据权利要求1所述的多栅晶体管，其中，沿着平行于晶体管沟道宽度Wsi的维的再生长源/漏翼片宽度大于所述沟道宽度Wsi。
5.根据权利要求4所述的多栅晶体管，其中，当形成所述再生长源/漏翼片时，到再生长源/漏厚度为二分之一侧壁高度Hsi时，所述再生长源/漏翼片达到比所述沟道宽度Wsi要大的宽度。
6.根据权利要求1所述的多栅晶体管，其中，所述栅叠层的横向相对侧与电介质隔离物相邻，并且其中，层间电介质ILD与所述电介质隔离物的外侧壁以及与位于所述侧壁高度Hsi以内的再生长源/漏翼片的侧壁部分都接触。
7.根据权利要求1所述的多栅晶体管，其中，所述栅叠层包括高k栅电介质层和金属栅电极，其中，再生长源/漏翼片区包括碳和磷掺杂硅或者硼掺杂硅锗以使所述沟道区应变。
8.根据权利要求7所述的多栅晶体管，其中，所述源/漏扩展区在所述高k栅电介质层下方，并且所述源/漏扩展区与所述高k栅电介质层之间的距离大于零。
9.根据权利要求1所述的多栅晶体管，其中，再生长源/漏翼片区沿平行于晶体管沟道宽度Wsi的维外延生长，使得所述再生长源/漏翼片区的最大宽度大于沟道宽度Wsi，所述再生长源/漏翼片区沿用所述衬底的结晶度。
10.根据权利要求9所述的多栅晶体管，其中，再生长源/漏翼片的宽度在侧壁高度Hsi的二分之一处大于沟道宽度Wsi。
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