CN104821308A - 半导体装置以及半导体装置的制造方法 - Google Patents
半导体装置以及半导体装置的制造方法 Download PDFInfo
- Publication number
- CN104821308A CN104821308A CN201510023552.9A CN201510023552A CN104821308A CN 104821308 A CN104821308 A CN 104821308A CN 201510023552 A CN201510023552 A CN 201510023552A CN 104821308 A CN104821308 A CN 104821308A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014015829A JP6163436B2 (ja) | 2014-01-30 | 2014-01-30 | 半導体装置および半導体装置の製造方法 |
JP2014-015988 | 2014-01-30 | ||
JP2014015988A JP6081387B2 (ja) | 2014-01-30 | 2014-01-30 | 半導体装置および半導体装置の製造方法 |
JP2014-015829 | 2014-07-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104821308A true CN104821308A (zh) | 2015-08-05 |
CN104821308B CN104821308B (zh) | 2018-10-16 |
Family
ID=53679723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510023552.9A Active CN104821308B (zh) | 2014-01-30 | 2015-01-16 | 半导体装置以及半导体装置的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10083893B2 (zh) |
CN (1) | CN104821308B (zh) |
TW (1) | TWI601284B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106960871A (zh) * | 2017-03-16 | 2017-07-18 | 浙江大学 | 一种带沟槽阵列和空腔的碳化硅衬底结构 |
CN111081666A (zh) * | 2019-12-12 | 2020-04-28 | 联合微电子中心有限责任公司 | 一种减小热应力的tsv结构及其形成方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9666507B2 (en) * | 2014-11-30 | 2017-05-30 | United Microelectronics Corp. | Through-substrate structure and method for fabricating the same |
JP6509635B2 (ja) | 2015-05-29 | 2019-05-08 | 東芝メモリ株式会社 | 半導体装置、及び、半導体装置の製造方法 |
JP2017168528A (ja) | 2016-03-14 | 2017-09-21 | 東芝メモリ株式会社 | 半導体製造方法 |
JP2019145737A (ja) * | 2018-02-23 | 2019-08-29 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置および半導体装置の製造方法 |
JP2022047357A (ja) * | 2020-09-11 | 2022-03-24 | キオクシア株式会社 | 半導体装置およびその製造方法 |
WO2022218610A1 (en) * | 2021-04-12 | 2022-10-20 | Ams-Osram Ag | Semiconductor device with sealed through-substrate via and method for producing thereof |
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CN1592965A (zh) * | 2001-12-19 | 2005-03-09 | 国际商业机器公司 | 利用垂直连接的芯片和晶片集成工艺 |
US20080315422A1 (en) * | 2007-06-20 | 2008-12-25 | John Boyd | Methods and apparatuses for three dimensional integrated circuits |
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JP2012142414A (ja) * | 2010-12-28 | 2012-07-26 | Panasonic Corp | 半導体装置及びその製造方法並びにそれを用いた積層型半導体装置 |
US20120276733A1 (en) * | 2011-04-27 | 2012-11-01 | Elpida Memory, Inc. | Method for manufacturing semiconductor device |
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US6103585A (en) * | 1998-06-09 | 2000-08-15 | Siemens Aktiengesellschaft | Method of forming deep trench capacitors |
JP3748516B2 (ja) | 2001-04-23 | 2006-02-22 | シャープ株式会社 | 半導体装置および無線通信システム |
US6743727B2 (en) * | 2001-06-05 | 2004-06-01 | International Business Machines Corporation | Method of etching high aspect ratio openings |
JP2003142484A (ja) * | 2001-10-31 | 2003-05-16 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP3964263B2 (ja) | 2002-05-17 | 2007-08-22 | 株式会社デンソー | ブラインドビアホール充填方法及び貫通電極形成方法 |
JP4376715B2 (ja) * | 2004-07-16 | 2009-12-02 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP4552770B2 (ja) | 2005-06-21 | 2010-09-29 | パナソニック電工株式会社 | 半導体基板への貫通配線の形成方法 |
US7892972B2 (en) | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
JP2007280997A (ja) | 2006-04-03 | 2007-10-25 | Matsushita Electric Ind Co Ltd | 多層プリント配線基板の製造方法 |
EP1890524A4 (en) | 2006-04-03 | 2009-07-01 | Panasonic Corp | MULTILAYER PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME |
US7709320B2 (en) * | 2006-06-28 | 2010-05-04 | International Business Machines Corporation | Method of fabricating trench capacitors and memory cells using trench capacitors |
US7919834B2 (en) | 2007-12-04 | 2011-04-05 | International Business Machines Corporation | Edge seal for thru-silicon-via technology |
KR20100020718A (ko) | 2008-08-13 | 2010-02-23 | 삼성전자주식회사 | 반도체 칩, 그 스택 구조 및 이들의 제조 방법 |
US8258010B2 (en) | 2009-03-17 | 2012-09-04 | Stats Chippac, Ltd. | Making a semiconductor device having conductive through organic vias |
JP5600919B2 (ja) | 2009-10-06 | 2014-10-08 | セイコーエプソン株式会社 | 半導体装置 |
CN102148202B (zh) * | 2010-02-09 | 2016-06-08 | 精材科技股份有限公司 | 晶片封装体及其形成方法 |
US8580687B2 (en) * | 2010-09-30 | 2013-11-12 | Infineon Technologies Ag | Semiconductor structure and method for making same |
CN102543835B (zh) | 2010-12-15 | 2015-05-13 | 中国科学院微电子研究所 | 开口的填充方法 |
JP5568811B2 (ja) | 2011-04-01 | 2014-08-13 | 学校法人 関西大学 | 基板中間体、基板及び貫通ビア電極形成方法 |
JP5228094B2 (ja) | 2011-08-29 | 2013-07-03 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
JP5953701B2 (ja) | 2011-10-27 | 2016-07-20 | 富士通株式会社 | 接続基板、半導体装置、接続基板の製造方法 |
KR20130053338A (ko) * | 2011-11-15 | 2013-05-23 | 삼성전자주식회사 | Tsv 구조를 구비한 집적회로 소자 |
JP2012169669A (ja) | 2012-05-28 | 2012-09-06 | Renesas Electronics Corp | 半導体装置 |
JP5826782B2 (ja) * | 2013-03-19 | 2015-12-02 | 株式会社東芝 | 半導体装置の製造方法 |
US9484325B2 (en) * | 2013-10-09 | 2016-11-01 | Invensas Corporation | Interconnections for a substrate associated with a backside reveal |
US9117879B2 (en) * | 2013-12-30 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
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2014
- 2014-09-10 US US14/482,395 patent/US10083893B2/en active Active
-
2015
- 2015-01-05 TW TW104100082A patent/TWI601284B/zh active
- 2015-01-16 CN CN201510023552.9A patent/CN104821308B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1592965A (zh) * | 2001-12-19 | 2005-03-09 | 国际商业机器公司 | 利用垂直连接的芯片和晶片集成工艺 |
US20080315422A1 (en) * | 2007-06-20 | 2008-12-25 | John Boyd | Methods and apparatuses for three dimensional integrated circuits |
US20090280643A1 (en) * | 2008-05-06 | 2009-11-12 | International Business Machines Corporation | Optimal tungsten through wafer via and process of fabricating same |
TW201145486A (en) * | 2010-02-23 | 2011-12-16 | Qualcomm Inc | Semiconductor device with vias having more than one material |
JP2012142414A (ja) * | 2010-12-28 | 2012-07-26 | Panasonic Corp | 半導体装置及びその製造方法並びにそれを用いた積層型半導体装置 |
US20120276733A1 (en) * | 2011-04-27 | 2012-11-01 | Elpida Memory, Inc. | Method for manufacturing semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106960871A (zh) * | 2017-03-16 | 2017-07-18 | 浙江大学 | 一种带沟槽阵列和空腔的碳化硅衬底结构 |
CN111081666A (zh) * | 2019-12-12 | 2020-04-28 | 联合微电子中心有限责任公司 | 一种减小热应力的tsv结构及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US10083893B2 (en) | 2018-09-25 |
CN104821308B (zh) | 2018-10-16 |
TWI601284B (zh) | 2017-10-01 |
US20150214134A1 (en) | 2015-07-30 |
TW201530755A (zh) | 2015-08-01 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
EXSB | Decision made by sipo to initiate substantive examination | ||
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TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20170818 Address after: Tokyo, Japan Applicant after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Applicant before: Toshiba Corp. |
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GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Pangea Co.,Ltd. |
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TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220126 Address after: Tokyo Patentee after: Pangea Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |