CN107452714A - 形成低电阻率贵金属互连的装置及方法 - Google Patents

形成低电阻率贵金属互连的装置及方法 Download PDF

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CN107452714A
CN107452714A CN201710398591.6A CN201710398591A CN107452714A CN 107452714 A CN107452714 A CN 107452714A CN 201710398591 A CN201710398591 A CN 201710398591A CN 107452714 A CN107452714 A CN 107452714A
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group
barrier layer
groove
interconnection
air gap
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CN107452714B (zh
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张洵渊
法兰克·W·蒙特
埃罗尔·特德·莱恩
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GlobalFoundries US Inc
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Abstract

本发明涉及形成低电阻率贵金属互连的装置及方法，其提供制造集成电路装置以形成低电阻率互连的装置及方法。一种方法包括例如：获得中间半导体互连装置，该中间半导体互连装置具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；沿该半导体互连装置的顶部表面沉积阻挡层；在该阻挡层的顶部表面上方沉积并退火金属互连材料，其中，该金属互连材料填充该组沟槽及该组过孔；平坦化该中间半导体互连装置的顶部表面；暴露该组沟槽与该组过孔之间的该阻挡层的一部分；以及沉积介电覆盖层。本发明还揭露通过该方法形成的中间装置。

Description

形成低电阻率贵金属互连的装置及方法
技术领域
本发明涉及半导体装置以及制造半导体装置的方法，尤其涉及形成具有贵金属的低电阻率金属互连的装置及方法。
背景技术
对于5纳米及以下节点，随着对更小电路结构及更快装置性能的需求不断增加，铜线电阻率开始攀升，从而降低该些节点的性能。5纳米节点及更小节点的开发将可能需要降低该些节点中的线的电阻率。
因此，可能希望开发在此类小尺寸下与铜相比具有较低电阻率的线的节点制造方法。
发明内容
为克服现有技术的缺点并提供额外的优点，在一个态样中提供一种方法，该方法包括例如：获得中间半导体互连装置，该中间半导体互连装置具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；沿该半导体互连装置的顶部表面沉积阻挡层；在该阻挡层的顶部表面上方沉积金属互连材料，其中，该金属互连材料填充该组沟槽及该组过孔；退火该金属互连材料；平坦化该中间半导体互连装置的顶部表面，以移除该组沟槽及该组过孔上方的该金属互连材料；暴露该组沟槽与该组过孔之间的该阻挡层的一部分；以及在该阻挡层的一组外表面上及该中间半导体互连装置上方沉积介电覆盖层。
在另一个态样中，提供一种中间装置，其包括例如：衬底；覆盖层；介电矩阵；一组过孔，延伸穿过该覆盖层；一组沟槽，延伸进入该介电矩阵中，其中，该组沟槽及该组过孔包括贵金属；以及介电覆盖层。
附图说明
本发明的一个或多个态样被特别指出并在说明书的结束处的声明中被明确称为示例。从下面结合附图所作的详细说明可清楚本发明的上述及其它目的、特征以及优点，该些附图中：
图1显示依据本发明的一个或多个态样用以形成中间半导体互连结构的方法的一个实施例；
图2显示依据本发明的一个或多个态样具有衬底、覆盖层以及包括一组沟槽及一组过孔的介电矩阵的中间半导体互连结构的一个实施例的剖切立视图；
图3显示依据本发明的一个或多个态样在沉积阻挡层及金属互连材料以后的图2的结构；
图4显示依据本发明的一个或多个态样在平坦化该中间半导体互连结构的顶部表面以后的图3的结构；
图5显示依据本发明的一个或多个态样在沉积牺牲介电覆盖层以后的图4的结构；
图6显示依据本发明的一个或多个态样在沉积阻挡掩膜并形成开口以后的图5的结构；
图7显示依据本发明的一个或多个态样在形成一组气隙并移除该牺牲介电覆盖层及该阻挡掩膜以后的图6的结构；
图8a显示依据本发明的一个或多个态样在氧化所暴露的阻挡层以后的图7的结构；
图8b显示依据本发明的一个或多个态样在移除所暴露的阻挡层以后的图7的结构；
图9a显示依据本发明的一个或多个态样在围绕该氧化暴露阻挡层沉积介电覆盖层以后的图8a的结构；
图9b显示依据本发明的一个或多个态样在移除该暴露阻挡层之后接着沉积介电覆盖层以后的图8b的结构；
图10显示依据本发明的一个或多个态样具有衬底、覆盖层、介电矩阵、一组沟槽、一组过孔以及介电覆盖层的中间装置的一个实施例的剖切立视图；
图11显示依据本发明的一个或多个态样具有一组气隙的图10的装置；
图12显示具有围绕该组过孔及该组沟槽的阻挡层的图11的装置。
主要组件符号说明
100至170 步骤
200 装置或中间半导体装置
210 衬底
220 覆盖层
230 介电矩阵
242 过孔
244 沟槽
250 阻挡层
255 阻挡层或部分
260 金属互连材料
270 牺牲介电覆盖层
272 阻挡掩膜
280 气隙
290 介电覆盖层
900 中间装置。
具体实施方式
下面通过参照附图中所示的非限制性例子来更加充分地解释本发明的态样及其特定的特征、优点以及细节。省略对已知材料、制造工具、制程技术等的说明，以免在细节上不必要地模糊本发明。不过，应当理解，当说明本发明的实施例时，详细说明及具体例子仅作为示例，而非限制。本领域的技术人员将会从本揭露中了解在基础的发明概念的精神和/或范围内的各种替代、修改、添加和/或布局。还要注意，下面参照附图，为方便理解，该些附图并非按比例绘制，其中，不同附图中所使用的相同附图标记表示相同或类似的组件。
一般来说，本文揭露特定集成电路，其提供相对上述的现有半导体装置及制程的优点。有利地，本文中所揭露的集成电路装置制程提供与先前可能使用传统铜线相比具有较低线电阻率的半导体装置。
在一个态样中，在一个实施例中，如图1中所示，依据本发明的一个或多个态样的集成电路装置形成制程可包括例如：获得具有衬底、覆盖层以及包括一组沟槽及一组过孔的介电矩阵的中间半导体互连装置100；沿该半导体互连装置的顶部表面沉积阻挡层110；在该阻挡层的顶部表面上方沉积金属互连材料120；退火该金属互连材料130；平坦化该中间半导体互连装置的顶部表面140；在该中间半导体互连装置上方沉积牺牲介电覆盖层及阻挡掩膜150；形成一组气隙并移除该牺牲介电覆盖层及该阻挡掩膜160；以及在该阻挡层的一组外表面上及该中间半导体互连装置上方沉积介电覆盖层170。
图2至8显示(仅示例)依据本发明的一个或多个态样的半导体装置形成制程的一部分及中间半导体互连装置的一部分的一个详细实施例。要注意的是，这些附图并非按比例绘制，以促进理解本发明，且不同附图中所使用的相同附图标记表示相同或类似的组件。
图2显示处于中间半导体制造阶段的中间半导体装置200的一部分。已依据所制造的装置200的设计通过初始装置制程步骤对装置200进行了处理。例如，装置200可包括例如衬底210，在衬底210上设有覆盖层220，该覆盖层可包括介电材料。衬底210可为任意合适的材料，例如硅。另外，在衬底210或覆盖层220上可沉积介电矩阵230。介电矩阵230可包括一种或多种介电材料，且可包括材料混合矩阵或多个材料层(未显示)。介电矩阵230可包括一组过孔242及一组沟槽244。如图2中所示，该组过孔242可延伸穿过覆盖层220至下方特征，而该组沟槽244可仅延伸进入介电矩阵230中。
在另一个实施例中(未显示)，装置200的衬底可为例如绝缘体上覆硅(silicon oninsulator；SOI)衬底(未显示)。例如，该SOI衬底可包括隔离层(未显示)，该隔离层可为局部埋置氧化物区(buride oxide；BOX)或任意合适的材料以电性隔离晶体管，与栅极结构对齐。在一些实施例中，该装置为集成电路(integrated circuit；IC)的后端工艺(back endof line；BEOL)部分的一部分。
如图2中所示，通过使用光刻及蚀刻制程，可已于介电矩阵230中蚀刻介电矩阵230和/或覆盖层220，以定义该组过孔242及该组沟槽244。该蚀刻可通过任意合适的蚀刻制程执行，例如定向反应离子蚀刻(reactive ion etching；RIE)。
如图3中所示，通过原子层沉积(atomic layer deposition；ALD)、化学气相沉积(chemical vapor deposition；CVD)、物理气相沉积(physical vapor deposition；PVD)或当前已知或以后开发的任意其它合适的沉积技术，可沿装置200的顶部表面沉积阻挡层250。例如，阻挡层250可具有钽(Ta)、钛(Ti)或锰(Mn)组分并可小于约3纳米(nm)厚，且在一些实施例中，小于约1.5纳米厚。如图3中所示，可使用能够形成与变化表面共形的小于3纳米的一致薄膜或薄层的任意沉积来沉积阻挡层250。
也如图3中所示，在一些实施例中，在沉积阻挡层250之后，接着通过ALD或CVD在阻挡层250的顶部表面上方沉积金属互连材料260。在一些实施例中，该金属互连材料沉积约10纳米与约20纳米之间的厚度，以使其填充该组过孔242(图2)及该组沟槽244(图2)。金属互连材料260可包括任意贵金属，包括但不限于：钌(Ru)、铌(Nb)、铑(Rh)、铱(Ir)、以及铂(PT)。在沉积金属互连材料260之后，接着在约350C至约500C范围内热退火该材料可帮助固化该材料。尽管传统上铜(Cu)为该互连材料的选择，但随着装置的线宽不断变小，铜的电阻率开始增加。相比之下，贵金属在较小尺寸可具有更理想的电阻率。
例如，与在20纳米与6纳米之间不断爬升的铜不同，Ru薄膜从20纳米至6纳米具有几乎恒定的电阻率。在约5纳米，Ru可具有与Cu几乎相同的电阻率，且在5纳米以下可具有较低的电阻率。另外，不像许多其它互连材料，Ru不会出现因电迁移(electromigration；EM)而导致的失效。贵金属薄膜的时间相关介电击穿(time dependent dielectricbreakdown；TDDB)可比铜好至少10倍。不过，如下面进一步说明，通过增加与金属互连材料260相邻的层(例如阻挡层250)的电阻，可更进一步降低金属互连材料260的电阻率。因此，就组成改变阻挡层250来增加电阻可降低金属互连材料260的电阻。
如图4中所示，通过使用化学机械抛光，可平坦化并抛光装置200的顶部表面，移除多余金属互连材料260并提供光滑表面，以在该光滑表面上继续装置制造。在一个实施例中，在此平坦化之后，接着可氧化阻挡层250(未显示)，以降低金属互连材料260的电阻。通过在惰性环境空气中(在一些情况下具有小于约1％氧)退火该结构可实现氧化阻挡层250，而不破坏金属互连材料260。在此实施例中，可显着降低金属互连材料260的电阻。
如图5中所示，在装置200上方可沉积牺牲介电覆盖层270。由于此覆盖层用于遮蔽下方结构且不用于最终装置的运行，因此将其视为牺牲。
如图6中所示，例如通过使用标准光刻及蚀刻技术，在牺牲介电覆盖层270的顶部表面上可形成阻挡掩膜272，且通过使用任意光刻技术可移除牺牲介电覆盖层270，以在该组沟槽244及该组过孔242上方暴露并形成一个或多个开口。在使用阻挡掩膜272之后，接着可执行移除过孔蚀刻技术。
如图7中所示，例如通过在介电矩阵230内形成一组气隙280可暴露该组过孔242与该组沟槽244的至少其中一些之间的阻挡层250的一部分。在一些实施例中，例如，可破坏介电矩阵230的区域(例如该组沟槽244与该组过孔242的其中一些或全部之间的区域)，以形成该组气隙280。在一些实施例中，使用H2及N2等离子体来破坏介电矩阵230。例如，通过使用稀释氢氟酸可移除被破坏的材料，保留该组过孔242与该组沟槽244的至少其中一些之间的气隙280。同时，通过使用同一材料可移除牺牲介电覆盖层270及阻挡掩膜272。
如图8a中所示，形成气隙280使阻挡层250的部分255暴露，通常为覆盖金属互连材料260(其填充该组过孔242及该组沟槽244)的侧表面的全部或其中一些的部分。可氧化阻挡层255的这些部分，以增加其电阻率，从而有效降低金属互连材料260的电阻率。此氧化可通过暴露于湿化学发生。在一些实施例中，其中，阻挡层250包括Ta或Ti金属组分，该湿化学可包括过氧化氢(H2O2)。金属互连材料260较难以氧化，尤其在室温下，因此有效地，仅暴露阻挡层250氧化。
在替代实施例中，如图8b中所示，可移除而不是氧化阻挡层250的暴露部分。移除阻挡层250允许金属互连材料260与介电覆盖层290直接相接(图9b)，后面将作说明。介电覆盖层260将具有与阻挡层250相比较高的电阻，因而降低最终装置中的金属互连材料260的电阻。阻挡层250的该暴露部分可通过暴露于湿化学来移除或者通过任意必要技术的蚀刻来移除。
如图9a中所示，在阻挡层250的一组外表面上以及中间半导体互连装置200上方可沉积介电覆盖层290。介电覆盖层290可部分涂布阻挡层250，但保留气隙280(图7)完好并被介电覆盖层290覆盖。
如图9b中所示，介电覆盖层290可涂布所暴露的金属互连材料260，也保留气隙280(图7)完好。与图9a相比，该介电覆盖层的材料(其可包括SiN或其它介电材料)将充当金属互连材料260的界面。此材料可经选择而具有高电阻率，其将降低最终IC中的金属互连材料260的有效电阻。
图10显示中间装置900，依据一些实施例，该中间装置包括衬底210、覆盖层220、介电矩阵230、延伸穿过覆盖层220的一组过孔242、延伸进入介电矩阵230中的一组沟槽244、以及介电覆盖层290。在这些实施例中，该组沟槽244及该组过孔242包括贵金属。其它材料如上所述。
如图11中所示，中间装置900可包括位于该组过孔242与该组沟槽244的至少其中一些之间的一组气隙280。可以看出，当具有气隙280时，介电覆盖层290可作为气隙280的衬里。
如图12中所示，阻挡层250围绕该组过孔242及该组沟槽244，不过，在该组气隙280附近的阻挡层255(在非正式附图中显示为橙色)是上面所揭露的具有Ta或Ti组分的阻挡层材料的其中一种的氧化材料。在一些实施例中，可氧化整个阻挡层250。
应当了解，上面所揭露的新颖的中间半导体互连装置及其形成方法降低后端工艺(BEOL)互连形成及线的电阻。依据实施例，通过改变该互连本身的材料来降低该装置的表面散射，且增加阻挡层的电阻降低该互连材料的最终电阻。由于电迁移现象减少，贵金属作为互连材料是有利的，部分因为该金属的较高熔点。另外，贵金属更加抗氧化，从而使阻挡层更容易氧化。
本文中所使用的术语仅是出于说明特定实施例的目的，并非意图限制本发明。除非上下文中明确指出，否则本文中所使用的单数形式“一个”以及“该”也意图包括复数形式。还应当理解，术语“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(以及任意形式的包含)都是开放式连接动词。因此，“包括”、“具有”或“包含”一个或多个步骤或组件的方法或装置具有那些一个或多个步骤或组件，但并不限于仅仅具有那些一个或多个步骤或组件。类似地，“包括”、“具有”或“包含”一个或多个特征的一种方法的步骤或一种装置的组件具有那些一个或多个特征，但并不限于仅仅具有那些一个或多个特征。而且，以特定方式配置的装置或结构至少以那种方式配置，但也可以未列出的方式配置。
下面的权利要求中的所有方式或步骤加功能元素的相应结构、材料、动作及等同(如果有的话)意图包括结合具体请求保护的其它请求保护的元素执行该功能的任意结构、材料或动作。本发明的说明用于示例及说明目的，而非意图详尽无遗或限于所揭露形式的发明。许多修改及变更将对于本领域的普通技术人员显而易见，而不背离本发明的范围及精神。该些实施例经选择及说明以最佳解释本发明的一个或多个态样的原理以及实际应用，并使本领域的普通技术人员能够理解针对各种实施例具有适合所考虑的特定应用的各种变更的本发明的一个或多个态样。

Claims (20)

1.一种方法，包括：
获得中间半导体互连装置，该中间半导体互连装置具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；
沿该半导体互连装置的顶部表面沉积阻挡层；
在该阻挡层的顶部表面上方沉积金属互连材料，其中，该金属互连材料填充该组沟槽及该组过孔；
退火该金属互连材料；
平坦化该中间半导体互连装置的顶部表面，以移除该组沟槽及该组过孔上方的该金属互连材料；
暴露该组沟槽与该组过孔之间的该阻挡层的一部分；以及
在该阻挡层的一组外表面上及该中间半导体互连装置上方沉积介电覆盖层。
2.如权利要求1所述的方法，还包括：
在该中间半导体互连装置上方沉积牺牲介电覆盖层及阻挡掩膜；
在该组沟槽与该组过孔的至少其中一部分之间形成一组气隙，移除该牺牲介电覆盖层及该阻挡掩膜；以及
在所述形成该组气隙之后，接着氧化通过所述形成该组气隙而暴露的一组区域中的该阻挡层。
3.如权利要求2所述的方法，其中，通过将由所述形成暴露的该组区域暴露于湿化学来实施该氧化。
4.如权利要求3所述的方法，其中，该湿化学包括H2O2。
5.如权利要求1所述的方法，还包括：
在该中间半导体互连装置上方沉积牺牲介电覆盖层及阻挡掩膜；
在该组沟槽与该组过孔的至少其中一部分之间形成一组气隙，移除该牺牲介电覆盖层及该阻挡掩膜；以及
在所述形成该组气隙之后，接着移除通过所述形成该组气隙而暴露的一组区域中的该阻挡层。
6.如权利要求5所述的方法，其中，通过将由所述形成暴露的该组区域暴露于湿化学来实施该移除。
7.如权利要求1所述的方法，还包括：
在该中间半导体互连装置上方沉积牺牲介电覆盖层及阻挡掩膜；
在该组沟槽与该组过孔的至少其中一部分之间形成一组气隙，移除该牺牲介电覆盖层及该阻挡掩膜；以及
在所述平坦化该中间半导体互连装置的该顶部表面之后，接着通过在有氧的周围空气中退火来氧化该阻挡层。
8.如权利要求7所述的方法，其中，该氧小于1％。
9.如权利要求1所述的方法，其中，该金属互连材料包括贵金属。
10.如权利要求1所述的方法，其中，该阻挡层包括小于约3纳米的厚度的具有Ta、Ti或Mn元素的由金属组成的层，以及其中，该金属互连材料沉积约10纳米与约20纳米之间的厚度。
11.如权利要求10所述的方法，其中，该阻挡层包括小于约1.5纳米的厚度。
12.如权利要求10所述的方法，其中，该阻挡层通过包括原子层沉积(ALD)、化学气相沉积(CVD)以及物理气相沉积(PVD)的群组的其中之一来沉积，以及其中，该金属互连材料通过包括化学气相沉积及原子层沉积的群组的其中之一来沉积。
13.如权利要求1所述的方法，其中，该退火发生于约350C至约500C。
14.如权利要求1所述的方法，其中，所述沉积该介电覆盖层在该组过孔与该组沟槽之间的区域中形成一组气隙。
15.一种中间装置，包括：
衬底；
覆盖层；
介电矩阵；
一组过孔，延伸穿过该覆盖层；
一组沟槽，延伸进入该介电矩阵中，其中，该组沟槽及该组过孔包括贵金属；以及
介电覆盖层。
16.如权利要求15所述的装置，还包括：
一组气隙，位于该组过孔与该组沟槽的至少其中一些之间。
17.如权利要求16所述的装置，还包括：
阻挡层，围绕该组过孔及该组沟槽，其中，在该组气隙附近的该阻挡层包括氧化材料。
18.如权利要求17所述的装置，其中，不在该组气隙附近的该阻挡层包括Ta、Ti或Mn元素。
19.如权利要求15所述的装置，还包括：
阻挡层，围绕该组过孔及该组沟槽，其中，该阻挡层包括氧化材料。
20.如权利要求19所述的装置，其中，该阻挡层包括氧化的含Ta材料或氧化的含Ti材料。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10229851B2 (en) 2016-08-30 2019-03-12 International Business Machines Corporation Self-forming barrier for use in air gap formation
US10796949B2 (en) 2018-10-19 2020-10-06 International Business Machines Corporation Airgap vias in electrical interconnects
KR102192311B1 (ko) * 2019-02-19 2020-12-17 성균관대학교산학협력단 구리 인터커넥터, 이의 제조방법 및 이를 포함하는 반도체 장치
US11239165B2 (en) * 2020-03-10 2022-02-01 International Business Machines Corporation Method of forming an interconnect structure with enhanced corner connection
CN113539948B (zh) * 2020-04-20 2024-01-26 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
TW202236550A (zh) * 2020-11-25 2022-09-16 美商應用材料股份有限公司 用於低溫處理的補充能量
US20220246519A1 (en) * 2021-02-03 2022-08-04 Changxin Memory Technologies, Inc. Interconnection structure and manufacturing method thereof and semiconductor structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0506710A1 (en) * 1989-12-22 1992-10-07 Micro Power System, Inc. Process enhancement using molybdenum plugs in fabricating integrated circuits
KR20030083174A (ko) * 2002-04-19 2003-10-30 아남반도체 주식회사 반도체 소자의 에어갭 형성방법
KR20040000704A (ko) * 2002-06-25 2004-01-07 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성 방법
US6723634B1 (en) * 2002-03-14 2004-04-20 Advanced Micro Devices, Inc. Method of forming interconnects with improved barrier layer adhesion
CN101431046A (zh) * 2007-10-09 2009-05-13 应用材料股份有限公司 在用于减少rc延迟的介电层中产生气隙的方法和装置
US20110101529A1 (en) * 2009-10-29 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier layer for copper interconnect
CN104025262A (zh) * 2011-12-29 2014-09-03 英特尔公司 具有罩层的气隙互连以及形成的方法
US20140264908A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene gap filling process
CN104364903A (zh) * 2012-06-01 2015-02-18 高通股份有限公司 具有单向金属层的堆叠内有混合的金属叉指取向的金属叉指电容器
CN104576518A (zh) * 2013-10-23 2015-04-29 格罗方德半导体公司 用于后段制程金属化的混合型锰和氮化锰阻障物及其制法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6022808A (en) 1998-03-16 2000-02-08 Advanced Micro Devices, Inc. Copper interconnect methodology for enhanced electromigration resistance
US6515368B1 (en) 2001-12-07 2003-02-04 Advanced Micro Devices, Inc. Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper
JP4106048B2 (ja) * 2004-10-25 2008-06-25 松下電器産業株式会社 半導体装置の製造方法及び半導体装置
US7351656B2 (en) * 2005-01-21 2008-04-01 Kabushiki Kaihsa Toshiba Semiconductor device having oxidized metal film and manufacture method of the same
US7402519B2 (en) 2005-06-03 2008-07-22 Intel Corporation Interconnects having sealing structures to enable selective metal capping layers
US7605073B2 (en) * 2006-05-19 2009-10-20 Intel Corporation Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures
US7619310B2 (en) * 2006-11-03 2009-11-17 Infineon Technologies Ag Semiconductor interconnect and method of making same
US7777344B2 (en) * 2007-04-11 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Transitional interface between metal and dielectric in interconnect structures
JP2008294335A (ja) * 2007-05-28 2008-12-04 Panasonic Corp 半導体装置の製造方法
US20090321935A1 (en) 2008-06-30 2009-12-31 O'brien Kevin Methods of forming improved electromigration resistant copper films and structures formed thereby
JP5014356B2 (ja) * 2009-01-15 2012-08-29 パナソニック株式会社 半導体装置の製造方法
JP2012038961A (ja) 2010-08-09 2012-02-23 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US8822342B2 (en) * 2010-12-30 2014-09-02 Globalfoundries Singapore Pte. Ltd. Method to reduce depth delta between dense and wide features in dual damascene structures
JP5734757B2 (ja) * 2011-06-16 2015-06-17 株式会社東芝 半導体装置及びその製造方法
US9224643B2 (en) * 2011-09-19 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for tunable interconnect scheme
US9034756B2 (en) * 2012-07-26 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit interconnects and methods of making same
KR102154112B1 (ko) * 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
US9105697B2 (en) * 2013-12-11 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Trench formation using rounded hard mask
US9219033B2 (en) * 2014-03-21 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Via pre-fill on back-end-of-the-line interconnect layer
US9960052B2 (en) * 2014-04-02 2018-05-01 Applied Materials, Inc. Methods for etching a metal layer to form an interconnection structure for semiconductor applications
US9263389B2 (en) * 2014-05-14 2016-02-16 International Business Machines Corporation Enhancing barrier in air gap technology
CN105140172B (zh) 2014-05-27 2019-01-25 中芯国际集成电路制造(北京)有限公司 互连结构及其形成方法
CN106033741B (zh) * 2015-03-20 2020-09-15 联华电子股份有限公司 金属内连线结构及其制作方法
US9754891B2 (en) 2015-09-23 2017-09-05 International Business Machines Corporation Low-temperature diffusion doping of copper interconnects independent of seed layer composition
US9728447B2 (en) * 2015-11-16 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-barrier deposition for air gap formation

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0506710A1 (en) * 1989-12-22 1992-10-07 Micro Power System, Inc. Process enhancement using molybdenum plugs in fabricating integrated circuits
US6723634B1 (en) * 2002-03-14 2004-04-20 Advanced Micro Devices, Inc. Method of forming interconnects with improved barrier layer adhesion
KR20030083174A (ko) * 2002-04-19 2003-10-30 아남반도체 주식회사 반도체 소자의 에어갭 형성방법
KR20040000704A (ko) * 2002-06-25 2004-01-07 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성 방법
CN101431046A (zh) * 2007-10-09 2009-05-13 应用材料股份有限公司 在用于减少rc延迟的介电层中产生气隙的方法和装置
US20110101529A1 (en) * 2009-10-29 2011-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier layer for copper interconnect
CN104025262A (zh) * 2011-12-29 2014-09-03 英特尔公司 具有罩层的气隙互连以及形成的方法
CN104364903A (zh) * 2012-06-01 2015-02-18 高通股份有限公司 具有单向金属层的堆叠内有混合的金属叉指取向的金属叉指电容器
US20140264908A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene gap filling process
CN104576518A (zh) * 2013-10-23 2015-04-29 格罗方德半导体公司 用于后段制程金属化的混合型锰和氮化锰阻障物及其制法

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