CN107452713A - 形成具有改进黏附性的低电阻率贵金属互连的装置及方法 - Google Patents

形成具有改进黏附性的低电阻率贵金属互连的装置及方法 Download PDF

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CN107452713A
CN107452713A CN201710398579.5A CN201710398579A CN107452713A CN 107452713 A CN107452713 A CN 107452713A CN 201710398579 A CN201710398579 A CN 201710398579A CN 107452713 A CN107452713 A CN 107452713A
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interconnection
barrier layer
groove
materials
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张洵渊
法兰克·W·蒙特
埃罗尔·特德·莱恩
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GlobalFoundries Inc
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Abstract

本发明涉及形成具有改进黏附性的低电阻率贵金属互连的装置及方法，其提供制造集成电路装置以形成具有改进黏附性的低电阻率互连的装置及方法。一种方法包括例如：获得中间半导体互连装置，该中间半导体互连装置具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；将金属互连材料直接沉积在该介电矩阵的顶部表面上方并与其接触，其中，该金属互连材料填充该组沟槽及该组过孔；在该装置的顶部表面上方沉积阻挡层；退火该阻挡层，以使该阻挡层扩散至该金属互连材料的底部表面；平坦化该中间半导体互连装置的顶部表面；以及在该中间半导体互连装置上方沉积介电覆盖层。

Description

形成具有改进黏附性的低电阻率贵金属互连的装置及方法
技术领域
本发明涉及半导体装置以及制造半导体装置的方法，尤其涉及形成具有改进黏附性的贵金属的低电阻率金属互连的装置及方法。
背景技术
对于5纳米及以下节点，随着对更小电路结构及更快装置性能的需求不断增加，铜线电阻率开始攀升，从而降低该些节点的性能。5纳米节点及更小节点的开发将可能需要降低该些节点中的线的电阻率。不过，在这些尺寸，先前的沟槽及过孔加衬方法可引起阻挡层及互连材料自装置脱层。
因此，可能希望开发在此类小尺寸下与铜相比具有较低电阻率并具有改进黏附性的线的节点制造方法。
发明内容
为克服现有技术的缺点并提供额外的优点，在一个态样中提供一种方法，该方法包括例如：获得中间半导体互连装置，该中间半导体互连装置具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；将金属互连材料直接沉积在该介电矩阵的顶部表面上方并与其接触，其中，该金属互连材料填充该组沟槽及该组过孔；在该半导体互连装置的顶部表面上方沉积阻挡层；退火该阻挡层，以使该阻挡层扩散至该金属互连材料的底部表面；平坦化该中间半导体互连装置的顶部表面，移除该组沟槽及该组过孔上方的该金属互连材料；以及在该中间半导体互连装置上方沉积介电覆盖层。
在另一个态样中，提供一种中间装置，其包括例如：中间半导体互连装置，具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；阻挡层，位于该介电矩阵材料的顶部表面上方，加衬该组沟槽及该组过孔；金属互连材料，直接位于该阻挡层上方并与其接触，其中，该金属互连材料填充该组沟槽及该组过孔，以及其中，该阻挡层被退火；以及介电覆盖层，位于该中间半导体互连装置上方。
在另一个态样中，提供一种装置，其包括例如：中间半导体互连装置，具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；阻挡层，位于该介电矩阵材料的顶部表面上方，加衬该组沟槽及该组过孔；金属互连材料，直接位于该阻挡层上方并与其接触，其中，该金属互连材料填充该组沟槽及该组过孔，以及其中，该阻挡层被退火；以及介电覆盖层，位于该中间半导体互连装置上方。
附图说明
本发明的一个或多个态样被特别指出并在说明书的结束处的声明中被明确称为示例。从下面结合附图所作的详细说明可清楚本发明的上述及其它目的、特征以及优点，该些附图中：
图1显示依据本发明的一个或多个态样用以形成中间半导体互连结构的方法的一个实施例；
图2显示依据本发明的一个或多个态样具有衬底、覆盖层以及包括一组沟槽及一组过孔的介电矩阵的中间半导体互连结构的一个实施例的剖切立视图；
图3显示依据本发明的一个或多个态样在沉积金属互连材料以后的图2的结构；
图4显示依据本发明的一个或多个态样在沉积阻挡层以后的图3的结构；
图5显示依据本发明的一个或多个态样在退火该阻挡层以后的图4的结构；
图6显示依据本发明的一个或多个态样在平坦化该中间半导体互连结构的顶部表面以后的图5的结构；
图7显示依据本发明的一个或多个态样在沉积牺牲介电覆盖层以后的图6的结构；
图8显示依据本发明的一个或多个态样在沉积阻挡掩膜并形成开口以后的图7的结构；
图9显示依据本发明的一个或多个态样在形成一组气隙并移除该牺牲介电覆盖层以后的图8的结构；以及
图10显示依据本发明的一个或多个态样在沉积介电覆盖层以后的图9的结构；
图11显示依据本发明的一个或多个态样具有衬底、覆盖层、介电矩阵、一组沟槽、一组过孔、加衬该组沟槽及该组过孔的阻挡层，以及介电覆盖层的中间装置的一个实施例的剖切立视图。
主要组件符号说明
100至140 步骤
200 装置或中间半导体装置
210 衬底
220 覆盖层
230 介电矩阵
242 过孔
244 沟槽
250 阻挡层
260 金属互连材料
270 牺牲介电覆盖层
272 阻挡掩膜
280 气隙
290 介电覆盖层。
具体实施方式
下面通过参照附图中所示的非限制性实施例来更加充分地解释本发明的态样及其特定的特征、优点以及细节。省略对已知材料、制造工具、制程技术等的说明，以免在细节上不必要地模糊本发明。不过，应当理解，当说明本发明的实施例时，详细说明及具体例子仅作为示例，而非限制。本领域的技术人员将会从本揭露中了解在基础的发明概念的精神和/或范围内的各种替代、修改、添加和/或布局。还要注意，下面参照附图，为方便理解，该些附图并非按比例绘制，其中，不同附图中所使用的相同附图标记表示相同或类似的组件。
一般来说，本文揭露特定的集成电路，其提供相对上述的现有半导体装置及制程的优点。有利地，本文中所揭露的集成电路装置制程提供与先前可能使用传统铜线相比具有较低线电阻率的半导体装置。
在一个态样中，在一个实施例中，如图1中所示，依据本发明的一个或多个态样的集成电路装置形成制程可包括例如：获得具有衬底、覆盖层以及包括一组沟槽及一组过孔的介电矩阵的中间半导体互连装置100；在该组沟槽及该组过孔中及上方沉积金属互连材料110；在该金属互连材料的顶部表面上方沉积阻挡层120；在有H2的情况下退火该阻挡层130；以及平坦化该中间半导体互连装置的顶部表面140。
图2至10显示(仅示例)依据本发明的一个或多个态样的半导体装置形成制程的部分及中间半导体互连结构的部分的一个详细实施例。要注意的是，这些附图并非按比例绘制，以促进理解本发明，且不同附图中所使用的相同附图标记表示相同或类似的组件。
图2显示处于中间半导体制造阶段的中间半导体装置200的一部分。已依据所制造的装置200的设计通过初始装置制程步骤对装置200进行了处理。例如，装置200可包括例如衬底210，在衬底210上设有覆盖层220，该覆盖层可包括介电材料。衬底210可为任意合适的材料，例如硅。另外，在衬底210或覆盖层220上可沉积介电矩阵230。介电矩阵可包括一种或多种介电材料，且可包括材料混合矩阵或多个材料层(未显示)。介电矩阵230可包括一组过孔242及一组沟槽244。如图2中所示，该组过孔242可延伸穿过覆盖层220至下方特征，而该组沟槽244可仅延伸进入介电矩阵230中。
在另一个实施例中(未显示)，装置200的该衬底可为例如绝缘体上覆硅(siliconon insulator；SOI)衬底(未显示)。例如，该SOI衬底可包括隔离层(未显示)，该隔离层可为局部埋置氧化物区(burideoxide；BOX)或任意合适的材料以电性隔离晶体管，与栅极结构对齐。在一些实施例中，该装置为集成电路(integrated circuit；IC)的后端工艺(backend of line；BEOL)部分的部分。
如图2中所示，通过使用光刻及蚀刻制程，可已于介电矩阵230中蚀刻介电矩阵230和/或覆盖层220，以定义该组过孔242及该组沟槽244。该蚀刻可通过任意合适的蚀刻制程执行，例如定向反应离子蚀刻(reactive ion etching；RIE)。
如图3中所示，在一些实施例中，通过原子层沉积(atomic layerdeposition；ALD)或化学气相沉积(chemical vapor deposition；CVD)在介电矩阵230上方直接沉积金属互连材料260。在一些实施例中，该金属互连材料沉积约10纳米与约20纳米之间的厚度，以使其填充该组过孔242(图2)及该组沟槽244(图2)。金属互连材料260可包括任意的贵金属，包括但不限于：钌(Ru)、铌(Nb)、铑(Rh)、铱(Ir)、以及铂(PT)。尽管传统上铜(Cu)为该互连材料的选择，但随着装置的线宽不断变小，铜的电阻率开始增加。相比之下，贵金属在较小尺寸可具有更理想的电阻率。
例如，与在20纳米与6纳米之间不断爬升的铜不同，Ru薄膜从20纳米至6纳米具有几乎恒定的电阻率。在约5纳米，Ru可具有与Cu几乎相同的电阻率，且在5纳米以下可具有较低的电阻率。另外，不像许多其它互连材料，Ru不会出现因电迁移(electromigration；EM)而导致的失效。贵金属薄膜的时间相关介电击穿(time dependentdielectric breakdown；TDDB)可比铜好至少10倍。不过，如下面进一步说明，通过增加与金属互连材料260相邻的层(例如阻挡层250)的电阻，可更进一步降低金属互连材料260的电阻率。因此，就组成改变阻挡层250来增加电阻可降低金属互连材料260的电阻。
如图4中所示，通过ALD、CVD、物理气相沉积(physical vapordeposition；PVD)或当前已知或以后开发的任意其它合适的沉积技术可沿金属互连材料260的顶部表面沉积阻挡层250。例如，阻挡层250可具有锰(Mn)组分并可为约1纳米(nm)厚至约3纳米(nm)厚。如图4中所示，可使用能够形成小于约3纳米的一致薄膜或薄层的任意沉积来沉积阻挡层250。
如图5中所示，可在有H2的情况下退火阻挡层250，其可处于周围空气中。在该空气中的氧的驱动下，该退火制程可使该含Mn阻挡层扩散穿过金属互连材料260，形成阻挡层于金属互连材料260与介电矩阵230之间。施加阻挡层250的此方法可增加阻挡层260及金属互连材料260与介电矩阵230的黏附性。例如，首先通过CVD、PVD或AVD沉积该阻挡层可导致该些层脱层，可能导致早期装置失效。在金属互连材料260上方沉积阻挡层250并使其扩散穿过该金属互连材料增加所有层的黏附性，并因此导致更稳定的装置。
如图6中所示，通过使用例如化学机械抛光，可平坦化并抛光装置200的顶部表面，移除多余金属互连材料260并提供光滑表面，以在该光滑表面上继续装置制造。在该低电阻率贵金属互连材料的外表面上具有较高电阻率的含Mn阻挡层降低该金属互连的有效电阻率。在此实施例中，金属互连材料260的电阻可被显着降低，同时很好地黏附于该组沟槽244及该组过孔242中。
图7至10显示通过移除该组沟槽244与该组过孔242的至少其中一些之间的介电矩阵230的部分在装置200中纳入一组气隙280的另一个实施例。在一些实施例中，气隙280可更进一步降低金属互连材料260的电导率。
如图7中所示，在另一个实施例中，例如通过在装置200上方沉积牺牲介电覆盖层270，可在装置200中进一步纳入该组气隙280(图9)。由于此覆盖层用于遮蔽下方结构且不用于最终装置的运行，因此将其视为牺牲。
如图8中所示，通过标准光刻及蚀刻技术在牺牲介电覆盖层270的顶部表面上可形成阻挡掩膜272，且例如通过蚀刻可移除牺牲介电覆盖层270，以通过使用任意光刻技术在该组沟槽244及该组过孔242上方暴露并形成一个或多个开口。在使用以后，可通过蚀刻移除阻挡掩膜272。
如图9中所示，例如通过在介电矩阵230内形成一组气隙280可暴露该组过孔242与该组沟槽244的至少其中一些之间的阻挡层250的一部分。在一些实施例中，例如，可破坏介电矩阵230的区域(例如该组沟槽244与该组过孔242的其中一些或全部之间的区域)，以形成该组气隙280。在一些实施例中，使用H2N2等离子体来破坏介电矩阵230。例如，通过使用稀释氢氟酸(hydrofluoric acid；HF)可移除被破坏的材料，保留该组过孔242与该组沟槽244的至少其中一些之间的气隙280。同时，通过使用同一材料可移除牺牲介电覆盖层270。
如图10中所示，介电覆盖层290可涂布装置200的顶部表面并涂布气隙280(图7)的内部表面。在金属互连材料260的表面具有含Mn阻挡层250将降低最终IC中的金属互连材料260的有效电阻。
如图4中所示，所声明的中间装置200可包括例如衬底210、覆盖层220、介电矩阵230、延伸穿过覆盖层220的一组过孔242、延伸进入介电矩阵230中的一组沟槽244，直接沉积于沟槽244及过孔242上方并与其接触的金属互连材料260，以及沉积于中间装置200上方的阻挡层250。在这些实施例中，该金属互连材料可包括贵金属。其它材料如上所述。
图11显示装置900，依据一些实施例，该装置包括衬底210、覆盖层220、介电矩阵230、延伸穿过覆盖层220的一组过孔242、延伸进入介电矩阵230中的一组沟槽244、加衬沟槽244及过孔242的外部的阻挡层250、填充沟槽244及过孔242的金属互连材料260，以及介电覆盖层290。在这些实施例中，金属互连材料260可包括贵金属。其它材料如上所述。
应当了解，上面所揭露的新颖的中间半导体互连装置及其形成方法降低后端工艺(BEOL)互连形成及线的电阻，同时改进该些层的黏附性。依据实施例，通过改变该互连本身的材料来降低该装置的表面散射，且增加阻挡层的电阻及黏附性降低该互连材料的最终电阻。由于电迁移现象减少，贵金属作为互连材料是有利的，部分因为该金属的较高熔点。另外，贵金属更加抗氧化，从而使阻挡层更容易氧化。
本文中所使用的术语仅是出于说明特定实施例的目的，并非意图限制本发明。除非上下文中明确指出，否则本文中所使用的单数形式“一个”以及“该”也意图包括复数形式。还应当理解，术语“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(以及任意形式的包含)都是开放式连接动词。因此，“包括”、“具有”或“包含”一个或多个步骤或组件的方法或装置具有那些一个或多个步骤或组件，但并不限于仅仅具有那些一个或多个步骤或组件。类似地，“包括”、“具有”或“包含”一个或多个特征的一种方法的步骤或一种装置的组件具有那些一个或多个特征，但并不限于仅仅具有那些一个或多个特征。而且，以特定方式配置的装置或结构至少以那种方式配置，但也可以未列出的方式配置。
所附的权利要求书中的所有方式或步骤加功能元素的相应结构、材料、动作及等同(如果有的话)意图包括结合具体请求保护的其它请求保护的元素执行该功能的任意结构、材料或动作。本发明的说明用于示例及说明目的，而非意图详尽无遗或限于所揭露形式的发明。许多修改及变更将对于本领域的普通技术人员显而易见，而不背离本发明的范围及精神。该些实施例经选择及说明以最佳解释本发明的一个或多个态样的原理以及实际应用，并使本领域的普通技术人员能够理解针对各种实施例具有适合所考虑的特定应用的各种变更的本发明的一个或多个态样。

Claims (20)

1.一种方法，包括：
获得中间半导体互连装置，该中间半导体互连装置具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；
将金属互连材料直接沉积在该介电矩阵的顶部表面上方并与其接触，其中，该金属互连材料填充该组沟槽及该组过孔；
在该半导体互连装置的顶部表面上方沉积阻挡层；
退火该阻挡层，以使该阻挡层扩散至该金属互连材料的底部表面；
平坦化该中间半导体互连装置的顶部表面，移除该组沟槽及该组过孔上方的该金属互连材料；以及
在该中间半导体互连装置上方沉积介电覆盖层。
2.如权利要求1所述的方法，其中，该阻挡层包括含锰材料。
3.如权利要求1所述的方法，其中，该金属互连材料包括贵金属。
4.如权利要求3所述的方法，其中，该贵金属包括：包括钌(Ru)、铌(Nb)、铑(Rh)、铱(Ir)及铂(PT)的群组的其中之一。
5.如权利要求1所述的方法，其中，该退火在有H2的情况下执行，且氧驱动该扩散。
6.如权利要求1所述的方法，还包括：
在所述沉积该介电覆盖层之前，在该中间半导体互连装置上方沉积牺牲介电覆盖层及阻挡掩膜；以及
在该组沟槽与该组过孔的至少其中一部分之间形成一组气隙，用湿化学移除该牺牲介电覆盖层。
7.如权利要求6所述的方法，其中，该湿化学包括稀释氢氟酸(HF)。
8.如权利要求6所述的方法，其中，所述沉积该介电覆盖层在该组过孔与该组沟槽之间的区域中形成一组气隙。
9.如权利要求1所述的方法，其中，该阻挡层包括约1纳米至约3纳米的厚度，以及其中，该金属互连材料沉积约10纳米与约20纳米之间的厚度。
10.如权利要求9所述的方法，其中，该阻挡层通过包括原子层沉积(ALD)、化学气相沉积(CVD)及物理气相沉积(PVD)的群组的其中之一来沉积，以及其中，该金属互连材料通过包括化学气相沉积及原子层沉积的群组的其中之一来沉积。
11.一种中间装置，包括：
中间半导体互连装置，具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；
金属互连材料，直接位于该介电矩阵的顶部表面上方并与其接触，其中，该金属互连材料填充该组沟槽及该组过孔；以及
阻挡层，位于该半导体互连装置的顶部表面上方。
12.如权利要求11所述的装置，还包括：
一组气隙，位于该组过孔与该组沟槽的至少其中一些之间。
13.如权利要求11所述的装置，其中，该阻挡层包括含锰材料。
14.如权利要求11所述的装置，其中，该金属互连材料包括贵金属。
15.如权利要求14所述的装置，其中，该贵金属包括：包括钌(Ru)、铌(Nb)、铑(Rh)、铱(Ir)及铂(PT)的群组的其中之一。
16.一种装置，包括：
中间半导体互连装置，具有衬底、覆盖层，以及包括一组沟槽及一组过孔的介电矩阵；
阻挡层，位于该介电矩阵材料的顶部表面上方，加衬该组沟槽及该组过孔；
金属互连材料，直接位于该阻挡层上方并与其接触，其中，该金属互连材料填充该组沟槽及该组过孔，以及其中，该阻挡层被退火；以及
介电覆盖层，位于该中间半导体互连装置上方。
17.如权利要求16所述的装置，还包括：
一组气隙，位于该组过孔与该组沟槽的至少其中一些之间。
18.如权利要求16所述的装置，其中，该阻挡层包括含锰材料。
19.如权利要求16所述的装置，其中，该金属互连材料包括贵金属。
20.如权利要求19所述的装置，其中，该贵金属包括：包括钌(Ru)、铌(Nb)、铑(Rh)、铱(Ir)及铂(PT)的群组的其中之一。
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