TW201812995A - 形成具有改進黏附性的低電阻率貴金屬互連的裝置及方法 - Google Patents

形成具有改進黏附性的低電阻率貴金屬互連的裝置及方法 Download PDF

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TW201812995A
TW201812995A TW106106411A TW106106411A TW201812995A TW 201812995 A TW201812995 A TW 201812995A TW 106106411 A TW106106411 A TW 106106411A TW 106106411 A TW106106411 A TW 106106411A TW 201812995 A TW201812995 A TW 201812995A
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barrier layer
vias
metal interconnect
trenches
interconnect material
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張洵淵
法蘭克Ｗ 蒙特
埃羅爾 特德 萊恩
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格羅方德半導體公司
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Abstract

本發明提供製造積體電路裝置以形成具有改進黏附性的低電阻率互連的裝置及方法。一種方法包括例如：獲得中間半導體互連裝置，該中間半導體互連裝置具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；將金屬互連材料直接沉積在該介電矩陣的頂部表面上方並與其接觸，其中，該金屬互連材料填充該組溝槽及該組通孔；在該裝置的頂部表面上方沉積阻擋層；退火該阻擋層，以使該阻擋層擴散至該金屬互連材料的底部表面；平坦化該中間半導體互連裝置的頂部表面；以及在該中間半導體互連裝置上方沉積介電覆蓋層。

Description

形成具有改進黏附性的低電阻率貴金屬互連的裝置及方法
本發明關於半導體裝置以及製造半導體裝置的方法，尤其關於形成具有改進黏附性的貴金屬的低電阻率金屬互連的裝置及方法。
對於5奈米及以下節點，隨著對更小電路結構及更快裝置性能的需求不斷增加，銅線電阻率開始攀升，從而降低該些節點的性能。5奈米節點及更小節點的開發將可能需要降低該些節點中的線的電阻率。不過，在這些尺寸，先前的溝槽及通孔加襯方法可引起阻擋層及互連材料自裝置脫層。
因此，可能希望開發在此類小尺寸下與銅相比具有較低電阻率並具有改進黏附性的線的節點製造方法。
為克服現有技術的缺點並提供額外的優 點，在一個態樣中提供一種方法，該方法包括例如：獲得中間半導體互連裝置，該中間半導體互連裝置具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；將金屬互連材料直接沉積在該介電矩陣的頂部表面上方並與其接觸，其中，該金屬互連材料填充該組溝槽及該組通孔；在該半導體互連裝置的頂部表面上方沉積阻擋層；退火該阻擋層，以使該阻擋層擴散至該金屬互連材料的底部表面；平坦化該中間半導體互連裝置的頂部表面，移除該組溝槽及該組通孔上方的該金屬互連材料；以及在該中間半導體互連裝置上方沉積介電覆蓋層。
在另一個態樣中，提供一種中間裝置，其包括例如：中間半導體互連裝置，具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；阻擋層，位於該介電矩陣材料的頂部表面上方，加襯該組溝槽及該組通孔；金屬互連材料，直接位於該阻擋層上方並與其接觸，其中，該金屬互連材料填充該組溝槽及該組通孔，以及其中，該阻擋層被退火；以及介電覆蓋層，位於該中間半導體互連裝置上方。
在另一個態樣中，提供一種裝置，其包括例如：中間半導體互連裝置，具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；阻擋層，位於該介電矩陣材料的頂部表面上方，加襯該組溝槽及該組通孔；金屬互連材料，直接位於該阻擋層上方並與其接觸，其中，該金屬互連材料填充該組溝槽及該組通孔，以及其中，該 阻擋層被退火；以及介電覆蓋層，位於該中間半導體互連裝置上方。
100至140‧‧‧步驟
200‧‧‧裝置或中間半導體裝置
210‧‧‧基板
220‧‧‧覆蓋層
230‧‧‧介電矩陣
242‧‧‧通孔
244‧‧‧溝槽
250‧‧‧阻擋層
260‧‧‧金屬互連材料
270‧‧‧犧牲介電覆蓋層
272‧‧‧阻擋遮罩
280‧‧‧氣隙
290‧‧‧介電覆蓋層
本發明的一個或多個態樣被特別指出並在說明書的結束處的聲明中被明確稱為示例。從下面結合附圖所作的詳細說明可清楚本發明的上述及其它目的、特徵以及優點，該些附圖中：第1圖顯示依據本發明的一個或多個態樣用以形成中間半導體互連結構的方法的一個實施例；第2圖顯示依據本發明的一個或多個態樣具有基板、覆蓋層以及包括一組溝槽及一組通孔的介電矩陣的中間半導體互連結構的一個實施例的剖切立視圖；第3圖顯示依據本發明的一個或多個態樣在沉積金屬互連材料以後的第2圖的結構；第4圖顯示依據本發明的一個或多個態樣在沉積阻擋層以後的第3圖的結構；第5圖顯示依據本發明的一個或多個態樣在退火該阻擋層以後的第4圖的結構；第6圖顯示依據本發明的一個或多個態樣在平坦化該中間半導體互連結構的頂部表面以後的第5圖的結構；第7圖顯示依據本發明的一個或多個態樣在沉積犧牲介電覆蓋層以後的第6圖的結構；第8圖顯示依據本發明的一個或多個態樣 在沉積阻擋遮罩並形成開口以後的第7圖的結構；第9圖顯示依據本發明的一個或多個態樣在形成一組氣隙並移除該犧牲介電覆蓋層以後的第8圖的結構；以及第10圖顯示依據本發明的一個或多個態樣在沉積介電覆蓋層以後的第9圖的結構；第11圖顯示依據本發明的一個或多個態樣具有基板、覆蓋層、介電矩陣、一組溝槽、一組通孔、加襯該組溝槽及該組通孔的阻擋層，以及介電覆蓋層的中間裝置的一個實施例的剖切立視圖。
下面通過參照附圖中所示的非限制性實施例來更加充分地解釋本發明的態樣及其特定的特徵、優點以及細節。省略對已知材料、製造工具、製程技術等的說明，以免在細節上不必要地模糊本發明。不過，應當理解，當說明本發明的實施例時，詳細說明及具體例子僅作為示例，而非限制。本領域的技術人員將會從本揭露中瞭解在基礎的發明概念的精神和/或範圍內的各種替代、修改、添加和/或佈局。還要注意，下面參照附圖，為方便理解，該些附圖並非按比例繪製，其中，不同附圖中所使用的相同附圖標記表示相同或類似的元件。
一般來說，本文揭露特定的積體電路，其提供相對上述的現有半導體裝置及製程的優點。有利地，本文中所揭露的積體電路裝置製程提供與先前可能使用傳 統銅線相比具有較低線電阻率的半導體裝置。
在一個態樣中，在一個實施例中，如第1圖中所示，依據本發明的一個或多個態樣的積體電路裝置形成製程可包括例如：獲得具有基板、覆蓋層以及包括一組溝槽及一組通孔的介電矩陣的中間半導體互連裝置100；在該組溝槽及該組通孔中及上方沉積金屬互連材料110；在該金屬互連材料的頂部表面上方沉積阻擋層120；在有H2的情況下退火該阻擋層130；以及平坦化該中間半導體互連裝置的頂部表面140。
第2至10圖顯示(僅示例)依據本發明的一個或多個態樣的半導體裝置形成製程的部分及中間半導體互連結構的部分的一個詳細實施例。要注意的是，這些附圖並非按比例繪製，以促進理解本發明，且不同附圖中所使用的相同附圖標記表示相同或類似的元件。
第2圖顯示處於中間半導體製造階段的中間半導體裝置200的一部分。已依據所製造的裝置200的設計通過初始裝置製程步驟對裝置200進行了處理。例如，裝置200可包括例如基板210，在基板210上設有覆蓋層220，該覆蓋層可包括介電材料。基板210可為任意合適的材料，例如矽。另外，在基板210或覆蓋層220上可沉積介電矩陣230。介電矩陣可包括一種或多種介電材料，且可包括材料混合矩陣或多個材料層(未顯示)。介電矩陣230可包括一組通孔242及一組溝槽244。如第2圖中所示，該組通孔242可延伸穿過覆蓋層220至下方特徵， 而該組溝槽244可僅延伸進入介電矩陣230中。
在另一個實施例中(未顯示)，裝置200的該基板可為例如絕緣體上覆矽(silicon on insulator；SOI)基板(未顯示)。例如，該SOI基板可包括隔離層(未顯示)，該隔離層可為局部埋置氧化物區(buride oxide；BOX)或任意合適的材料以電性隔離電晶體，與閘極結構對齊。在一些實施例中，該裝置為積體電路(integrated circuit；IC)的後端工藝(back end of line；BEOL)部分的部分。
如第2圖中所示，通過使用光刻及蝕刻製程，可已於介電矩陣230中蝕刻介電矩陣230和/或覆蓋層220，以定義該組通孔242及該組溝槽244。該蝕刻可通過任意合適的蝕刻製程執行，例如定向反應離子蝕刻(reactive ion etching；RIE)。
如第3圖中所示，在一些實施例中，通過原子層沉積(atomic layer deposition；ALD)或化學氣相沉積(chemical vapor deposition；CVD)在介電矩陣230上方直接沉積金屬互連材料260。在一些實施例中，該金屬互連材料沉積約10奈米與約20奈米之間的厚度，以使其填充該組通孔242(第2圖)及該組溝槽244(第2圖)。金屬互連材料260可包括任意的貴金屬，包括但不限於：釕(Ru)、鈮(Nb)、銠(Rh)、銥(Ir)、以及鉑(PT)。儘管傳統上銅(Cu)為該互連材料的選擇，但隨著裝置的線寬不斷變小，銅的電阻率開始增加。相比之下，貴金屬在較小尺寸可具有更理想的電阻率。
例如，與在20奈米與6奈米之間不斷爬升的銅不同，Ru薄膜從20奈米至6奈米具有幾乎恒定的電阻率。在約5奈米，Ru可具有與Cu幾乎相同的電阻率，且在5奈米以下可具有較低的電阻率。另外，不像許多其它互連材料，Ru不會出現因電遷移(electromigration；EM)而導致的失效。貴金屬薄膜的時間相關介電擊穿(time dependent dielectric breakdown；TDDB)可比銅好至少10倍。不過，如下面進一步說明，通過增加與金屬互連材料260相鄰的層(例如阻擋層250)的電阻，可更進一步降低金屬互連材料260的電阻率。因此，就組成改變阻擋層250來增加電阻可降低金屬互連材料260的電阻。
如第4圖中所示，通過ALD、CVD、物理氣相沉積(physical vapor deposition；PVD)或當前已知或以後開發的任意其它合適的沉積技術可沿金屬互連材料260的頂部表面沉積阻擋層250。例如，阻擋層250可具有錳(Mn)組分並可為約1奈米(nm)厚至約3奈米(nm)厚。如第4圖中所示，可使用能夠形成小於約3奈米的一致薄膜或薄層的任意沉積來沉積阻擋層250。
如第5圖中所示，可在有H2的情況下退火阻擋層250，其可處於周圍空氣中。在該空氣中的氧的驅動下，該退火製程可使該含Mn阻擋層擴散穿過金屬互連材料260，形成阻擋層于金屬互連材料260與介電矩陣230之間。施加阻擋層250的此方法可增加阻擋層260及金屬互連材料260與介電矩陣230的黏附性。例如，首先通過 CVD、PVD或AVD沉積該阻擋層可導致該些層脫層，可能導致早期裝置失效。在金屬互連材料260上方沉積阻擋層250並使其擴散穿過該金屬互連材料增加所有層的黏附性，並因此導致更穩定的裝置。
如第6圖中所示，通過使用例如化學機械拋光，可平坦化並拋光裝置200的頂部表面，移除多餘金屬互連材料260並提供光滑表面，以在該光滑表面上繼續裝置製造。在該低電阻率貴金屬互連材料的外表面上具有較高電阻率的含Mn阻擋層降低該金屬互連的有效電阻率。在此實施例中，金屬互連材料260的電阻可被顯著降低，同時很好地黏附於該組溝槽244及該組通孔242中。
第7至10圖顯示通過移除該組溝槽244與該組通孔242的至少其中一些之間的介電矩陣230的部分在裝置200中納入一組氣隙280的另一個實施例。在一些實施例中，氣隙280可更進一步降低金屬互連材料260的電導率。
如第7圖中所示，在另一個實施例中，例如通過在裝置200上方沉積犧牲介電覆蓋層270，可在裝置200中進一步納入該組氣隙280(第9圖)。由於此覆蓋層用於遮蔽下方結構且不用於最終裝置的運行，因此將其視為犧牲。
如第8圖中所示，通過標準光刻及蝕刻技術在犧牲介電覆蓋層270的頂部表面上可形成阻擋遮罩272，且例如通過蝕刻可移除犧牲介電覆蓋層270，以通過 使用任意光刻技術在該組溝槽244及該組通孔242上方暴露並形成一個或多個開口。在使用以後，可通過蝕刻移除阻擋遮罩272。
如第9圖中所示，例如通過在介電矩陣230內形成一組氣隙280可暴露該組通孔242與該組溝槽244的至少其中一些之間的阻擋層250的一部分。在一些實施例中，例如，可破壞介電矩陣230的區域(例如該組溝槽244與該組通孔242的其中一些或全部之間的區域)，以形成該組氣隙280。在一些實施例中，使用H2N2電漿來破壞介電矩陣230。例如，通過使用稀釋氫氟酸(hydrofluoric acid；HF)可移除被破壞的材料，保留該組通孔242與該組溝槽244的至少其中一些之間的氣隙280。同時，通過使用同一材料可移除犧牲介電覆蓋層270。
如第10圖中所示，介電覆蓋層290可塗布裝置200的頂部表面並塗布氣隙280(第7圖)的內部表面。在金屬互連材料260的表面具有含Mn阻擋層250將降低最終IC中的金屬互連材料260的有效電阻。
如第4圖中所示，所聲明的中間裝置200可包括例如基板210、覆蓋層220、介電矩陣230、延伸穿過覆蓋層220的一組通孔242、延伸進入介電矩陣230中的一組溝槽244，直接沉積於溝槽244及通孔242上方並與其接觸的金屬互連材料260，以及沉積於中間裝置200上方的阻擋層250。在這些實施例中，該金屬互連材料可包括貴金屬。其它材料如上所述。
第11圖顯示裝置900，依據一些實施例，該裝置包括基板210、覆蓋層220、介電矩陣230、延伸穿過覆蓋層220的一組通孔242、延伸進入介電矩陣230中的一組溝槽244、加襯溝槽244及通孔242的外部的阻擋層250、填充溝槽244及通孔242的金屬互連材料260，以及介電覆蓋層290。在這些實施例中，金屬互連材料260可包括貴金屬。其它材料如上所述。
應當瞭解，上面所揭露的新穎的中間半導體互連裝置及其形成方法降低後端工藝(BEOL)互連形成及線的電阻，同時改進該些層的黏附性。依據實施例，通過改變該互連本身的材料來降低該裝置的表面散射，且增加阻擋層的電阻及黏附性降低該互連材料的最終電阻。由於電遷移現象減少，貴金屬作為互連材料是有利的，部分因為該金屬的較高熔點。另外，貴金屬更加抗氧化，從而使阻擋層更容易氧化。
本文中所使用的術語僅是出於說明特定實施例的目的，並非意圖限制本發明。除非上下文中明確指出，否則本文中所使用的單數形式“一個”以及“該”也意圖包括複數形式。還應當理解，術語“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(以及任意形式的包含)都是開放式連接動詞。因此，“包括”、“具有”或“包含”一個或多個步驟或元件的方法或裝置具有那些一個或多個步驟或元件，但並不限於僅僅具有那些一個或多個步驟或元件。類似地，“包括”、 “具有”或“包含”一個或多個特徵的一種方法的步驟或一種裝置的元件具有那些一個或多個特徵，但並不限於僅僅具有那些一個或多個特徵。而且，以特定方式配置的裝置或結構至少以那種方式配置，但也可以未列出的方式配置。
所附的申請專利範圍中的所有方式或步驟加功能元素的相應結構、材料、動作及等同(如果有的話)意圖包括結合具體請求保護的其它請求保護的元素執行該功能的任意結構、材料或動作。本發明的說明用於示例及說明目的，而非意圖詳盡無遺或限於所揭露形式的發明。許多修改及變更將對於本領域的普通技術人員顯而易見，而不背離本發明的範圍及精神。該些實施例經選擇及說明以最佳解釋本發明的一個或多個態樣的原理以及實際應用，並使本領域的普通技術人員能夠理解針對各種實施例具有適合所考慮的特定應用的各種變更的本發明的一個或多個態樣。

Claims (20)

  1. 一種方法，包括：獲得中間半導體互連裝置，該中間半導體互連裝置具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；將金屬互連材料直接沉積在該介電矩陣的頂部表面上方並與其接觸，其中，該金屬互連材料填充該組溝槽及該組通孔；在該半導體互連裝置的頂部表面上方沉積阻擋層；退火該阻擋層，以使該阻擋層擴散至該金屬互連材料的底部表面；平坦化該中間半導體互連裝置的頂部表面，移除該組溝槽及該組通孔上方的該金屬互連材料；以及在該中間半導體互連裝置上方沉積介電覆蓋層。
  2. 如申請專利範圍第1項所述的方法，其中，該阻擋層包括含錳材料。
  3. 如申請專利範圍第1項所述的方法，其中，該金屬互連材料包括貴金屬。
  4. 如申請專利範圍第3項所述的方法，其中，該貴金屬包括：包括釕(Ru)、鈮(Nb)、銠(Rh)、銥(Ir)及鉑(PT)的群組的其中之一。
  5. 如申請專利範圍第1項所述的方法，其中，該退火在有H 2的情況下執行，且氧驅動該擴散。
  6. 如申請專利範圍第1項所述的方法，還包括：在所述沉積該介電覆蓋層之前，在該中間半導體互連裝置上方沉積犧牲介電覆蓋層及阻擋遮罩；以及在該組溝槽與該組通孔的至少其中一部分之間形成一組氣隙，用濕化學移除該犧牲介電覆蓋層。
  7. 如申請專利範圍第6項所述的方法，其中，該濕化學包括稀釋氫氟酸(HF)。
  8. 如申請專利範圍第6項所述的方法，其中，所述沉積該介電覆蓋層在該組通孔與該組溝槽之間的區域中形成一組氣隙。
  9. 如申請專利範圍第1項所述的方法，其中，該阻擋層包括約1奈米至約3奈米的厚度，以及其中，該金屬互連材料沉積約10奈米與約20奈米之間的厚度。
  10. 如申請專利範圍第9項所述的方法，其中，該阻擋層通過包括原子層沉積(ALD)、化學氣相沉積(CVD)及物理氣相沉積(PVD)的群組的其中之一來沉積，以及其中，該金屬互連材料通過包括化學氣相沉積及原子層沉積的群組的其中之一來沉積。
  11. 一種中間裝置，包括：中間半導體互連裝置，具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；金屬互連材料，直接位於該介電矩陣的頂部表面上方並與其接觸，其中，該金屬互連材料填充該組溝槽及該組通孔；以及 阻擋層，位於該半導體互連裝置的頂部表面上方。
  12. 如申請專利範圍第11項所述的裝置，還包括：一組氣隙，位於該組通孔與該組溝槽的至少其中一些之間。
  13. 如申請專利範圍第11項所述的裝置，其中，該阻擋層包括含錳材料。
  14. 如申請專利範圍第11項所述的裝置，其中，該金屬互連材料包括貴金屬。
  15. 如申請專利範圍第14項所述的裝置，其中，該貴金屬包括：包括釕(Ru)、鈮(Nb)、銠(Rh)、銥(Ir)及鉑(PT)的群組的其中之一。
  16. 一種裝置，包括：中間半導體互連裝置，具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；阻擋層，位於該介電矩陣材料的頂部表面上方，加襯該組溝槽及該組通孔；金屬互連材料，直接位於該阻擋層上方並與其接觸，其中，該金屬互連材料填充該組溝槽及該組通孔，以及其中，該阻擋層被退火；以及介電覆蓋層，位於該中間半導體互連裝置上方。
  17. 如申請專利範圍第16項所述的裝置，還包括：一組氣隙，位於該組通孔與該組溝槽的至少其中一些之間。
  18. 如申請專利範圍第16項所述的裝置，其中，該阻擋層 包括含錳材料。
  19. 如申請專利範圍第16項所述的裝置，其中，該金屬互連材料包括貴金屬。
  20. 如申請專利範圍第19項所述的裝置，其中，該貴金屬包括：包括釕(Ru)、鈮(Nb)、銠(Rh)、銥(Ir)及鉑(PT)的群組的其中之一。
TW106106411A 2016-05-31 2017-02-24 形成具有改進黏附性的低電阻率貴金屬互連的裝置及方法 TW201812995A (zh)

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