TWI655715B - 形成低電阻率貴金屬互連之裝置及方法 - Google Patents

形成低電阻率貴金屬互連之裝置及方法 Download PDF

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TWI655715B
TWI655715B TW106105906A TW106105906A TWI655715B TW I655715 B TWI655715 B TW I655715B TW 106105906 A TW106105906 A TW 106105906A TW 106105906 A TW106105906 A TW 106105906A TW I655715 B TWI655715 B TW I655715B
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trenches
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張洵淵
法蘭克Ｗ 蒙特
埃羅爾 特德 萊恩
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格羅方德半導體公司
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Abstract

本發明提供製造積體電路裝置以形成低電阻率互連之裝置及方法。一種方法包括例如：獲得中間半導體互連裝置，該中間半導體互連裝置具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；沿該半導體互連裝置的頂部表面沉積阻擋層；在該阻擋層的頂部表面上方沉積並退火金屬互連材料，其中，該金屬互連材料填充該組溝槽及該組通孔；平坦化該中間半導體互連裝置的頂部表面；暴露該組溝槽與該組通孔之間的該阻擋層的一部分；以及沉積介電覆蓋層。本發明還揭露通過該方法形成的中間裝置。

Description

形成低電阻率貴金屬互連之裝置及方法
本發明關於半導體裝置以及製造半導體裝置之方法，尤其關於形成具有貴金屬的低電阻率金屬互連之互連裝置及方法。
對於5奈米及以下節點，隨著對更小電路結構及更快裝置性能的需求不斷增加，銅線電阻率開始攀升，從而降低該些節點的性能。5奈米節點及更小節點的開發將可能需要降低該些節點中的線的電阻率。
因此，可能希望開發在此類小尺寸下與銅相比具有較低電阻率的線的節點製造方法。
為克服現有技術的缺點並提供額外的優點，在一個態樣中提供一種方法，該方法包括例如：獲得中間半導體互連裝置，該中間半導體互連裝置具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；沿該半導體互連裝置的頂部表面沉積阻擋層；在該阻擋層的頂部表面上方沉積金屬互連材料，其中，該金屬互連材料填 充該組溝槽及該組通孔；退火該金屬互連材料；平坦化該中間半導體互連裝置的頂部表面，以移除該組溝槽及該組通孔上方的該金屬互連材料；暴露該組溝槽與該組通孔之間的該阻擋層的一部分；以及在該阻擋層的一組外表面上及該中間半導體互連裝置上方沉積介電覆蓋層。
在另一個態樣中，提供一種中間裝置，其包括例如：基板；覆蓋層；介電矩陣；一組通孔，延伸穿過該覆蓋層；一組溝槽，延伸進入該介電矩陣中，其中，該組溝槽及該組通孔包括貴金屬；以及介電覆蓋層。
100至170‧‧‧步驟
200‧‧‧裝置或中間半導體裝置
210‧‧‧基板
220‧‧‧覆蓋層
230‧‧‧介電矩陣
242‧‧‧通孔
244‧‧‧溝槽
250‧‧‧阻擋層
255‧‧‧阻擋層或部分
260‧‧‧金屬互連材料
270‧‧‧犧牲介電覆蓋層
272‧‧‧阻擋遮罩
280‧‧‧氣隙
290‧‧‧介電覆蓋層
900‧‧‧中間裝置
本發明的一個或多個態樣被特別指出並在說明書的結束處的聲明中被明確稱為示例。從下面結合附圖所作的詳細說明可清楚本發明的上述及其它目的、特徵以及優點，該些附圖中：第1圖顯示依據本發明的一個或多個態樣用以形成中間半導體互連結構的方法的一個實施例；第2圖顯示依據本發明的一個或多個態樣具有基板、覆蓋層以及包括一組溝槽及一組通孔的介電矩陣的中間半導體互連結構的一個實施例的剖切立視圖；第3圖顯示依據本發明的一個或多個態樣在沉積阻擋層及金屬互連材料以後的第2圖的結構；第4圖顯示依據本發明的一個或多個態樣在平坦化該中間半導體互連結構的頂部表面以後的第3圖的結構； 第5圖顯示依據本發明的一個或多個態樣在沉積犧牲介電覆蓋層以後的第4圖的結構；第6圖顯示依據本發明的一個或多個態樣在沉積阻擋遮罩並形成開口以後的第5圖的結構；第7圖顯示依據本發明的一個或多個態樣在形成一組氣隙並移除該犧牲介電覆蓋層及該阻擋遮罩以後的第6圖的結構；第8a圖顯示依據本發明的一個或多個態樣在氧化所暴露的阻擋層以後的第7圖的結構；第8b圖顯示依據本發明的一個或多個態樣在移除所暴露的阻擋層以後的第7圖的結構；第9a圖顯示依據本發明的一個或多個態樣在圍繞該氧化暴露阻擋層沉積介電覆蓋層以後的第8a圖的結構；第9b圖顯示依據本發明的一個或多個態樣在移除該暴露阻擋層之後接著沉積介電覆蓋層以後的第8b圖的結構；第10圖顯示依據本發明的一個或多個態樣具有基板、覆蓋層、介電矩陣、一組溝槽、一組通孔以及介電覆蓋層的中間裝置的一個實施例的剖切立視圖；第11圖顯示依據本發明的一個或多個態樣具有一組氣隙的第10圖的裝置；第12圖顯示具有圍繞該組通孔及該組溝槽的阻擋層的第11圖的裝置。
下面通過參照附圖中所示的非限制性例子來更加充分地解釋本發明的態樣及其特定的特徵、優點以及細節。省略對已知材料、製造工具、製程技術等的說明，以免在細節上不必要地模糊本發明。不過，應當理解，當說明本發明的實施例時，詳細說明及具體例子僅作為示例，而非限制。本領域的技術人員將會從本揭露中瞭解在基礎的發明概念的精神和/或範圍內的各種替代、修改、添加和/或佈局。還要注意，下面參照附圖，為方便理解，該些附圖並非按比例繪製，其中，不同附圖中所使用的相同附圖標記表示相同或類似的元件。
一般來說，本文揭露特定積體電路，其提供相對上述的現有半導體裝置及製程的優點。有利地，本文中所揭露的積體電路裝置製程提供與先前可能使用傳統銅線相比具有較低線電阻率的半導體裝置。
在一個態樣中，在一個實施例中，如第1圖中所示，依據本發明的一個或多個態樣的積體電路裝置形成製程可包括例如：獲得具有基板、覆蓋層以及包括一組溝槽及一組通孔的介電矩陣的中間半導體互連裝置100；沿該半導體互連裝置的頂部表面沉積阻擋層110；在該阻擋層的頂部表面上方沉積金屬互連材料120；退火該金屬互連材料130；平坦化該中間半導體互連裝置的頂部表面140；在該中間半導體互連裝置上方沉積犧牲介電覆蓋層及阻擋遮罩150；形成一組氣隙並移除該犧牲介電覆 蓋層及該阻擋遮罩160；以及在該阻擋層的一組外表面上及該中間半導體互連裝置上方沉積介電覆蓋層170。
第2至8圖顯示(僅示例)依據本發明的一個或多個態樣的半導體裝置形成製程的一部分及中間半導體互連裝置的一部分的一個詳細實施例。要注意的是，這些附圖並非按比例繪製，以促進理解本發明，且不同附圖中所使用的相同附圖標記表示相同或類似的元件。
第2圖顯示處於中間半導體製造階段的中間半導體裝置200的一部分。已依據所製造的裝置200的設計通過初始裝置製程步驟對裝置200進行了處理。例如，裝置200可包括例如基板210，在基板210上設有覆蓋層220，該覆蓋層可包括介電材料。基板210可為任意合適的材料，例如矽。另外，在基板210或覆蓋層220上可沉積介電矩陣230。介電矩陣230可包括一種或多種介電材料，且可包括材料混合矩陣或多個材料層(未顯示)。介電矩陣230可包括一組通孔242及一組溝槽244。如第2圖中所示，該組通孔242可延伸穿過覆蓋層220至下方特徵，而該組溝槽244可僅延伸進入介電矩陣230中。
在另一個實施例中(未顯示)，裝置200的基板可為例如絕緣體上覆矽(silicon on insulator；SOI)基板(未顯示)。例如，該SOI基板可包括隔離層(未顯示)，該隔離層可為局部埋置氧化物區(buride oxide；BOX)或任意合適的材料以電性隔離電晶體，與閘極結構對齊。在一些實施例中，該裝置為積體電路(integrated circuit；IC)的後端工 藝(back end of line；BEOL)部分的一部分。
如第2圖中所示，通過使用光刻及蝕刻製程，可已於介電矩陣230中蝕刻介電矩陣230和/或覆蓋層220，以定義該組通孔242及該組溝槽244。該蝕刻可通過任意合適的蝕刻製程執行，例如定向反應離子蝕刻(reactive ion etching；RIE)。
如第3圖中所示，通過原子層沉積(atomic layer deposition；ALD)、化學氣相沉積(chemical vapor deposition；CVD)、物理氣相沉積(physical vapor deposition；PVD)或當前已知或以後開發的任意其它合適的沉積技術，可沿裝置200的頂部表面沉積阻擋層250。例如，阻擋層250可具有鉭(Ta)、鈦(Ti)或錳(Mn)組分並可小於約3奈米(nm)厚，且在一些實施例中，小於約1.5奈米厚。如第3圖中所示，可使用能夠形成與變化表面共形的小於3奈米的一致薄膜或薄層的任意沉積來沉積阻擋層250。
也如第3圖中所示，在一些實施例中，在沉積阻擋層250之後，接著通過ALD或CVD在阻擋層250的頂部表面上方沉積金屬互連材料260。在一些實施例中，該金屬互連材料沉積約10奈米與約20奈米之間的厚度，以使其填充該組通孔242(第2圖)及該組溝槽244(第2圖)。金屬互連材料260可包括任意貴金屬，包括但不限於：釕(Ru)、鈮(Nb)、銠(Rh)、銥(Ir)、以及鉑(PT)。在沉積金屬互連材料260之後，接著在約350C至約500C範圍內熱退火該材料可幫助固化該材料。儘管傳統上銅(Cu)為 該互連材料的選擇，但隨著裝置的線寬不斷變小，銅的電阻率開始增加。相比之下，貴金屬在較小尺寸可具有更理想的電阻率。
例如，與在20奈米與6奈米之間不斷爬升的銅不同，Ru薄膜從20奈米至6奈米具有幾乎恒定的電阻率。在約5奈米，Ru可具有與Cu幾乎相同的電阻率，且在5奈米以下可具有較低的電阻率。另外，不像許多其它互連材料，Ru不會出現因電遷移(electromigration；EM)而導致的失效。貴金屬薄膜的時間相關介電擊穿(time dependent dielectric breakdown；TDDB)可比銅好至少10倍。不過，如下面進一步說明，通過增加與金屬互連材料260相鄰的層(例如阻擋層250)的電阻，可更進一步降低金屬互連材料260的電阻率。因此，就組成改變阻擋層250來增加電阻可降低金屬互連材料260的電阻。
如第4圖中所示，通過使用化學機械拋光，可平坦化並拋光裝置200的頂部表面，移除多餘金屬互連材料260並提供光滑表面，以在該光滑表面上繼續裝置製造。在一個實施例中，在此平坦化之後，接著可氧化阻擋層250(未顯示)，以降低金屬互連材料260的電阻。通過在惰性環境空氣中(在一些情況下具有小於約1%氧)退火該結構可實現氧化阻擋層250，而不破壞金屬互連材料260。在此實施例中，可顯著降低金屬互連材料260的電阻。
如第5圖中所示，在裝置200上方可沉積犧牲介電覆蓋層270。由於此覆蓋層用於遮蔽下方結構且不 用於最終裝置的運行，因此將其視為犧牲。
如第6圖中所示，例如通過使用標準光刻及蝕刻技術，在犧牲介電覆蓋層270的頂部表面上可形成阻擋遮罩272，且通過使用任意光刻技術可移除犧牲介電覆蓋層270，以在該組溝槽244及該組通孔242上方暴露並形成一個或多個開口。在使用阻擋遮罩272之後，接著可執行移除通孔蝕刻技術。
如第7圖中所示，例如通過在介電矩陣230內形成一組氣隙280可暴露該組通孔242與該組溝槽244的至少其中一些之間的阻擋層250的一部分。在一些實施例中，例如，可破壞介電矩陣230的區域(例如該組溝槽244與該組通孔242的其中一些或全部之間的區域)，以形成該組氣隙280。在一些實施例中，使用H2及N2電漿來破壞介電矩陣230。例如，通過使用稀釋氫氟酸可移除被破壞的材料，保留該組通孔242與該組溝槽244的至少其中一些之間的氣隙280。同時，通過使用同一材料可移除犧牲介電覆蓋層270及阻擋遮罩272。
如第8a圖中所示，形成氣隙280使阻擋層250的部分255暴露，通常為覆蓋金屬互連材料260(其填充該組通孔242及該組溝槽244)的側表面的全部或其中一些的部分。可氧化阻擋層255的這些部分，以增加其電阻率，從而有效降低金屬互連材料260的電阻率。此氧化可通過暴露於濕化學發生。在一些實施例中，其中，阻擋層250包括Ta或Ti金屬組分，該濕化學可包括過氧化氫(H2O2)。金屬互連材料260較難以氧化，尤其在室溫下，因此有效地，僅暴露阻擋層250氧化。
在替代實施例中，如第8b圖中所示，可移除而不是氧化阻擋層250的暴露部分。移除阻擋層250允許金屬互連材料260與介電覆蓋層290直接相接(第9b圖)，後面將作說明。介電覆蓋層290將具有與阻擋層250相比較高的電阻，因而降低最終裝置中的金屬互連材料260的電阻。阻擋層250的該暴露部分可通過暴露於濕化學來移除或者通過任意必要技術的蝕刻來移除。
如第9a圖中所示，在阻擋層250的一組外表面上以及中間半導體互連裝置200上方可沉積介電覆蓋層290。介電覆蓋層290可部分塗布阻擋層250，但保留氣隙280(第7圖)完好並被介電覆蓋層290覆蓋。
如第9b圖中所示，介電覆蓋層290可塗布所暴露的金屬互連材料260，也保留氣隙280(第7圖)完好。與第9a圖相比，該介電覆蓋層的材料(其可包括SiN或其它介電材料)將充當金屬互連材料260的介面。此材料可經選擇而具有高電阻率，其將降低最終IC中的金屬互連材料260的有效電阻。
第10圖顯示中間裝置900，依據一些實施例，該中間裝置包括基板210、覆蓋層220、介電矩陣230、延伸穿過覆蓋層220的一組通孔242、延伸進入介電矩陣230中的一組溝槽244、以及介電覆蓋層290。在這些實施例中，該組溝槽244及該組通孔242包括貴金屬。其它材 料如上所述。
如第11圖中所示，中間裝置900可包括位於該組通孔242與該組溝槽244的至少其中一些之間的一組氣隙280。可以看出，當具有氣隙280時，介電覆蓋層290可作為氣隙280的襯裡。
如第12圖中所示，阻擋層250圍繞該組通孔242及該組溝槽244，不過，在該組氣隙280附近的阻擋層255(在非正式附圖中顯示為橙色)是上面所揭露的具有Ta或Ti組分的阻擋層材料的其中一種的氧化材料。在一些實施例中，可氧化整個阻擋層250。
應當瞭解，上面所揭露的新穎的中間半導體互連裝置及其形成方法降低後端工藝(BEOL)互連形成及線的電阻。依據實施例，通過改變該互連本身的材料來降低該裝置的表面散射，且增加阻擋層的電阻降低該互連材料的最終電阻。由於電遷移現象減少，貴金屬作為互連材料是有利的，部分因為該金屬的較高熔點。另外，貴金屬更加抗氧化，從而使阻擋層更容易氧化。
本文中所使用的術語僅是出於說明特定實施例的目的，並非意圖限制本發明。除非上下文中明確指出，否則本文中所使用的單數形式“一個”以及“該”也意圖包括複數形式。還應當理解，術語“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(以及任意形式的包含)都是開放式連接動詞。因此，“包括”、“具有”或“包含”一個或多個步驟或元件的 方法或裝置具有那些一個或多個步驟或元件，但並不限於僅僅具有那些一個或多個步驟或元件。類似地，“包括”、“具有”或“包含”一個或多個特徵的一種方法的步驟或一種裝置的元件具有那些一個或多個特徵，但並不限於僅僅具有那些一個或多個特徵。而且，以特定方式配置的裝置或結構至少以那種方式配置，但也可以未列出的方式配置。
所附的申請專利範圍中的所有方式或步驟加功能元素的相應結構、材料、動作及等同(如果有的話)意圖包括結合具體請求保護的其它請求保護的元素執行該功能的任意結構、材料或動作。本發明的說明用於示例及說明目的，而非意圖詳盡無遺或限於所揭露形式的發明。許多修改及變更將對於本領域的普通技術人員顯而易見，而不背離本發明的範圍及精神。該些實施例經選擇及說明以最佳解釋本發明的一個或多個態樣的原理以及實際應用，並使本領域的普通技術人員能夠理解針對各種實施例具有適合所考慮的特定應用的各種變更的本發明的一個或多個態樣。

Claims (17)

  1. 一種用於製造半導體裝置之方法，該方法包括：獲得中間半導體互連裝置，該中間半導體互連裝置具有基板、覆蓋層，以及包括一組溝槽及一組通孔的介電矩陣；沿該半導體互連裝置的頂部表面沉積阻擋層；在該阻擋層的頂部表面上方沉積金屬互連材料，其中，該金屬互連材料填充該組溝槽及該組通孔，及其中，該金屬互連材料包括貴金屬；退火該金屬互連材料；平坦化該中間半導體互連裝置的頂部表面，以移除該組溝槽及該組通孔上方的該金屬互連材料；在該中間半導體互連裝置上方沉積犧牲介電覆蓋層及阻擋遮罩；在該組溝槽與該組通孔的至少其中一部分之間形成一組氣隙，移除該犧牲介電覆蓋層及該阻擋遮罩；暴露該組溝槽與該組通孔之間的該阻擋層的一部分；在所述平坦化該中間半導體互連裝置的該頂部表面之後，接著通過在有氧的周圍空氣中退火來氧化該阻擋層；以及在該阻擋層的一組外表面上及該中間半導體互連裝置上方沉積介電覆蓋層。
  2. 如申請專利範圍第1項所述的方法，還包括：在所述形成該組氣隙之後，接著氧化通過所述形成該組氣隙而暴露的一組區域中的該阻擋層。
  3. 如申請專利範圍第2項所述的方法，其中，通過將由所述形成暴露的該組區域暴露於濕化學來實施該氧化。
  4. 如申請專利範圍第3項所述的方法，其中，該濕化學包括H2O2。
  5. 如申請專利範圍第1項所述的方法，還包括：在該中間半導體互連裝置上方沉積犧牲介電覆蓋層及阻擋遮罩；在該組溝槽與該組通孔的至少其中一部分之間形成一組氣隙，移除該犧牲介電覆蓋層及該阻擋遮罩；以及在所述形成該組氣隙之後，接著移除通過所述形成該組氣隙而暴露的一組區域中的該阻擋層。
  6. 如申請專利範圍第5項所述的方法，其中，通過將由所述形成暴露的該組區域暴露於濕化學來實施該移除。
  7. 如申請專利範圍第1項所述的方法，其中，該氧小於1%。
  8. 如申請專利範圍第1項所述的方法，其中，該阻擋層包括小於約3奈米的厚度的具有Ta、Ti或Mn元素的由金屬組成的層，以及其中，該金屬互連材料沉積約10奈米與約20奈米之間的厚度。
  9. 如申請專利範圍第8項所述的方法，其中，該阻擋層包括小於約1.5奈米的厚度。
  10. 如申請專利範圍第8項所述的方法，其中，該阻擋層通過包括原子層沉積(ALD)、化學氣相沉積(CVD)以及物理氣相沉積(PVD)的群組的其中之一來沉積，以及其中，該金屬互連材料通過包括化學氣相沉積及原子層沉積的群組的其中之一來沉積。
  11. 如申請專利範圍第1項所述的方法，其中，該退火發生於約350C至約500C。
  12. 如申請專利範圍第1項所述的方法，其中，所述沉積該介電覆蓋層在該組通孔與該組溝槽之間的區域中形成一組氣隙。
  13. 一種中間裝置，包括：基板；覆蓋層；介電矩陣；一組通孔，延伸穿過該覆蓋層；一組溝槽，延伸進入該介電矩陣中，其中，該組溝槽及該組通孔包括貴金屬；一組氣隙，位於該組通孔與該組溝槽的至少其中一些之間；以及介電覆蓋層。
  14. 如申請專利範圍第13項所述的中間裝置，還包括：阻擋層，圍繞該組通孔及該組溝槽，其中，在該組氣隙附近的該阻擋層包括氧化材料。
  15. 如申請專利範圍第14項所述的中間裝置，其中，不在該組氣隙附近的該阻擋層包括Ta、Ti或Mn元素。
  16. 如申請專利範圍第13項所述的中間裝置，還包括：阻擋層，圍繞該組通孔及該組溝槽，其中，該阻擋層包括氧化材料。
  17. 如申請專利範圍第16項所述的中間裝置，其中，該阻擋層包括氧化的含Ta材料或氧化的含Ti材料。
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