US20150061141A1 - Interconnect structures and methods of forming same - Google Patents
Interconnect structures and methods of forming same Download PDFInfo
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- US20150061141A1 US20150061141A1 US14/019,276 US201314019276A US2015061141A1 US 20150061141 A1 US20150061141 A1 US 20150061141A1 US 201314019276 A US201314019276 A US 201314019276A US 2015061141 A1 US2015061141 A1 US 2015061141A1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- the semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.
- various electronic components e.g., transistors, diodes, resistors, capacitors, etc.
- Conductive materials such as metals or semiconductors are used in semiconductor devices for making electrical connections for the integrated circuits.
- aluminum was used as a metal for conductive materials for electrical connections
- silicon dioxide was used as an insulator.
- the materials for conductors and insulators have changed, to improve device performance.
- FIGS. 1A through 6 are top-views and cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment
- FIG. 7 is a process flow diagram of the process shown in FIGS. 1A through 6 in accordance with an embodiment.
- FIGS. 1A through 6 are top-views and cross-sectional views of intermediate stages in the manufacturing of a interconnect structure in accordance with an embodiment
- FIG. 7 is a process flow of the process shown in FIGS. 1A through 6 .
- FIG. 1A is a top-view of the semiconductor device 10 with FIG. 1B being a cross-sectional view of FIG. 1A along the line A-A.
- the semiconductor device 10 includes a substrate 20 , which may be a part of a wafer, a dielectric layer 24 , and a conductive line 26 in the dielectric layer 24 .
- the substrate 20 may comprise a semiconductor material such as silicon, germanium, diamond, or the like.
- the substrate 20 may comprise a silicon-on-insulator (SOI) substrate.
- SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof.
- the substrate 20 may be doped with a p-type dopant, such as boron, aluminum, gallium, or the like, although the substrate may alternatively be doped with an n-type dopant, as is known in the art.
- the substrate 20 may include active and passive devices 22 .
- active and passive devices 22 may be formed using any suitable methods. Only a portion of the substrate 20 is illustrated in the figures, as this is sufficient to fully describe the illustrative embodiments.
- the dielectric layer 24 is formed over the substrate 20 (step 202 ).
- the dielectric layer 24 may be formed of oxides such as silicon oxide, borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof.
- the low-k dielectric materials may have k values lower than 3.9.
- the dielectric layer 24 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-on-dielectric (SOD) process, the like, or a combination thereof.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- ALD atomic layer deposition
- SOD spin-on-dielectric
- the dielectric layer 24 is formed directly on a top surface of the substrate 20 .
- the dielectric layer 24 is formed on intermediate layers and/or structures (not shown) which are on substrate 20 .
- the dielectric layer 24 is an inter-layer dielectric (ILD).
- the conductive line 26 may be formed in the dielectric layer 24 (step 204 ).
- the conductive line 26 is formed in recesses (not shown) in the dielectric layer 24 . These recesses may be formed using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch.
- the conductive line is formed and patterned on a first portion of the dielectric layer 24 (e.g. portion below the conductive line 26 ) with a second portion of the dielectric layer 24 being formed around the patterned conductive line 26 .
- a barrier layer (not shown) may be formed between the conductive line 26 and the dielectric layer 24 .
- the barrier layer may help to block diffusion of the subsequently formed conductive line 26 into adjacent dielectric materials such as the dielectric layer 24 .
- the barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, polybenzoxazole (PBO) the like, or a combination thereof.
- the barrier layer may be formed by CVD, PVD, plasma enhanced CVD (PECVD), ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer is omitted.
- the conductive line 26 may be formed on the barrier layer, if the barrier layer is present.
- the conductive line 26 may also be referred to as a metal layer M X and may be the first metal layer (M 1 ) over the substrate or may any number metal layer over the substrate (e.g. M 5 , M 10 , M 100 ).
- the conductive line 26 may comprise copper, aluminum, the like, or a combination thereof.
- the conductive line 26 may be formed through a deposition process such as electrochemical plating (ECP) process, CVD, PVD, the like, or a combination thereof.
- ECP electrochemical plating
- the conductive line 26 is formed on a seed layer, such as a copper alloy and formed by an ECP process.
- the conductive line 26 is formed to a thickness from about 100 ⁇ to about 7000 ⁇ .
- the conductive lines 26 may be planarized by a chemical mechanical polish (CMP) process or an etching process.
- CMP chemical mechanical polish
- a top surface of the conductive line 26 is substantially coplanar with a top surface of the dielectric layer 24 .
- a photoresist 28 may be formed and patterned over the conductive line 26 (step 206 ) as illustrated in FIGS. 2A and 2B .
- FIG. 2B is a cross-sectional view of FIG. 2A along a line similar to line A-A in FIG. 1A but is not shown in FIG. 2A for clarity.
- a photoresist 28 may be deposited and patterned over the conductive line 26 and the dielectric layer 24 .
- the photoresist 28 may comprise a conventional photoresist material, such as a deep ultra-violet (DUV) photoresist, and may be deposited on the top surfaces of the conductive line 26 and the dielectric layer 24 , for example, by using a spin-on process to place the photoresist 28 .
- DUV deep ultra-violet
- any other suitable material or method of forming or placing the photoresist 28 may alternatively be utilized.
- the photoresist 28 may be exposed to energy, e.g. light, through a patterned reticle in order to induce a reaction in those portions of the photoresist 28 exposed to the energy.
- the photoresist 28 may then be developed, and portions of the photoresist 28 may be removed forming openings 30 , exposing portions of a top surface 26 A of conductive line 26 through the openings 30 .
- the conductive line has a width W 1 and the opening 30 has a width W 2 , the width W 2 being larger than the width W 1 , and thus exposing portions of a top surface 24 A of the dielectric layer 24 in openings 30 .
- the widths W 2 and W 1 are substantially equal such that only portions of the top surface 26 A of the conductive line are exposed in the openings 30 .
- the conductive line 26 may be patterned (step 208 ) to expose a top surface 24 A of the dielectric layer 24 as illustrated in FIGS. 3A and 3B .
- FIG. 3B is a cross-sectional view of FIG. 3A along a line similar to line A-A in FIG. 1A but is not shown in FIG. 3A for clarity.
- the patterning of the conductive line 26 forms multiple conductive lines 26 .
- the conductive lines 26 may have a spacing S 1 between adjacent conductive lines 26 in a range from 5 nm to about 40 nm.
- the spacing S 1 may also be referred to as an end-to-end spacing.
- the patterning may be performed by a dry etch process or ion bombardment with a plasma/ion source and an etchant gas such as H 2 , NH 3 , Ar, He, Cl 2 the like, or a combination thereof.
- the patterning process etches the conductive line 26 and forms recesses in the dielectric layer 24 between the patterned conductive lines 26 . These recesses have sidewalls 24 B of the dielectric layer and sidewalls 26 B of the conductive lines 26 .
- W 2 being larger than W 1
- portions of the dielectric layer 24 exposed in the openings 30 are also removed by the patterning of the conductive line 26 .
- FIG. 3B illustrates three conductive lines 26 along a single longitudinal axis, there may be adjacent, parallel conductive lines 26 formed at a same time and by a same process as illustrated in FIG. 3C .
- FIGS. 3B and 3C illustrate three conductive lines 26 and seven conductive lines 26 , respectively, there may be more or less conductive lines 26 as desired.
- FIG. 4 through 6 are cross-sectional views of further stages of processing along a line similar to line A-A in FIG. 1A .
- FIG. 4 illustrates forming a selective conductive layer 32 on the conductive lines 26 (step 210 ).
- the selective conductive layer 32 may be a capping/barrier layer and will be referred to as a capping layer 32 hereinafter.
- the capping layer 32 is formed on the top surfaces 26 A of the conductive lines 26 and on the sidewalls 26 B of the conductive lines 26 .
- the capping layer 32 disposed over the conductive lines 26 improves the electromigration characteristics of the conductive lines 26 and also improves the adhesion between the subsequently formed etch stop layer 34 (see FIG. 5 ) and the conductive lines 26 .
- the capping layer 32 has a thickness ranging from about 10 ⁇ to about 1000 ⁇ formed by a deposition process including low-pressure CVD (LPCVD), CVD, PECVD, plasma-enhanced ALD (PEALD), PVD, sputtering, the like, or a combination thereof.
- LPCVD low-pressure CVD
- CVD chemical vapor deposition
- PEALD plasma-enhanced ALD
- PVD sputtering, the like, or a combination thereof.
- the capping layer 32 is not formed on the surface of the dielectric layer 24 but is only formed on the conductive lines 26 .
- the capping layer 32 is a metal-containing layer.
- the capping layer 32 includes Co, Cu, W, Al, Mn, Ru, Ta, the like, or combinations and alloys thereof.
- the capping layer 32 includes a Co layer formed by introducing a cobalt-containing chemical such as cyclopentadienylcobalt dicarbonyl (CPCo(CO) 2 ), dicobalt octacarbonyl (Co 2 (CO) 8 ), or decamethylcobaltocene (CoCp 2 ) with a plasma source such as H 2 , NH 3 , Ar, He, the like, or a combination thereof in which the semiconductor device 10 is being processed.
- CPCo(CO) 2 cyclopentadienylcobalt dicarbonyl
- Co 2 (CO) 8 dicobalt octacarbonyl
- decamethylcobaltocene CoCp 2
- the capping layer 32 is selectively formed on the conductive lines 26 . In other embodiments, the capping layer 32 is formed entirely over the semiconductor device 10 and then subjected to a patterning process to remove the portion of capping layer 32 on the dielectric layer 24 , while leaving another portion of capping layer 32 on the conductive lines 26 .
- FIG. 5 illustrates the formation of an etch stop layer (ESL) 34 on the capping layers 32 and the dielectric layer 24 (step 212 ).
- the ESL 34 acts as an etch stop layer for the subsequent formation of conductive vias 38 to the conductive lines 26 (see FIG. 6 ).
- the ESL 34 may be made of one or more suitable dielectric materials such as silicon oxide, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, combinations of these, or the like.
- the ESL 34 may be deposited through a process such as CVD, an SOD process, although any acceptable process may be utilized to form the ESL 34 .
- FIG. 6 illustrates the semiconductor device 10 after a via layer V X is formed over the conductive lines 26 of the metal layer M X and another metal layer M X+1 is formed on the via layer V X .
- the semiconductor device 10 may also be referred to as an interconnect structure 10 .
- a dielectric layer 36 is formed over the ESL 34 .
- the dielectric layer 36 may be formed of oxides such as silicon oxide, BPSG, USG, FSG, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof.
- the low-k dielectric materials may have k values lower than 3.9.
- the dielectric layer 36 may be deposited by CVD, PVD, ALD, an SOD process, the like, or a combination thereof. In some embodiments, the dielectric layer 36 is an ILD. In an embodiment, the dielectric layer 36 has a bottom surface portion lower than top surfaces of the conductive lines 26 .
- openings may be formed through the dielectric layer 36 and the ESL 34 to expose portions of the capping layer 32 and/or the conductive lines 26 .
- the openings allows for the electrical and physical coupling between the conductive line 26 and the conductive vias 38 .
- the openings may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the capping layer 32 and/or conductive lines 26 may be used.
- the conductive vias 38 are formed in the openings.
- the conductive vias 38 include a barrier layer (not shown) formed in the openings. The barrier layer helps to block diffusion of the subsequently formed conductive vias 38 into adjacent dielectric materials such as the dielectric layer 36 .
- the barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, PBO, the like, or a combination thereof.
- the barrier layer may be formed by CVD, PVD, PECVD, ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer is omitted.
- the conductive vias 38 are formed in the openings and, if present, on the barrier layer.
- the conductive vias 38 electrically couple the conductive lines 26 in the metal layer M X below and subsequently formed conductive lines 40 in the layers M X+1 above.
- the conductive vias 38 may be formed of copper, aluminum, the like, or a combination thereof.
- the conductive vias 38 may be formed through a deposition process such as electrochemical plating, CVD, PVD, the like, or a combination thereof.
- the conductive vias 38 are formed on a seed layer (not shown), such as a copper alloy and formed by an ECP process.
- the conductive vias 38 extend through the capping layer 32 to directly contact the conductive lines 26 . In other embodiments, the conductive vias 38 do not extend through the capping layer 32
- the conductive vias 38 are planarized by a CMP process or an etching process. In these embodiments, the conductive vias 38 have a top surface that is substantially coplanar with the top surface of the dielectric layer 36 .
- the conductive lines 40 are formed on the conductive vias 38 and the dielectric layer 36 .
- the conductive lines 40 may be formed by similar materials and processes as the conductive lines 26 described above and the descriptions are not repeated herein, although the conductive lines 40 and 26 need not be the same.
- the conductive vias 38 and the conductive lines 40 could be formed by a damascene process, such as a dual damascene process any other suitable process to form conductive vias and lines.
- a capping layer 42 and an ESL 44 are formed over the conductive lines 40 .
- the capping layer 42 improves the electromigration characteristics of the conductive lines 40 and also improves the adhesion between the subsequently formed etch stop layer 44 and the conductive lines 40 .
- the capping layer 42 may be selectively formed on the conductive lines 40 but not on the dielectric layer 36 .
- the capping layer 42 may be formed by similar materials and processes as the capping layer 32 described above and the descriptions are not repeated herein, although the capping layers 42 and 32 need not be the same.
- the ESL 44 is formed on the capping layers 42 and the dielectric layer 36 .
- the ESL 44 acts as an etch stop layer for the subsequent conductive features (not shown) formed to the conductive lines 40 .
- the ESL 44 may be formed by similar materials and processes as the ESL 34 described above and the descriptions are not repeated herein, although the ESLs 44 and 34 need not be the same.
- the number of conductive lines 26 and 40 and metal layers M X and M X+1 are only for illustrative purposes and are not limiting. There could be any suitable number conductive lines 26 and 40 and metal layers M X and M X+1 . For example, there could be two more metal layers M X+2 and M X+3 formed over the metal layer M X+1 and formed in a similar manner as described above. Further, there may be devices, structures, and/or connectors formed over and electrically coupled to the metal layers M X through M X+1 and the active and passive devices 22 to form functional circuitry.
- forming the conductive line in a dielectric layer and then etching it to form separate conductive lines allows the end-to-end spacing between the conductive lines to shrink. This improves the reliability of 10 nm technology node and even smaller future technology nodes.
- the process includes a selective capping layer between the conductive lines and an etch stop layer to improve adhesion of the etch stop layer.
- the profile shape of the conductive lines can be controlled better than the profile of a conductive line formed with a double-patterning process.
- the etched conductive lines process is also a simpler process than a double-patterning process which reduces the process stage and the overall cost of the device.
- An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing.
- the method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.
- Another embodiment is a method of forming a interconnect structure, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and etching the first conductive layer to form a first conductive line and a second conductive line, the first conductive line being separated from the second conductive line by a first spacing.
- the method further includes forming a first capping layer on top surfaces and sidewalls of the first and second conductive lines, forming a first etch stop layer on the first capping layer and the first dielectric layer, and forming a second dielectric layer over the etch stop layer, the second dielectric layer adjoining top surfaces and sidewalls of the etch stop layer.
- a further embodiment is an interconnect structure including a first dielectric layer over a substrate, a first metal line in the first dielectric layer, and a second metal line in the first dielectric layer, the second metal line laterally separated from the first metal line by a first spacing.
- the interconnect structure further includes a capping layer on top surfaces and sidewalls of the first and second metal lines, and a second dielectric layer over the capping layer, the second dielectric layer having a bottom surface lower than top surfaces of the first and second metal lines.
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Abstract
Description
- Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area.
- Conductive materials such as metals or semiconductors are used in semiconductor devices for making electrical connections for the integrated circuits. For many years, aluminum was used as a metal for conductive materials for electrical connections, and silicon dioxide was used as an insulator. However, as devices are decreased in size, the materials for conductors and insulators have changed, to improve device performance.
- For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
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FIGS. 1A through 6 are top-views and cross-sectional views of intermediate stages in the manufacturing of a semiconductor device in accordance with an embodiment; and -
FIG. 7 is a process flow diagram of the process shown inFIGS. 1A through 6 in accordance with an embodiment. - The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.
- Semiconductor devices and methods of forming the same are provided in accordance with various embodiments. The intermediate stages of forming the semiconductor devices are illustrated. Some variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments are discussed in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps described herein.
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FIGS. 1A through 6 are top-views and cross-sectional views of intermediate stages in the manufacturing of a interconnect structure in accordance with an embodiment, andFIG. 7 is a process flow of the process shown inFIGS. 1A through 6 . - With reference now to
FIGS. 1A and 1B , there is shown asemiconductor device 10 at an intermediate stage of processing according to an embodiment.FIG. 1A is a top-view of thesemiconductor device 10 withFIG. 1B being a cross-sectional view ofFIG. 1A along the line A-A. Thesemiconductor device 10 includes asubstrate 20, which may be a part of a wafer, adielectric layer 24, and aconductive line 26 in thedielectric layer 24. Thesubstrate 20 may comprise a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, thesubstrate 20 may comprise a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Thesubstrate 20 may be doped with a p-type dopant, such as boron, aluminum, gallium, or the like, although the substrate may alternatively be doped with an n-type dopant, as is known in the art. - The
substrate 20 may include active andpassive devices 22. As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for thesemiconductor device 10. The active andpassive devices 22 may be formed using any suitable methods. Only a portion of thesubstrate 20 is illustrated in the figures, as this is sufficient to fully describe the illustrative embodiments. - The
dielectric layer 24 is formed over the substrate 20 (step 202). Thedielectric layer 24 may be formed of oxides such as silicon oxide, borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof. The low-k dielectric materials may have k values lower than 3.9. Thedielectric layer 24 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-on-dielectric (SOD) process, the like, or a combination thereof. In an embodiment, thedielectric layer 24 is formed directly on a top surface of thesubstrate 20. In other embodiments, thedielectric layer 24 is formed on intermediate layers and/or structures (not shown) which are onsubstrate 20. In some embodiments, thedielectric layer 24 is an inter-layer dielectric (ILD). - The
conductive line 26 may be formed in the dielectric layer 24 (step 204). In some embodiments, theconductive line 26 is formed in recesses (not shown) in thedielectric layer 24. These recesses may be formed using acceptable photolithography and etching techniques such as, for example, an anisotropic dry etch. In other embodiments, the conductive line is formed and patterned on a first portion of the dielectric layer 24 (e.g. portion below the conductive line 26) with a second portion of thedielectric layer 24 being formed around the patternedconductive line 26. - A barrier layer (not shown) may be formed between the
conductive line 26 and thedielectric layer 24. The barrier layer may help to block diffusion of the subsequently formedconductive line 26 into adjacent dielectric materials such as thedielectric layer 24. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, polybenzoxazole (PBO) the like, or a combination thereof. The barrier layer may be formed by CVD, PVD, plasma enhanced CVD (PECVD), ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer is omitted. - The
conductive line 26 may be formed on the barrier layer, if the barrier layer is present. Theconductive line 26 may also be referred to as a metal layer MX and may be the first metal layer (M1) over the substrate or may any number metal layer over the substrate (e.g. M5, M10, M100). Theconductive line 26 may comprise copper, aluminum, the like, or a combination thereof. Theconductive line 26 may be formed through a deposition process such as electrochemical plating (ECP) process, CVD, PVD, the like, or a combination thereof. In some embodiments, theconductive line 26 is formed on a seed layer, such as a copper alloy and formed by an ECP process. In an embodiment, theconductive line 26 is formed to a thickness from about 100 Å to about 7000 Å. In an embodiment, theconductive lines 26 may be planarized by a chemical mechanical polish (CMP) process or an etching process. In some embodiments, a top surface of theconductive line 26 is substantially coplanar with a top surface of thedielectric layer 24. - After
conductive line 26 is formed, aphotoresist 28 may be formed and patterned over the conductive line 26 (step 206) as illustrated inFIGS. 2A and 2B .FIG. 2B is a cross-sectional view ofFIG. 2A along a line similar to line A-A inFIG. 1A but is not shown inFIG. 2A for clarity. Aphotoresist 28 may be deposited and patterned over theconductive line 26 and thedielectric layer 24. Thephotoresist 28 may comprise a conventional photoresist material, such as a deep ultra-violet (DUV) photoresist, and may be deposited on the top surfaces of theconductive line 26 and thedielectric layer 24, for example, by using a spin-on process to place thephotoresist 28. However, any other suitable material or method of forming or placing thephotoresist 28 may alternatively be utilized. Once thephotoresist 28 has been formed, thephotoresist 28 may be exposed to energy, e.g. light, through a patterned reticle in order to induce a reaction in those portions of thephotoresist 28 exposed to the energy. Thephotoresist 28 may then be developed, and portions of thephotoresist 28 may be removed formingopenings 30, exposing portions of atop surface 26A ofconductive line 26 through theopenings 30. In some embodiments, the conductive line has a width W1 and theopening 30 has a width W2, the width W2 being larger than the width W1, and thus exposing portions of atop surface 24A of thedielectric layer 24 inopenings 30. In other embodiments, the widths W2 and W1 are substantially equal such that only portions of thetop surface 26A of the conductive line are exposed in theopenings 30. - After the
photoresist 28 is patterned, theconductive line 26 may be patterned (step 208) to expose atop surface 24A of thedielectric layer 24 as illustrated inFIGS. 3A and 3B .FIG. 3B is a cross-sectional view ofFIG. 3A along a line similar to line A-A inFIG. 1A but is not shown inFIG. 3A for clarity. The patterning of theconductive line 26 forms multipleconductive lines 26. Theconductive lines 26 may have a spacing S1 between adjacentconductive lines 26 in a range from 5 nm to about 40 nm. The spacing S1 may also be referred to as an end-to-end spacing. In an embodiment, the patterning may be performed by a dry etch process or ion bombardment with a plasma/ion source and an etchant gas such as H2, NH3, Ar, He, Cl2 the like, or a combination thereof. In some embodiments, the patterning process etches theconductive line 26 and forms recesses in thedielectric layer 24 between the patternedconductive lines 26. These recesses have sidewalls 24B of the dielectric layer and sidewalls 26B of theconductive lines 26. In the embodiments with W2 being larger than W1, portions of thedielectric layer 24 exposed in theopenings 30 are also removed by the patterning of theconductive line 26. AlthoughFIG. 3B illustrates threeconductive lines 26 along a single longitudinal axis, there may be adjacent, parallelconductive lines 26 formed at a same time and by a same process as illustrated inFIG. 3C . AlthoughFIGS. 3B and 3C illustrate threeconductive lines 26 and sevenconductive lines 26, respectively, there may be more or lessconductive lines 26 as desired. -
FIG. 4 through 6 are cross-sectional views of further stages of processing along a line similar to line A-A inFIG. 1A .FIG. 4 illustrates forming a selectiveconductive layer 32 on the conductive lines 26 (step 210). The selectiveconductive layer 32 may be a capping/barrier layer and will be referred to as acapping layer 32 hereinafter. In some embodiments, thecapping layer 32 is formed on thetop surfaces 26A of theconductive lines 26 and on the sidewalls 26B of theconductive lines 26. Thecapping layer 32 disposed over theconductive lines 26 improves the electromigration characteristics of theconductive lines 26 and also improves the adhesion between the subsequently formed etch stop layer 34 (seeFIG. 5 ) and theconductive lines 26. In some embodiments, thecapping layer 32 has a thickness ranging from about 10 Å to about 1000 Å formed by a deposition process including low-pressure CVD (LPCVD), CVD, PECVD, plasma-enhanced ALD (PEALD), PVD, sputtering, the like, or a combination thereof. In an embodiment, thecapping layer 32 is not formed on the surface of thedielectric layer 24 but is only formed on theconductive lines 26. - The
capping layer 32, for example, is a metal-containing layer. In some embodiments, thecapping layer 32 includes Co, Cu, W, Al, Mn, Ru, Ta, the like, or combinations and alloys thereof. In an embodiment, thecapping layer 32 includes a Co layer formed by introducing a cobalt-containing chemical such as cyclopentadienylcobalt dicarbonyl (CPCo(CO)2), dicobalt octacarbonyl (Co2(CO)8), or decamethylcobaltocene (CoCp2) with a plasma source such as H2, NH3, Ar, He, the like, or a combination thereof in which thesemiconductor device 10 is being processed. In some embodiments, thecapping layer 32 is selectively formed on theconductive lines 26. In other embodiments, thecapping layer 32 is formed entirely over thesemiconductor device 10 and then subjected to a patterning process to remove the portion of cappinglayer 32 on thedielectric layer 24, while leaving another portion of cappinglayer 32 on theconductive lines 26. -
FIG. 5 illustrates the formation of an etch stop layer (ESL) 34 on the capping layers 32 and the dielectric layer 24 (step 212). TheESL 34 acts as an etch stop layer for the subsequent formation ofconductive vias 38 to the conductive lines 26 (seeFIG. 6 ). TheESL 34 may be made of one or more suitable dielectric materials such as silicon oxide, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, combinations of these, or the like. TheESL 34 may be deposited through a process such as CVD, an SOD process, although any acceptable process may be utilized to form theESL 34. -
FIG. 6 illustrates thesemiconductor device 10 after a via layer VX is formed over theconductive lines 26 of the metal layer MX and another metal layer MX+1 is formed on the via layer VX. Thesemiconductor device 10 may also be referred to as aninterconnect structure 10. After theESL 34 is formed, adielectric layer 36 is formed over theESL 34. Thedielectric layer 36 may be formed of oxides such as silicon oxide, BPSG, USG, FSG, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, the like, or a combination thereof. The low-k dielectric materials may have k values lower than 3.9. Thedielectric layer 36 may be deposited by CVD, PVD, ALD, an SOD process, the like, or a combination thereof. In some embodiments, thedielectric layer 36 is an ILD. In an embodiment, thedielectric layer 36 has a bottom surface portion lower than top surfaces of theconductive lines 26. - After the
dielectric layer 36 is formed, openings (not shown) may be formed through thedielectric layer 36 and theESL 34 to expose portions of thecapping layer 32 and/or theconductive lines 26. The openings allows for the electrical and physical coupling between theconductive line 26 and theconductive vias 38. The openings may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of thecapping layer 32 and/orconductive lines 26 may be used. - After the openings are formed through the
dielectric layer 36, theconductive vias 38 are formed in the openings. In some embodiments, theconductive vias 38 include a barrier layer (not shown) formed in the openings. The barrier layer helps to block diffusion of the subsequently formedconductive vias 38 into adjacent dielectric materials such as thedielectric layer 36. The barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, PBO, the like, or a combination thereof. The barrier layer may be formed by CVD, PVD, PECVD, ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer is omitted. - The
conductive vias 38 are formed in the openings and, if present, on the barrier layer. Theconductive vias 38 electrically couple theconductive lines 26 in the metal layer MX below and subsequently formedconductive lines 40 in the layers MX+1 above. Theconductive vias 38 may be formed of copper, aluminum, the like, or a combination thereof. Theconductive vias 38 may be formed through a deposition process such as electrochemical plating, CVD, PVD, the like, or a combination thereof. In an embodiment, theconductive vias 38 are formed on a seed layer (not shown), such as a copper alloy and formed by an ECP process. In some embodiments, theconductive vias 38 extend through thecapping layer 32 to directly contact theconductive lines 26. In other embodiments, theconductive vias 38 do not extend through thecapping layer 32 - In some embodiments, the
conductive vias 38 are planarized by a CMP process or an etching process. In these embodiments, theconductive vias 38 have a top surface that is substantially coplanar with the top surface of thedielectric layer 36. - After the
conductive vias 38 are formed, theconductive lines 40 are formed on theconductive vias 38 and thedielectric layer 36. In some embodiments, theconductive lines 40 may be formed by similar materials and processes as theconductive lines 26 described above and the descriptions are not repeated herein, although theconductive lines conductive vias 38 and theconductive lines 40 could be formed by a damascene process, such as a dual damascene process any other suitable process to form conductive vias and lines. - After the
conductive lines 40 are formed, acapping layer 42 and anESL 44 are formed over theconductive lines 40. Thecapping layer 42 improves the electromigration characteristics of theconductive lines 40 and also improves the adhesion between the subsequently formedetch stop layer 44 and theconductive lines 40. Thecapping layer 42 may be selectively formed on theconductive lines 40 but not on thedielectric layer 36. Thecapping layer 42 may be formed by similar materials and processes as thecapping layer 32 described above and the descriptions are not repeated herein, although the capping layers 42 and 32 need not be the same. - The
ESL 44 is formed on the capping layers 42 and thedielectric layer 36. TheESL 44 acts as an etch stop layer for the subsequent conductive features (not shown) formed to theconductive lines 40. TheESL 44 may be formed by similar materials and processes as theESL 34 described above and the descriptions are not repeated herein, although theESLs - The number of
conductive lines conductive lines passive devices 22 to form functional circuitry. - It has been found that forming the conductive line in a dielectric layer and then etching it to form separate conductive lines allows the end-to-end spacing between the conductive lines to shrink. This improves the reliability of 10 nm technology node and even smaller future technology nodes. The process includes a selective capping layer between the conductive lines and an etch stop layer to improve adhesion of the etch stop layer. Also, the profile shape of the conductive lines can be controlled better than the profile of a conductive line formed with a double-patterning process. The etched conductive lines process is also a simpler process than a double-patterning process which reduces the process stage and the overall cost of the device.
- An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.
- Another embodiment is a method of forming a interconnect structure, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and etching the first conductive layer to form a first conductive line and a second conductive line, the first conductive line being separated from the second conductive line by a first spacing. The method further includes forming a first capping layer on top surfaces and sidewalls of the first and second conductive lines, forming a first etch stop layer on the first capping layer and the first dielectric layer, and forming a second dielectric layer over the etch stop layer, the second dielectric layer adjoining top surfaces and sidewalls of the etch stop layer.
- A further embodiment is an interconnect structure including a first dielectric layer over a substrate, a first metal line in the first dielectric layer, and a second metal line in the first dielectric layer, the second metal line laterally separated from the first metal line by a first spacing. The interconnect structure further includes a capping layer on top surfaces and sidewalls of the first and second metal lines, and a second dielectric layer over the capping layer, the second dielectric layer having a bottom surface lower than top surfaces of the first and second metal lines.
- Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
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