CN104779254A - 薄膜晶体管阵列面板及其制造方法 - Google Patents

薄膜晶体管阵列面板及其制造方法 Download PDF

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Publication number
CN104779254A
CN104779254A CN201410850991.2A CN201410850991A CN104779254A CN 104779254 A CN104779254 A CN 104779254A CN 201410850991 A CN201410850991 A CN 201410850991A CN 104779254 A CN104779254 A CN 104779254A
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China
Prior art keywords
layer
source electrode
passivation layer
drain electrode
electrode
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Inventor
朱迅
朴在佑
宋栽沅
李金熙
崔畯焕
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种薄膜晶体管阵列面板及其制造方法。栅极电极设置在基板上。半导体层设置在栅极电极上。栅极绝缘层设置在栅极电极和半导体层之间。源极电极设置在半导体层的第一侧，并具有第一侧表面。漏极电极设置在半导体层的第二侧，并具有第二侧表面。第一和第二侧表面限定重叠栅极电极的间隔。金属硅化物层设置在第一和第二侧表面上。钝化层设置在金属硅化物层、源极电极和漏极电极上。钝化层不与第一和第二侧表面接触。

Description

薄膜晶体管阵列面板及其制造方法
技术领域
本发明涉及薄膜晶体管阵列面板及其制造方法。
背景技术
显示器诸如液晶显示器(LCD)、有机发光二极管(OLED)显示器等包括多对电场产生电极和插置在其间的电光有源层。液晶显示器包括作为电光有源层的液晶层，有机发光二极管显示器包括作为电光有源层的有机发光层。
场产生电极连接到开关元件以接收电信号，电光有源层将电信号转变成光信号以显示图像。这样的开关元件包括薄膜晶体管。薄膜晶体管包括传送控制薄膜晶体管的扫描信号的栅极线和传送被施加到像素电极的信号的数据线。
随着显示装置的显示区域变大，需要信号更快地传播通过显示区域。
发明内容
根据本发明的一示例性实施方式，一种薄膜晶体管阵列面板被提供如下。栅极电极设置在基板上。半导体层设置在栅极电极上。栅极绝缘层设置在栅极电极和半导体层之间。源极电极设置在半导体层的第一侧，并具有第一侧表面。漏极电极设置在半导体层的第二侧，并具有第二侧表面。第一和第二侧表面限定重叠栅极电极的间隔。金属硅化物层设置在第一和第二侧表面上。钝化层设置在金属硅化物层、源极电极和漏极电极上。
根据本发明的一示例性实施方式，一种制造薄膜晶体管阵列面板的方法被提供如下。在基板上形成栅极电极。在基板和栅极电极上形成半导体层。在栅极电极和半导体层之间形成栅极绝缘层。在半导体层的第一和第二侧设置源极电极和漏极电极。源极电极和漏极电极包括金属元素。在源极电极和漏极电极上形成硅烷(SiH4)材料层。在源极电极和漏极电极上形成钝化层。钝化层的形成导致硅化工艺。硅化工艺包括在硅烷(SiH4)材料层的硅与源极电极和漏极电极的金属元素之间的反应，由此分别在源极电极和漏极电极的第一和第二侧表面上形成金属硅化物层。第一和第二侧表面限定重叠栅极电极的间隔。第一和第二侧表面与金属硅化物层接触。
附图说明
本发明的这些和其它特征将通过参考附图描述其示例性实施方式而变得更加明显，在图中：
图1是根据本发明示例性实施方式的薄膜晶体管阵列面板的俯视平面图；
图2是沿着图1的线II-II截取的截面图；
图3至图10是显示根据本发明示例性实施方式的薄膜晶体管阵列面板的制造方法的截面图；
图11是根据本发明示例性实施方式的液晶显示器的截面图；
图12是在根据本发明示例性实施方式的薄膜晶体管阵列面板中主布线层和钝化层之间的界面的图像；
图13是根据本发明示例性实施方式的薄膜晶体管阵列面板的沿着图1的线II-II截取的截面图；
图14至图20是显示根据本发明示例性实施方式的薄膜晶体管阵列面板的制造方法的截面图；以及
图21是在根据本发明示例性实施方式的薄膜晶体管阵列面板中主布线层和钝化层之间的界面的图像。
具体实施方式
以下将参考附图详细描述本发明的示例性实施方式。然而，本发明可以以不同的形式实施并且不应被理解为限于此处阐明的实施方式。在图中，为了清晰，可以夸大层和区域的厚度。还将理解，当一元件被称为“在”另一元件或基板“上”时，它可以直接在所述另一元件或基板上，或者也可以存在居间元件。还将理解，当一元件被称为“联接到”或“连接到”另一元件时，它可以直接联接到或连接到所述另一元件，或者也可以存在居间元件。相同的附图标记可以在整个说明书和附图中指代相同的元件。
图1是根据本发明示例性实施方式的薄膜晶体管阵列面板的俯视平面图。图2是沿着图1的线II-II截取的截面图。
参考图1和图2，薄膜晶体管阵列面板100包括形成在由透明玻璃或塑料形成的绝缘基板110上的栅极线121。
栅极线121传送栅极信号并且在横向方向上延伸。每条栅极线121包括从栅极线121伸出的栅极电极124。
栅极线121和栅极电极124可具有双层结构，该双层结构具有第一层121p和124p以及第二层121q和124q。第一层121p和124p以及第二层121q和124q的每个可以由铝基金属诸如铝(Al)和铝合金、银基金属诸如银(Ag)和银合金、铜基金属诸如铜(Cu)和铜合金、钼基金属诸如钼(Mo)和钼合金、铬(Cr)、钛(Ti)、钽(Ta)、锰(Mn)等形成。例如，第一层121p和124p可以包括钛，第二层121q和124q可以包括铜或铜合金。
备选地，第一层121p和124p以及第二层121q和124q可以由具有不同物理特性的膜的组合形成。栅极线121和栅极电极124包括两层，但是不限于此，并且可以形成为单层或三层。
由绝缘材料诸如硅氧化物或硅氮化物形成的栅极绝缘层140位于栅极线121上。栅极绝缘层140可以包括第一绝缘层140a和第二绝缘层140b。第一绝缘层140a可以由具有大约的厚度的硅氮化物(SiNx)形成，第二绝缘层140b可以由具有大约的厚度的硅氧化物(SiOx)形成。备选地，第一绝缘层140a可以由硅氮氧化物(SiON)形成，第二绝缘层140b可以由硅氧化物(SiOx)形成。栅极绝缘层140包括两层，但是可以包括单层。
半导体层151形成在栅极绝缘层140上。半导体层151可以由非晶硅、晶体硅或氧化物半导体形成。半导体层151主要在竖直方向上延伸并且包括朝向栅极电极124突出的突出部154。
当半导体层151由氧化物半导体形成时，半导体层151包含锌(Zn)、铟(In)、锡(Sn)、镓(Ga)和铪(Hf)中的至少一种。例如，半导体层151可以包含铟镓锌氧化物。
数据线171、连接到数据线171的源极电极173以及漏极电极175形成在半导体层151和栅极绝缘层140上。
数据线171传送数据信号并且主要在竖直方向上延伸以交叉栅极线121。源极电极173可以从数据线171延伸。源极电极173可以重叠栅极电极124。源极电极173可以基本上是U形。
漏极电极175与数据线171分离并且从源极电极173的“U”形的中心向上延伸。
数据线171、源极电极173和漏极电极175具有阻挡层171p、173p和175p以及主布线层171q、173q和175q的双膜结构。阻挡层171p、173p和175p由金属氧化物形成，主布线层171q、173q和175q由铜或铜合金形成。
例如，阻挡层171p、173p和175p可以由铟锌氧化物、镓锌氧化物和铝锌氧化物之一形成。
阻挡层171p、173p和175p用于防止诸如铜等的材料扩散到半导体层151。
金属硅化物层177位于主布线层171q、173q和175q上。金属硅化物层177包括铜、硅和氧，例如，可以包括由CuSixOy表示的化合物。金属硅化物层177，其覆盖源极电极173和漏极电极175，与源极电极173和漏极电极175的表面接触。例如，金属硅化物层177覆盖源极电极173和漏极电极175的暴露的侧表面A和B以及源极电极173和漏极电极175的暴露的上表面。金属硅化物层177不与栅极绝缘层140接触。
在下文中，将描述源极电极173和漏极电极175的靠近半导体层151的沟道区的暴露的侧表面A。
参考图2，半导体层151的突出部154包括没有被数据线171、源极电极173和漏极电极175覆盖的部分。例如，突出部154的该部分在源极电极173和漏极电极175之间暴露。数据线171、源极电极173和漏极电极175层叠在半导体层151上。半导体层151中的突出部154的该部分在源极电极173和漏极电极175之间暴露。半导体层151的边缘与数据线171和漏极电极175的外边缘竖直对准。源极电极173和漏极电极175的内边缘限定突出部154的暴露部分。数据线171、源极电极173和漏极电极175的边缘可以竖直地倾斜。
一个栅极电极124、一个源极电极173和一个漏极电极175与氧化物半导体层151的突出部154一起形成一个薄膜晶体管(TFT)，该薄膜晶体管的沟道形成在源极电极173和漏极电极175之间的突出部154中。
源极电极173和漏极电极175的邻近沟道区的侧表面被暴露，源极电极173和漏极电极175的暴露的侧表面A被金属硅化物层177覆盖。如果源极电极173和漏极电极175的侧表面A被暴露而没有金属硅化物层177，如果执行形成包括硅氧化物的钝化层的后续工艺或者执行向半导体层151的突出部154提供沟道特性的热处理，则主布线层171q、173q和175q中包括的材料诸如铜形成多孔氧化物，从而可能降低薄膜晶体管特性。因此，金属硅化物层可以防止诸如铜等的材料在执行诸如形成钝化层的后续工艺期间以及执行热处理期间被氧化。
金属硅化物层177可以使用包括形成硅烷材料层以及利用硅烷材料层执行硅化工艺的两步骤工艺来形成。随后将参考图8-10进行详细的描述。
钝化层180形成在金属硅化物层177上。钝化层180由无机绝缘体诸如硅氮化物或硅氧化物、有机绝缘体或低介电绝缘体形成。
钝化层180可以包括下钝化层180a和上钝化层180b。下钝化层180a可以由硅氧化物形成，上钝化层180b可以由硅氮化物形成。因为半导体层151包括氧化物半导体，所以邻近半导体层151的下钝化层180a由硅氧化物形成。在下钝化层180a由硅氮化物形成时，半导体层151不用作薄膜晶体管的沟道区。
钝化层180在源极电极173和漏极电极175之间可以与突出部154的没有被源极电极173和漏极电极175覆盖的暴露部分接触。
暴露漏极电极175的一个端部的接触孔185形成在钝化层180上。
像素电极191形成在钝化层180上。像素电极191经由接触孔185与漏极电极175物理地连接和电连接，并且被施加来自漏极电极175的数据电压。
像素电极191可以由透明导体诸如ITO(铟锡氧化物)或IZO(铟锌氧化物)形成。
图3至图10是示出用于制造根据本发明示例性实施方式的薄膜晶体管阵列面板的方法的截面图。图3至图10顺序示出沿着图1的线II-II截取的截面图。
参考图3，钼基金属诸如钼(Mo)和钼合金、铬基金属诸如铬(Cr)和铬合金、钛基金属诸如钛(Ti)和钛合金、钽基金属诸如钽(Ta)和钽合金、以及锰基金属诸如锰(Mn)和锰合金中的至少一种沉积在由透明玻璃或塑料形成的绝缘基板110上，从铝基金属诸如铝和铝合金、银基金属诸如银(Ag)和银合金、铜基金属诸如铜(Cu)和铜合金中选出的其中之一沉积在其上以形成两层并将其图案化，由此形成包括栅极电极124的栅极线121。例如，第一层121p和124p可以包含钛，第二层121q和124q可以包含铜或铜合金。
例如，在形成两层之后，光致抗蚀剂(未示出)被沉积并且被图案化，其后，第一层121p和124p以及第二层121q和124q通过利用图案化的光致抗蚀剂(未示出)作为掩模而被一起蚀刻。在此情形下，作为蚀刻剂，可采用能够蚀刻第一层121p和124p以及第二层121q和124q二者的一种。
参考图4，栅极绝缘层140、氧化物层150、金属氧化物层170p和金属层170q沉积在栅极线121和栅极电极124上。在栅极绝缘层140的形成期间，可以沉积包含硅氮化物的第一绝缘层140a，然后可以沉积包含硅氧化物的第二绝缘层140b。
氧化物层150可以包含锌(Zn)、铟(In)、锡(Sn)、镓(Ga)和铪(Hf)中的至少一种，金属氧化物层170p可以包含铟锌氧化物、镓锌氧化物和铝锌氧化物中的一种，金属层170q可以包含铜或铜合金。
光致抗蚀剂被形成并且被图案化以在金属层170q上形成第一光致抗蚀剂图案50。第一光致抗蚀剂图案50具有厚的第一区50a和相对薄的第二区50b。第一光致抗蚀剂图案50的厚度差异可以通过用掩模控制照射的光的量或者通过使用回流(reflow)方法而形成。在控制光的量时，狭缝图案、栅格图案或半透明层可以形成在掩模上。薄的第二区50b相应于将形成薄膜晶体管的沟道区的位置。
参考图5，金属氧化物层170p和金属层170q通过利用可以蚀刻金属氧化物层170p和金属层170q二者的蚀刻剂，通过利用第一光致抗蚀剂图案50作为掩模而被蚀刻。此处使用的蚀刻剂可以与在蚀刻栅极线121的第一层121p和124p以及第二层121q和124q时使用的蚀刻剂相同。
如果金属氧化物层170p和金属层170q被蚀刻，则金属氧化物层170p和金属层170q的被第一光致抗蚀剂图案50覆盖的侧表面也被蚀刻剂蚀刻，结果，第一金属层170p和第二金属层170q的边界线位于形成第一光致抗蚀剂图案50的区域A1、B1和C1内侧。
在此情形下，蚀刻金属氧化物层170p和金属层170q的蚀刻剂不蚀刻栅极绝缘层140和氧化层150。
另外，氧化层150通过利用第一光致抗蚀剂图案50作为掩模而被蚀刻。
参考图6，图5中的薄的第二区50b通过回蚀工艺被去除。在此情形下，第一区50a也被蚀刻，因而宽度和高度减小而变成图6的第二光致抗蚀剂图案51。第二光致抗蚀剂图案51形成在比图5中形成第一光致抗蚀剂图案50的区域B1和C1小的区域B2和C2中。
参考图7，金属氧化物层170p和金属层170q通过利用第二光致抗蚀剂图案51作为掩模被蚀刻剂蚀刻。
在此情形下，金属氧化物层170p和金属层170q被图案化以形成具有两层结构的数据线171p和171q、源极电极173p和173q以及漏极电极175p和175q。此外，氧化物半导体层151包括突出部154。突出部154可以用作薄膜晶体管的沟道区。
利用具有不同厚度的光致抗蚀剂图案，形成半导体层151和突出部154以及数据线171、源极电极173和漏极电极175的阻挡层171p、173p和175p以及主布线层171q、173q和175q。因为半导体层151和突出部154、数据线171、源极电极173和漏极电极175利用光致抗蚀剂图案作为蚀刻掩模而形成，所以它们的边缘竖直对准。
接着，参考图8，在光致抗蚀剂图案通过灰化工艺被去除之后，源极电极173和漏极电极175受到硅烷(SiH4)处理以形成硅烷材料层176。硅烷(SiH4)处理可以通过化学气相沉积(CVD)工艺来执行。
参考图9，硅烷材料层176沿着源极电极173和漏极电极175的用硅烷(SiH4)处理的表面形成。此时，源极电极173和漏极电极175的接近位于源极电极173和漏极电极175之间的沟道区的每个侧表面被暴露，硅烷材料层176形成在源极电极和漏极电极的暴露的侧表面上。例如，源极电极和漏极电极的暴露的侧表面被硅烷材料层176覆盖。
硅烷材料层176形成为覆盖沟道区和栅极绝缘层140以及源极电极173和漏极电极175的表面。
参考图10，钝化层180形成在硅烷材料层176上。在形成钝化层180期间，包含硅氮化物的下钝化层180a可以形成在硅烷材料层176上，包含硅氮化物的上钝化层180b可以形成在下钝化层180a上。包括硅氧化物(SiOx)的下钝化层180a可以通过例如SiH4和NO2的反应形成。在下钝化层180a的工艺中，硅烷材料层176可以与主布线层171q、173q和175q的铜或铜合金反应，由此形成金属硅化物层177。这里，硅烷材料层176可以在硅烷材料层176与由铜或铜合金形成的主布线层171q、173q和175q接触的位置处，被选择性地转变成金属硅化物层177。
通过图案化钝化层180形成暴露漏极电极175的一部分的接触孔185，像素电极191形成在钝化层180上以形成图2的薄膜晶体管阵列面板。在此情形下，像素电极191形成为经由接触孔185与漏极电极175物理地连接和电连接。
图11是示出根据本发明示例性实施方式的薄膜晶体管阵列面板的截面图。
参考图11，第二基板210面对绝缘基板110。第二基板210可以是由透明玻璃或塑料形成的绝缘基板。光阻挡构件220形成在第二基板210上。光阻挡构件220可以由黑矩阵形成并且用于防止光泄漏。
滤色器230也形成在第二基板210和光阻挡构件220上。滤色器230设置在由光阻挡构件220围绕的区域中，并且可以沿着一列像素电极191延长。每个滤色器230可以表现三原色诸如红色、绿色和蓝色中的一种。然而，所表现的颜色不限于红色、绿色和蓝色的三原色，每个滤色器230可以表现青色、品红色、黄色或基于白色的颜色中的一种。
光阻挡构件220和滤色器230形成在如上所述的相对的阵列面板200上，然而光阻挡构件220和滤色器230的至少之一可以形成在薄膜晶体管阵列面板100上。
外涂层250形成在滤色器230和光阻挡构件220上。外涂层250可以由绝缘材料形成。外涂层250可以密封滤色器230，并且还可以提供平坦的表面。备选地，外涂层250可以被省略。
公共电极270形成在外涂层250上。
施加有数据电压的像素电极191与施加有公共电压的公共电极270一起产生电场，以确定在两个电极之间的液晶层3的液晶分子31的方向。像素电极191和公共电极270组成电容器，从而即使在薄膜晶体管被截止之后，仍保持所施加的电压。
像素电极191与存储电极线(未示出)重叠以组成存储电容器，结果，可以增加液晶电容器的电压存储能力。
薄膜晶体管阵列面板100的描述可以适用于参考图2描述的示例性实施方式的内容。
根据示例性实施方式的薄膜晶体管阵列面板不限于液晶显示器，而是可以被应用于其它显示系统诸如有机发光显示装置。
图12是在根据本发明示例性实施方式的薄膜晶体管阵列面板中主布线层和钝化层之间的界面的图像。
图12是根据本发明示例性实施方式的薄膜晶体管阵列面板的电子显微镜图像。参考图12，金属硅化物层177被均匀地形成在主布线层173q和下钝化层180a之间的界面处。此外，没有形成污染源诸如铜氧化物。
图13是根据本发明示例性实施方式的薄膜晶体管阵列面板的沿着图1的线II-II截取的截面图。图13的截面结构基本上类似于图2的截面结构，除了源极电极173和漏极电极175之外。在下文中，将描述与图2的示例性实施方式的差异。
参考图13，数据线171、源极电极173和漏极电极175还包括形成在主布线层171q、173q和175q上的盖层171r、173r和175r。盖层171r、173r和175r包括金属氧化物。例如，盖层171r、173r和175r可以由铟锌氧化物、镓锌氧化物、铝锌氧化物和镓锌氧化物中的至少一种形成。例如，金属硅化物层177仅形成在主布线层171q、173q和175q的侧表面处。主布线层171q、173q和175q的侧表面没有被阻挡层171p、173p和175p以及盖层171r、173r和175r覆盖。例如，主布线层171q、173q和175q的侧表面被暴露在阻挡层171p、173p和175p与盖层171r、173r和175r之间。
除了所描述的差异之外，图2中描述的内容可以全部被应用于图13的本示例性实施方式。
图14至图20是显示根据本发明示例性实施方式的薄膜晶体管阵列面板的制造方法的截面图。图14至图20顺序显示沿着图1的线II-II截取的截面图。
参考图14至图19，根据本发明示例性实施方式的薄膜晶体管阵列面板的制造方法基本上类似于图4至图9中描述的示例性实施方式。参考图14，金属氧化物层170r可以另外地形成在金属层170q上。在后续工艺中，金属氧化物层170r与下面的金属层170q和金属氧化物层170p一起被图案化，如图17所示，由此盖层171r、173r和175r形成在主布线层171q、173q和175q上。
参考图18，在光致抗蚀剂图案通过灰化工艺被去除之后，源极电极173和漏极电极175的表面受到硅烷(SiH4)处理以形成硅烷材料层176。硅烷(SiH4)处理可以通过化学气相沉积(CVD)方法来执行。
参考图19，硅烷材料层176沿着源极电极173和漏极电极175的用硅烷(SiH4)处理的表面形成。此时，在源极电极173和漏极电极175的接近位于源极电极173和漏极电极175之间的沟道区的每个侧表面当中，硅烷材料层176形成为覆盖阻挡层171p、173p和175p与盖层171r、173r和175r之间的主布线层171q、173q和175q的暴露的侧表面。硅烷材料层176形成为覆盖沟道区和栅极绝缘层140以及源极电极173和漏极电极175的表面。
参考图20，钝化层180形成在硅烷材料层176上。在形成钝化层180期间，包含硅氧化物的下钝化层180a可以形成在硅烷材料层176上，包含硅氮化物的上钝化层180b可以形成在下钝化层180a上。包括硅氧化物(SiOx)的下钝化层180a可以通过硅烷(SiH4)和二氧化氮(NO2)的反应而形成。在形成下钝化层180a期间，硅烷材料层176与主布线层171q、173q和175q彼此反应，由此形成金属硅化物层177。主布线层171q、173q和175q由铜或铜合金形成。在形成下钝化层180a期间，硅烷材料层176的硅可以在硅烷材料层176与源极电极173和漏极电极175之间的界面处与铜或铜合金反应。
暴露漏极电极175的一部分的接触孔185通过图案化钝化层180而形成，像素电极191形成在钝化层180上以形成图13的薄膜晶体管阵列面板。在此情形下，像素电极191形成为经由接触孔185与漏极电极175物理地连接和电连接。
图21是在根据本发明示例性实施方式的薄膜晶体管阵列面板形成之后的电子显微镜图像，参考图21，金属硅化物层177均匀地形成在主布线层173q与下钝化层180a之间的界面处。此外，没有形成污染源诸如铜氧化物。
虽然已经参考本发明的示例性实施方式显示和描述了本发明，但是对于本领域的普通技术人员而言明显的是，其中可以在形式和细节上进行各种改变而不脱离由权利要求所限定的本发明的精神和范围。

Claims (20)

1.一种薄膜晶体管阵列面板，包括：
基板；
栅极电极，设置在所述基板上；
半导体层，设置在所述栅极电极和所述基板上；
栅极绝缘层，设置在所述栅极电极和所述半导体层之间；
源极电极，设置在所述半导体层的第一侧，其中所述源极电极包括第一侧表面；
漏极电极，设置在所述半导体层的第二侧，其中所述漏极电极包括第二侧表面并且与所述源极电极间隔开，其中所述第一侧表面和所述第二侧表面限定重叠所述栅极电极的间隔；
金属硅化物层，设置在所述第一侧表面和所述第二侧表面上；以及
钝化层，设置在所述金属硅化物层、所述源极电极和所述漏极电极上。
2.根据权利要求1所述的薄膜晶体管阵列面板，其中
所述半导体层通过由所述源极电极的所述第一侧表面和所述漏极电极的所述第二侧表面限定的所述间隔而与所述钝化层接触。
3.根据权利要求2所述的薄膜晶体管阵列面板，还包括
连接到所述源极电极的数据线，其中所述数据线的顶表面低于所述源极电极的顶表面，其中所述源极电极包括阻挡层和设置在所述阻挡层上的主布线层，其中所述主布线层包括铜或铜合金，所述阻挡层包括金属氧化物。
4.根据权利要求3所述的薄膜晶体管阵列面板，其中
所述钝化层包括下钝化层和上钝化层，所述下钝化层包括硅氧化物，所述上钝化层包括硅氮化物。
5.根据权利要求3所述的薄膜晶体管阵列面板，其中
所述金属硅化物层包括铜。
6.根据权利要求5所述的薄膜晶体管阵列面板，其中
所述阻挡层包括铟锌氧化物(IZO)、镓锌氧化物(GZO)和铝锌氧化物(AZO)中的至少一种。
7.根据权利要求1所述的薄膜晶体管阵列面板，其中
所述金属硅化物层还设置在所述源极电极和所述漏极电极的上表面上，其中所述源极电极和所述漏极电极的所述上表面不与所述钝化层接触。
8.根据权利要求3所述的薄膜晶体管阵列面板，还包括
设置在所述主布线层的上表面上的盖层，所述盖层包括金属氧化物，其中所述钝化层设置在所述盖层上而不与所述主布线层的所述上表面接触。
9.根据权利要求1所述的薄膜晶体管阵列面板，其中
所述半导体层包括氧化物半导体。
10.根据权利要求3所述的薄膜晶体管阵列面板，其中
所述半导体层包括第三侧表面，所述数据线包括第四侧表面，其中所述第三侧表面和所述第四侧表面彼此竖直地对准，其中所述第三侧表面与所述钝化层接触，所述第四侧表面与所述金属硅化物层接触而不与所述钝化层接触。
11.一种制造薄膜晶体管阵列面板的方法，包括：
在基板上形成栅极电极；
在所述基板和所述栅极电极上形成半导体层；
在所述栅极电极和所述半导体层之间形成栅极绝缘层；
形成分别设置在所述半导体层的第一侧和第二侧的源极电极和漏极电极，其中所述源极电极和所述漏极电极包括金属元素；
在所述源极电极和所述漏极电极上形成硅烷(SiH4)材料层；以及
在所述源极电极和所述漏极电极上形成钝化层，
其中所述钝化层的形成导致硅化工艺，其中所述硅化工艺包括在所述硅烷(SiH4)材料层的硅与所述源极电极和所述漏极电极的所述金属元素之间的反应，由此分别在所述源极电极和所述漏极电极的第一侧表面和第二侧表面上形成金属硅化物层，其中所述第一侧表面和所述第二侧表面限定重叠所述栅极电极的间隔，其中所述第一侧表面和所述第二侧表面与所述金属硅化物层接触。
12.根据权利要求11所述的方法，其中
所述硅烷(SiH4)材料层的形成通过化学气相沉积工艺来执行。
13.根据权利要求12所述的方法，其中
所述钝化层通过SiH4和NO2的反应而形成。
14.根据权利要求13所述的方法，其中
所述钝化层通过由所述源极电极和所述漏极电极的所述第一侧表面和所述第二侧表面限定的所述间隔而与所述半导体层接触。
15.根据权利要求14所述的方法，其中
所述源极电极的形成包括在所述半导体层上形成阻挡层以及在所述阻挡层上形成主布线层，以及
所述主布线层包括铜或铜合金以及所述阻挡层包括金属氧化物。
16.根据权利要求15所述的方法，其中
所述钝化层的形成包括形成下钝化层和形成上钝化层，其中所述下钝化层的形成导致在所述主布线层与所述硅烷(SiH4)材料层之间的界面处发生所述硅化工艺，其中所述下钝化层包括硅氧化物，所述上钝化层包括硅氮化物。
17.根据权利要求16所述的方法，其中
所述金属硅化物层还设置在所述源极电极和所述漏极电极的上表面上，其中所述源极电极和所述漏极电极的所述上表面不与所述钝化层接触。
18.根据权利要求15所述的方法，还包括在所述主布线层的上表面上形成盖层，其中所述主布线层的所述上表面不与所述钝化层接触。
19.根据权利要求11所述的方法，其中
所述半导体层包括氧化物半导体。
20.根据权利要求11所述的方法，其中
所述半导体层的形成以及所述源极电极和所述漏极电极的形成通过使用掩模来执行。
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105518845A (zh) * 2015-09-15 2016-04-20 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制备方法、显示装置
CN106206609A (zh) * 2016-08-17 2016-12-07 深圳市华星光电技术有限公司 显示器件板及其制造方法
CN107546231A (zh) * 2016-06-23 2018-01-05 三星显示有限公司 薄膜晶体管阵列面板
TWI627744B (zh) * 2015-12-29 2018-06-21 Ｌｇ顯示器股份有限公司 有機發光顯示裝置及製造該有機發光顯示裝置的方法
CN108475700A (zh) * 2016-01-29 2018-08-31 株式会社半导体能源研究所 半导体装置以及包括该半导体装置的显示装置
CN109360827A (zh) * 2018-08-23 2019-02-19 京东方科技集团股份有限公司 显示基板及其制造方法、显示面板
CN110648965A (zh) * 2019-10-23 2020-01-03 成都中电熊猫显示科技有限公司 阵列基板的制造方法及阵列基板
WO2020052024A1 (zh) * 2018-09-11 2020-03-19 惠科股份有限公司 阵列基板及其制备方法和显示器件
CN111129104A (zh) * 2020-01-16 2020-05-08 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示面板制程方法
CN111179749A (zh) * 2018-11-09 2020-05-19 三星显示有限公司 显示面板
WO2021077674A1 (zh) * 2019-10-23 2021-04-29 成都中电熊猫显示科技有限公司 阵列基板的制作方法及阵列基板

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102166898B1 (ko) 2014-01-10 2020-10-19 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
US9576984B1 (en) * 2016-01-14 2017-02-21 Hon Hai Precision Industry Co., Ltd. Thin film transistor array panel and conducting structure
CN205645818U (zh) * 2016-05-18 2016-10-12 武汉华星光电技术有限公司 一种oled显示面板
US10916430B2 (en) 2016-07-25 2021-02-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN110223989A (zh) * 2019-05-28 2019-09-10 深圳市华星光电半导体显示技术有限公司 薄膜晶体管基板及其制作方法
US11037851B2 (en) * 2019-08-30 2021-06-15 Applied Materials, Inc. Nitrogen-rich silicon nitride films for thin film transistors
US11444025B2 (en) * 2020-06-18 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor and fabrication method thereof
US11819847B2 (en) 2020-07-20 2023-11-21 Applied Materials, Inc. Nanofluidic device with silicon nitride membrane

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297405A (ja) * 1994-04-22 1995-11-10 Mitsubishi Electric Corp 薄膜トランジスタ及びその製造方法
JPH09321045A (ja) * 1996-05-30 1997-12-12 Nec Corp 半導体装置およびその製造方法
CN1776513A (zh) * 2004-11-17 2006-05-24 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
US20100320467A1 (en) * 2007-11-14 2010-12-23 Panasonic Corporation Thin-film transistor, manufacturing method therefor, and electronic device using a thin-film transistor
CN102270644A (zh) * 2010-06-04 2011-12-07 三星电子株式会社 薄膜晶体管显示面板及其制造方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4030193B2 (ja) * 1998-07-16 2008-01-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6534826B2 (en) * 1999-04-30 2003-03-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP4955848B2 (ja) * 2000-02-28 2012-06-20 エルジー ディスプレイ カンパニー リミテッド 電子素子用基板製造方法
US7105868B2 (en) * 2002-06-24 2006-09-12 Cermet, Inc. High-electron mobility transistor with zinc oxide
KR100935670B1 (ko) * 2003-04-04 2010-01-07 삼성전자주식회사 액정표시장치, 박막 트랜지스터 표시판 및 그의 제조 방법
US7211825B2 (en) * 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
US7221039B2 (en) * 2004-06-24 2007-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Thin film transistor (TFT) device structure employing silicon rich silicon oxide passivation layer
RU2358354C2 (ru) * 2004-11-10 2009-06-10 Кэнон Кабусики Кайся Светоизлучающее устройство
US8003449B2 (en) * 2004-11-26 2011-08-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having a reverse staggered thin film transistor
US7790617B2 (en) 2005-11-12 2010-09-07 Chartered Semiconductor Manufacturing, Ltd. Formation of metal silicide layer over copper interconnect for reliability enhancement
EP1895545B1 (en) * 2006-08-31 2014-04-23 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
KR101335276B1 (ko) * 2006-09-20 2013-11-29 삼성디스플레이 주식회사 어레이 기판, 이를 갖는 표시패널 및 그 제조 방법
JP5305630B2 (ja) * 2006-12-05 2013-10-02 キヤノン株式会社 ボトムゲート型薄膜トランジスタの製造方法及び表示装置の製造方法
JP5197058B2 (ja) * 2007-04-09 2013-05-15 キヤノン株式会社 発光装置とその作製方法
KR101345376B1 (ko) * 2007-05-29 2013-12-24 삼성전자주식회사 ＺｎＯ 계 박막 트랜지스터 및 그 제조방법
US7682882B2 (en) * 2007-06-20 2010-03-23 Samsung Electronics Co., Ltd. Method of manufacturing ZnO-based thin film transistor
EP2065927B1 (en) * 2007-11-27 2013-10-02 Imec Integration and manufacturing method of Cu germanide and Cu silicide as Cu capping layer
JP5315701B2 (ja) 2008-01-18 2013-10-16 三菱マテリアル株式会社 薄膜トランジスター
US9391099B2 (en) * 2008-02-15 2016-07-12 Lg Display Co., Ltd. Array substrate and liquid crystal display module including TFT having improved mobility and method of fabricating the same
US7968880B2 (en) * 2008-03-01 2011-06-28 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and display device
JP5484853B2 (ja) 2008-10-10 2014-05-07 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR101557817B1 (ko) * 2008-12-15 2015-10-07 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
US8681307B2 (en) * 2008-12-19 2014-03-25 Sharp Kabushiki Kaisha Insulated gate transistor, active matrix substrate, liquid crystal display device, and method for producing the same
JP5575451B2 (ja) 2009-10-08 2014-08-20 三菱電機株式会社 薄膜トランジスタの製造方法
WO2011058913A1 (en) 2009-11-13 2011-05-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR101895561B1 (ko) 2009-11-13 2018-09-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
US8415731B2 (en) * 2010-01-20 2013-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor storage device with integrated capacitor and having transistor overlapping sections
KR20150010776A (ko) * 2010-02-05 2015-01-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 및 반도체 장치의 제조 방법
KR101838130B1 (ko) * 2010-02-12 2018-03-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작방법
CN102812547B (zh) * 2010-03-19 2015-09-09 株式会社半导体能源研究所 半导体装置
US8779433B2 (en) * 2010-06-04 2014-07-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8916866B2 (en) 2010-11-03 2014-12-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI471946B (zh) * 2010-11-17 2015-02-01 Innolux Corp 薄膜電晶體
CN103348464B (zh) * 2011-01-26 2016-01-13 株式会社半导体能源研究所 半导体装置及其制造方法
KR101844953B1 (ko) * 2011-03-02 2018-04-04 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
JP2012182385A (ja) 2011-03-02 2012-09-20 Japan Display East Co Ltd 表示装置及び表示装置の製造方法
KR20120138074A (ko) 2011-06-14 2012-12-24 삼성디스플레이 주식회사 박막 트랜지스터, 및 박막 트랜지스터 표시판과 이들을 제조하는 방법
KR20130007340A (ko) * 2011-07-01 2013-01-18 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
KR101305830B1 (ko) * 2011-11-16 2013-09-06 현대자동차주식회사 차량의 실내 환기방법
KR102008902B1 (ko) * 2012-03-05 2019-10-21 엘지디스플레이 주식회사 어레이 기판 및 이의 제조 방법
KR20130126240A (ko) * 2012-05-11 2013-11-20 삼성디스플레이 주식회사 박막 트랜지스터 표시판
KR102207028B1 (ko) * 2012-12-03 2021-01-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9577107B2 (en) * 2013-03-19 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and method for forming oxide semiconductor film
TWI742574B (zh) * 2013-05-16 2021-10-11 日商半導體能源研究所股份有限公司 半導體裝置
KR102169861B1 (ko) * 2013-11-07 2020-10-26 엘지디스플레이 주식회사 어레이기판 및 이의 제조방법
KR102166898B1 (ko) 2014-01-10 2020-10-19 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
JP6689062B2 (ja) * 2014-12-10 2020-04-28 株式会社半導体エネルギー研究所 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297405A (ja) * 1994-04-22 1995-11-10 Mitsubishi Electric Corp 薄膜トランジスタ及びその製造方法
JPH09321045A (ja) * 1996-05-30 1997-12-12 Nec Corp 半導体装置およびその製造方法
CN1776513A (zh) * 2004-11-17 2006-05-24 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
US20100320467A1 (en) * 2007-11-14 2010-12-23 Panasonic Corporation Thin-film transistor, manufacturing method therefor, and electronic device using a thin-film transistor
CN102270644A (zh) * 2010-06-04 2011-12-07 三星电子株式会社 薄膜晶体管显示面板及其制造方法

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105518845A (zh) * 2015-09-15 2016-04-20 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制备方法、显示装置
US9991398B2 (en) 2015-09-15 2018-06-05 Boe Technology Group Co., Ltd. Thin film transistor (TFT) array substrate and fabrication method thereof, and display device
US10084026B2 (en) 2015-12-29 2018-09-25 Lg Display Co., Ltd. Organic light emitting display device and method of fabricating the same
US10403696B2 (en) 2015-12-29 2019-09-03 Lg Display Co., Ltd. Organic light emitting display device and method of fabricating the same
TWI627744B (zh) * 2015-12-29 2018-06-21 Ｌｇ顯示器股份有限公司 有機發光顯示裝置及製造該有機發光顯示裝置的方法
US11830950B2 (en) 2016-01-29 2023-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
CN108475700A (zh) * 2016-01-29 2018-08-31 株式会社半导体能源研究所 半导体装置以及包括该半导体装置的显示装置
CN108475700B (zh) * 2016-01-29 2022-01-14 株式会社半导体能源研究所 半导体装置以及包括该半导体装置的显示装置
US10734529B2 (en) 2016-01-29 2020-08-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
US11107930B2 (en) 2016-01-29 2021-08-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
CN107546231A (zh) * 2016-06-23 2018-01-05 三星显示有限公司 薄膜晶体管阵列面板
CN107546231B (zh) * 2016-06-23 2023-08-04 三星显示有限公司 薄膜晶体管阵列面板
CN106206609B (zh) * 2016-08-17 2019-05-03 深圳市华星光电技术有限公司 显示器件板及其制造方法
CN106206609A (zh) * 2016-08-17 2016-12-07 深圳市华星光电技术有限公司 显示器件板及其制造方法
CN109360827A (zh) * 2018-08-23 2019-02-19 京东方科技集团股份有限公司 显示基板及其制造方法、显示面板
WO2020052024A1 (zh) * 2018-09-11 2020-03-19 惠科股份有限公司 阵列基板及其制备方法和显示器件
CN111179749A (zh) * 2018-11-09 2020-05-19 三星显示有限公司 显示面板
CN110648965A (zh) * 2019-10-23 2020-01-03 成都中电熊猫显示科技有限公司 阵列基板的制造方法及阵列基板
WO2021077674A1 (zh) * 2019-10-23 2021-04-29 成都中电熊猫显示科技有限公司 阵列基板的制作方法及阵列基板
CN111129104B (zh) * 2020-01-16 2023-04-07 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示面板制程方法
CN111129104A (zh) * 2020-01-16 2020-05-08 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示面板制程方法

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