CN104769716B - 形成光子结构的方法 - Google Patents

形成光子结构的方法 Download PDF

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CN104769716B
CN104769716B CN201380044708.0A CN201380044708A CN104769716B CN 104769716 B CN104769716 B CN 104769716B CN 201380044708 A CN201380044708 A CN 201380044708A CN 104769716 B CN104769716 B CN 104769716B
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古尔特杰·桑胡
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Abstract

所揭示的实施例涉及一种集成电路结构及其形成方法，其中在用于制造含有电子装置的CMOS半导体结构的后端上形成光子装置。使用用于掺杂剂活化的微波退火来形成与所述光子装置相关联的掺杂区域。

Description

形成光子结构的方法
政府依据由DARPA授予的第HR0011-11-9-0009号协议支持本发明。政府在本发明中具有一定权利。
技术领域
本发明的实施例大体上涉及在硅晶片上制造光子结构及电子装置，且具体来说，本发明的实施例针对在CMOS工艺流程的后端处形成光子结构的方法。
背景技术
近年来，硅光子学日益受关注，其主要针对微电子电路中的光学发射及光学互连。利用互补金属氧化物半导体(CMOS)工艺，光子装置(例如波导、调制器及检测器)通常由绝缘体上半导体(SOI)或块状硅晶片上的硅或多晶硅及锗材料形成。将光子装置集成到CMOS工艺流程中的一种常规方法发生在CMOS生产线的前端处。典型前端方法涉及：首先，在衬底上制造光子装置；接着，在单一CMOS晶片上制造电子装置(例如晶体管)，其中所述光子装置及所述电子装置具有不同硅材料厚度。
光子装置的前端集成存在以下问题：制造光子装置所需的额外处理步骤可能干扰常规CMOS工艺流程。例如，光子装置在绝缘体上硅(SOI)晶片上的前端集成需要衬底，所述衬底具有比可使用具有小于1微米厚的埋藏氧化物材料及小于200纳米厚的硅材料的衬底的标准CMOS电子SOI装置厚的埋藏氧化物材料(大于1微米)及硅材料(大于200纳米)。在常规CMOS生产线的前端中，制造光子装置所需的额外处理步骤增加含有CMOS电子装置及光子装置两者的集成电路的总复杂性及成本。另外，对于CMOS电子装置及光子装置的并排布局，光子装置占据可用于电子装置的宝贵衬底空间。期望得到在CMOS生产线的后端中制造光子装置的改进方法。
附图说明
图1展示根据所揭示实施例的制造于单一CMOS半导体结构中的光子装置及电子装置；
图2展示根据所揭示实施例的在单一CMOS半导体结构中形成光子装置及电子装置的方法；及
图3展示根据所揭示实施例的在单一CMOS半导体结构中形成光子装置及电子装置的方法。
具体实施方式
在以下详细描述中，参考形成本发明的一部分的附图，且附图中依说明方式展示可被实践的特定实施例。应理解，相同参考数字表示全部图式中的相同元件。足够详细地描述这些实施例以使所属领域的技术人员能够制造及使用所述实施例，且应理解，可对所揭示的所述特定实施例(下文仅详细讨论其中一些)做出结构、材料、电性及程序变化。
术语“晶片”及“衬底”应被理解为可互换的且包含硅、绝缘体上硅(SOI)或蓝宝石上硅(SOS)、掺杂及未掺杂半导体、由底部半导体基座支撑的硅的外延生长材料及其它半导体结构。此外，当参考以下描述中的“晶片”及“衬底”时，先前工艺步骤可能已用于在底部半导体结构或基座中或底部半导体结构或基座上形成区域、结或材料层。另外，半导体无需基于硅，而是可基于硅锗、锗、砷化镓或其它已知半导体材料。
光子装置包含光子波导、调制器、解调器及光检测器，以及其它装置。通常需要掺杂剂活化来实现有源光子装置(例如光检测器、调制器)功能且产生欧姆电接触区域。在形成有源光子装置及欧姆接触件时，可通过将原子掺杂剂植入到半导体材料中且接着加热所述掺杂剂以使其活化而形成掺杂区域。以高温(例如1000摄氏度)加热所述掺杂剂需要：所述掺杂剂活化步骤发生在金属化之前，这是因为金属化材料会因此高温而受损坏。为此，在完成CMOS电路之前及在形成将光子装置与电子装置互连的金属化材料之前形成光子装置。在CMOS电路的金属化发生之后在CMOS工艺流程的后端处产生有源光子装置的一个挑战为：使用低温(即，低于约500摄氏度)来防止CMOS电路及金属化材料受损坏。
本文描述在常规CMOS工艺流程中集成光子装置的方法。所揭示的实施例涉及在CMOS工艺流程的后端处于单一CMOS半导体结构上形成光子装置及电子装置的方法。使用低沉积温度的多晶硅、锗及硅锗技术(例如(例如)物理气相沉积(PVD)、化学气相沉积(CVD)、等离子增强CVD(PECVD)、旋涂玻璃(SOG)沉积及原子层沉积(ALD))来形成光子装置。所揭示的实施例还利用在约200摄氏度到约500摄氏度、优选地约300摄氏度到约400摄氏度之间的温度下的电磁(例如微波)退火达至少五(5)分钟到高达两(2)小时以使有源光子装置及欧姆接触件掺杂剂活化及退火。尽管能够被吸收到被退火区域中的任何适当能量是适当的，但为方便起见，下文将仅讨论微波能。基于微波的活化技术可有效地活化所要掺杂剂(例如含磷、锑、镓、硼或砷掺杂原子)，而不损及前端CMOS电路或金属化材料以借此实现在CMOS工艺流程的后端处的光子装置的完全集成。低温微波退火还导致更少掺杂剂迁移出(及迁移入)衬底中的掺杂区域且导致掺杂区域内的掺杂剂浓度更均匀。
在常规CMOS工艺中的光子装置的前端集成中，光子装置通常由SOI晶片上的硅或多晶硅、锗及硅锗材料形成。后端集成的另一优点在于：光子装置可由额外材料形成，如果使用前端工艺，那么所述额外材料会受用于形成电子装置的处理影响。例如，后端处理可使用氮化硅来形成具有比多晶硅更好的光子传播的光子装置。例如，不在前端处使用SOI衬底上的硅或多晶硅来制造波导核心，而是可在后端工艺中由SOI衬底上的氮化硅形成波导核心。
参考图式，其中相同参考数字标示相同元件，图1展示使用后端处理来制造以在相同支撑衬底上形成CMOS集成结构103上的光子集成结构101的半导体结构200的一个实施例的部分横截面图。作为一实例，光子集成结构101包含光检测器250A及调制器250B。作为一实例，CMOS集成结构103包含制造为晶体管的电子装置210。可使用下文结合图2及3所描述的方法来制造半导体结构200。
CMOS集成结构103包括：硅衬底201；埋藏氧化物(BOX)202，其由(例如)二氧化硅形成；硅制造材料203；栅极氧化物材料219；及交替金属及绝缘材料，其形成包含绝缘(例如SiO2或BPSG)材料205、金属1材料214、绝缘(例如SiO2或BPSG)材料206、金属2材料215、最后金属材料216及钝化材料218(例如二氧化硅)的层间电介质(ILD)金属化结构。通过通孔导体217将金属1材料214连接到电子装置210的下方电路。
使用所属领域的技术人员所知的常规CMOS工艺来形成电子装置210。电子装置210包括：掺杂阱204、漏极植入区域211A及源极植入区域211B、栅极氧化物材料219上的栅极212及栅极侧壁间隔件213。栅极212可由多晶硅形成。绝缘材料205覆盖电子装置210及硅制造材料203，硅制造材料203由埋藏氧化物(BOX)202及硅衬底201支撑。
在此实施例中，光子集成结构101形成于CMOS集成结构103上，且包括形成于钝化层218上的半导体材料251、氧化物材料252、其中形成光检测器250A及调制器250B的硅制造材料253。交替金属及绝缘材料形成包含绝缘(例如SiO2或BPSG)材料255、金属1材料264、绝缘(例如SiO2或BPSG)材料256、金属2材料265、最后金属材料266及钝化材料267的ILD金属化结构。
光检测器250A可包括形成于硅波导核心253a上的掺杂或未掺杂锗(Ge)或硅锗(SiGe)区域262。波导核心253a由包覆材料包围，所述包覆材料由氧化物材料252及隔离区域254(其可由二氧化硅(SiO2)形成)形成。绝缘材料255还用作波导核心253a的包覆材料的部分。调制器250B可形成为掺杂或未掺杂硅波导核心253b，其具有可由导体257连接以调制波导核心253b内的光的额外掺杂区域261A及261B。光子结构101还可含有欧姆接触区域263A、263B、263C及263D以产生与导体257的欧姆接触。所述欧姆接触区域可为(例如)高掺杂接触区域或低温形成硅化物(例如Ni硅化物)。例如，光检测器250A可含有欧姆接触区域263A及263B，且调制器250B可含有欧姆接触区域263C及263D。欧姆接触区域263C及263D可含有比掺杂区域261A及261B的掺杂剂数量高的掺杂剂数量。锗(Ge)或硅锗(SiGe)区域262可用作为光检测器装置250A中的光子检测器。氧化物材料252及额外绝缘材料255及隔离区域254材料可用作为包围硅波导核心253a及253b的包覆材料。可为二氧化硅或BPSG的绝缘材料255覆盖光子装置250及硅制造材料253。光子装置250可使用比其上形成CMOS电子装置210的埋藏氧化物(BOX)材料202(小于1微米)及硅材料203(小于200纳米)厚的氧化物材料252(大于1微米)及硅制造材料253(大于200纳米)。
光子结构101中的交替金属及绝缘材料形成包含绝缘(例如SiO2或BPSG)材料255、256、金属1材料264、金属2材料265、最后金属材料266及钝化材料267的ILD金属化结构。绝缘材料255、256提供光检测器250A及调制器250B的电及光学隔离。通过导体257将金属1材料264连接到下方光子装置。作为结构101与103之间的电连接的实例，接触件207将集成光子结构101的金属1材料264连接到集成CMOS结构103的最后金属材料216。应了解，半导体结构200可由任何数目个电子装置及光子装置制造及由结构101与103之间的任何数目个接触件207制造以在半导体结构200内形成所要电子及光子布置。
图1仅表示包含波导253a、253b及相关联光检测器250A及调制器250B的光子电路。然而，可使用所描绘制造技术来将任何光子装置集成于集成CMOS结构103上，所述技术使用微波活化能来使掺杂剂在约200摄氏度到约500摄氏度的温度范围内、优选地在约300摄氏度到约400摄氏度的范围内活化，这不影响下方集成CMOS电路103。
图2展示根据所揭示实施例的使用CMOS工艺流程中的光子装置的后端集成来形成半导体结构200的方法。首先，在步骤300中，使用已知CMOS工艺技术来制造具有一或多个电子装置210的CMOS半导体结构103。CMOS结构包含钝化层218。在步骤310中，将光子结构101的相关联材料沉积于CMOS集成结构103上。这些材料包含半导体材料251(例如硅)、氧化物材料252及制造半导体材料253。将半导体材料251沉积于钝化保护材料218上，将用于形成光子装置250的具有适当厚度(例如大于1微米)的氧化物材料252沉积于半导体材料251上，及将用于光子装置250的具有适当厚度(例如大于200纳米)的硅制造材料253沉积于氧化物材料252上。用低温沉积技术(例如物理气相沉积(PVD)、化学气相沉积(CVD)、等离子增强CVD(PECVD)、旋涂玻璃(SOG)沉积及原子层沉积(ALD))来沉积材料251、252及253。在步骤320中，使用(例如)光刻、蚀刻、填充及化学机械抛光(CMP)来在硅制造材料253中界定及蚀刻隔离区域254(例如浅沟渠隔离区域)以在半导体制造材料253中的所要位置处产生隔离区域254。隔离区域254界定其中将形成光子装置(例如光检测器250A及调制器250B)的制造材料253中的区域。
在步骤330中，在调制器250B的两个隔离区域254之间的硅核心253b内形成掺杂区域261A、261B。在此步骤中，还可形成其它掺杂区域，例如，可掺杂硅波导核心253b且还可掺杂欧姆接触区域263C、263D。所述掺杂剂为通常用于形成集成电路的掺杂剂，例如硼、磷、锑、镓及砷。可形成例如原子掺杂剂浓度达每立方厘米约1x1016到约1x1021的所述掺杂区域。除形成掺杂区域之外，还可应用低温硅化物材料(例如Ni)以形成欧姆接触区域。在步骤340中，使用低温微波退火来退火及活化掺杂区域261A及261B以及任何其它掺杂区域及硅化物材料。在形成有源光子装置时，通过将掺杂剂原子植入到半导体材料(例如硅制造材料253)中且接着加热所述掺杂剂以使其活化而形成掺杂区域(例如261A及261B)。可通过在(例如)约1300瓦下以2.45GHz操作的空腔施料器微波系统内进行微波退火或(例如)通过在约1.5GHz到约8.5GHz之间的波长范围内操作的微波系统而实现有源光子装置的掺杂剂活化，但可使用任何适合频率及功率。使用低温来活化掺杂剂不会干扰下方CMOS结构103。所述微波系统在至少约5分钟到最多约两(2)小时内将所制造的CMOS结构103及部分完成的光子集成结构101加热到约200摄氏度到约500摄氏度之间、优选地约300摄氏度到约400摄氏度的温度。基于微波的活化技术可有效地活化所要掺杂剂(例如含磷、锑、镓、硼或砷掺杂原子)。可重复步骤330及340以界定及活化额外掺杂区域及欧姆接触区域。
在步骤350中，将锗(或硅锗)材料262沉积于用作波导核心的硅材料253a上。还将欧姆接触件263A、263B植入到或施加到材料262中。在步骤360中，使用后端绝缘体255、256来形成层间电介质结构(ILD)且沉积金属材料(例如金属1材料264、通孔1材料256、金属2材料265及最后金属材料266中的一或多者)以提供光子半导体结构的相关联材料之间及到光子装置250的电接触。此外，形成结构101与103之间的接触件207。绝缘体255与隔离区域254及氧化物材料252一起提供围绕波导核心253a的包覆材料。光检测器材料262检测波导核心253a内的光。在形成ILD的全部金属及绝缘体层之后，在步骤370中，将钝化材料267沉积于CMOS半导体结构200上。
在此实施例中，步骤340中的使用微波退火工艺的掺杂剂活化及退火发生在半导体及氧化物材料251、252、253步骤310、隔离区域254步骤320及掺杂区域步骤330之后，但在锗(或硅锗)沉积步骤360之前。在另一实施例中，如图3中所展示，使用低温微波退火的掺杂剂活化及退火步骤发生在锗(或硅锗)沉积步骤430之后及在掺杂或施加欧姆接触区域263A、263B、263C、263D之后。在图3中，步骤300到步骤320与图2中的相同编号步骤相同。在步骤430中，将锗(或硅锗)材料262沉积于硅制造材料253上，即，沉积于波导253a上。在步骤440中，除在调制器250B的硅核心253b内形成掺杂区域261A、261B以及欧姆接触区域263C及263D(如上文参考图2所描述)之外，还在锗材料262内形成欧姆接触区域263A及263B以产生欧姆电接触区域。欧姆接触区域263A及263B可为(例如)高掺杂区域或低温形成的硅化物(例如Ni硅化物)。还可掺杂硅核心253b。所述掺杂剂为通常用于形成集成电路的掺杂剂，例如硼、磷、锑、镓及砷。在步骤450中，使用上文结合图2的步骤340所描述的低温微波退火来活化硅核心253b、掺杂区域261A及261B、及欧姆接触区域263A、263B、263C及263D。图3中的步骤370及步骤380与图2中相同编号步骤相同。
尽管已详细描述所揭示实施例，但应容易地理解，本发明不受限于所述所揭示实施例。相反，所述所揭示实施例可经修改以并入前文未描述的任何数目个变动、改动、取代或等效布置。例如，尽管图1展示由示范性光检测器、波导及调制器及示范性晶体管制造的半导体结构200的部分横截面图，但应了解，所揭示实施例可经修改以由其它光子装置(例如(例如)调制器、解调器、光源)以及其它电子装置(例如晶体管、二极管及其它)制造半导体结构200。因此，本发明不受限于所揭示实施例，而是仅受限于所附权利要求书的范围。

Claims (21)

1.一种用于制造集成结构的方法，所述方法包括：
在衬底上制造含有电子装置的CMOS结构，其中所述电子装置通过使用第一半导体材料而形成；
在制造的含有所述电子装置的所述CMOS结构上制造第二半导体材料，以使得所述电子装置形成于所述第一半导体材料与所述第二半导体材料之间；
使用所述第二半导体材料制造光子装置，所述光子装置具有相关联掺杂区域；及
使用微波能来活化所述掺杂区域，使得所述掺杂区域被加热到在200摄氏度到500摄氏度的范围内的温度。
2.根据权利要求1所述的方法，其中所述掺杂区域被加热到在300摄氏度到400摄氏度的范围内的温度。
3.根据权利要求1所述的方法，其中所述第二半导体材料比所述CMOS结构的所述电子装置形成于其中的所述第一半导体材料厚。
4.根据权利要求3所述的方法，其进一步包括：形成邻近于所述第二半导体材料的埋藏氧化物材料。
5.根据权利要求4所述的方法，其中所述埋藏氧化物材料具有大于或等于1微米的厚度且所述第二半导体材料具有大于或等于200纳米的厚度。
6.根据权利要求1所述的方法，其中所述光子装置包括光检测器。
7.根据权利要求1所述的方法，其中所述光子装置是选自由波导、调制器、解调器及光检测器组成的群组的装置。
8.根据权利要求1所述的方法，其中用微波能加热掺杂剂达至少5分钟。
9.根据权利要求8所述的方法，其中用微波能加热所述掺杂剂高达2小时。
10.根据权利要求1所述的方法，其中使用具有大于或等于1.5GHz且小于或等于8.5GHz的频率的微波来进行所述活化步骤。
11.根据权利要求1所述的方法，其中使用具有2.45GHz的频率及1300瓦的功率的微波来进行所述活化步骤。
12.根据权利要求1所述的方法，其进一步包括：
在所述第二半导体材料中形成波导及与所述波导相关联的光检测器材料。
13.根据权利要求12所述的方法，其中所述活化发生在形成所述光检测器材料之前。
14.根据权利要求12所述的方法，其中所述活化发生在形成所述光检测器材料之后。
15.根据权利要求13所述的方法，其中所述光检测器材料包括锗及硅锗中的一者。
16.根据权利要求1所述的方法，其进一步包括：在金属化材料与所述光子装置之间形成电连接。
17.根据权利要求16所述的方法，其进一步包括：在相关联于所述CMOS结构中的电子装置的金属化材料与相关联于所述光子装置的金属化材料之间形成电连接。
18.一种半导体结构，其包括：
至少一个电子装置，其制造于第一半导体材料上；及
至少一个光子装置，其通过使用形成于所述至少一个电子装置上方的第二半导体材料来制造，所述至少一个光子装置具有相关联的微波活化掺杂剂植入物，其中所述至少一个电子装置在所述第一半导体材料与所述第二半导体材料之间。
19.根据权利要求18所述的半导体结构，其中所述半导体材料形成所述第一半导体衬底上所形成的绝缘体上硅衬底的部分。
20.根据权利要求18所述的半导体结构，其中所述光子装置选自由波导、调制器、解调器及光检测器组成的群组。
21.根据权利要求18所述的半导体结构，其进一步包括所述光子装置与所述至少一个电子装置之间的电连接。
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EP2891180A1 (en) 2015-07-08
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JP6154903B2 (ja) 2017-06-28
US20200348472A1 (en) 2020-11-05
CN104769716A (zh) 2015-07-08
US10761275B2 (en) 2020-09-01
WO2014035679A1 (en) 2014-03-06
US20180299626A1 (en) 2018-10-18
KR101742407B1 (ko) 2017-05-31
US11402590B2 (en) 2022-08-02
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US10094988B2 (en) 2018-10-09

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