TWI520313B - 形成光子結構之方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims description 36
- 239000000463 material Substances 0.000 claims description 130
- 239000004065 semiconductor Substances 0.000 claims description 63
- 239000002019 doping agent Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 15
- 239000012212 insulator Substances 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 41
- 229910052732 germanium Inorganic materials 0.000 description 37
- 229910052751 metal Inorganic materials 0.000 description 18
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
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- 239000011574 phosphorus Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
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- 230000003287 optical effect Effects 0.000 description 3
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 3
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- 230000000295 complement effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
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- 150000004772 tellurides Chemical class 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241000408659 Darpa Species 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
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- 238000004377 microelectronic Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
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- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12004—Combinations of two or more optical elements
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
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- G—PHYSICS
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- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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Description
政府依據由DARPA授予之協議第HR0011-11-9-0009號支援本發明。政府在本發明中具有一定權利。
本發明之實施例大體上係關於在矽晶圓上製造光子結構及電子裝置,且具體而言,本發明之實施例係針對在一CMOS程序流程之後端處形成光子結構之方法。
近年來,矽光子學日益受關注,其主要針對微電子電路中之光學傳輸及光學互連。利用一互補金屬氧化物半導體(CMOS)程序,光子裝置(諸如波導、調變器及偵測器)通常由一絕緣體上半導體(SOI)或塊狀矽晶圓上之矽或多晶矽及鍺材料形成。將光子裝置整合至該CMOS程序流程中之一習知方法發生在該CMOS生產線之前端處。典型前端方法涉及:首先,在一基板上製造光子裝置;接著,在一單一CMOS晶圓上製造電子裝置(例如電晶體),其中該等光子裝置及該等電子裝置具有不同矽材料厚度。
光子裝置之前端整合存在以下問題:製造光子裝置所需之額外處理步驟會干擾習知CMOS程序流程。例如,光子裝置於一絕緣體上矽(SOI)晶圓上之前端整合需要一基板,該基板具有比可使用具有一小於1微米厚之埋藏氧化物材料及一小於200奈米厚之矽材料之一基板之標準CMOS電子SOI裝置厚之一埋藏氧化物材料(大於1微米)及一矽
材料(大於200奈米)。在習知CMOS生產線之前端中,製造光子裝置所需之額外處理步驟增加總複雜性及含有CMOS電子裝置及光子裝置兩者之一積體電路之成本。另外,對於CMOS電子裝置及光子裝置之一並排佈局,光子裝置佔據可用於電子裝置之寶貴基板空間。期望得到在一CMOS生產線之後端中製造光子裝置之改良方法。
本申請案教示一種用於製造一積體結構之方法,該方法包括:在含有一電子裝置之一經製造之CMOS結構上形成一第一半導體材料;製造與該第一半導體材料相關聯之一光子裝置,該光子裝置具有相關聯摻雜區域;及用微波能活化該等摻雜區域,使得該等摻雜區域被加熱至約攝氏200度至約攝氏500度之範圍內之一溫度。本申請案進一步教示一種半導體結構,其包括:至少一電子裝置,其製造於一第一半導體結構上;及至少一光子裝置,其製造於形成於該至少一電子裝置上之一半導體材料中,該至少一光子裝置具有相關聯微波活化摻雜劑植入物。
101‧‧‧光子積體結構/積體光子結構
103‧‧‧互補金屬氧化物半導體(CMOS)積體結構/積體互補金屬氧化物半導體(CMOS)結構
200‧‧‧半導體結構
201‧‧‧矽基板
202‧‧‧埋藏氧化物(BOX)材料
203‧‧‧矽製造材料
204‧‧‧摻雜井
205‧‧‧絕緣材料
206‧‧‧絕緣材料
207‧‧‧接觸件
210‧‧‧電子裝置
211A‧‧‧汲極植入區域
211B‧‧‧源極植入區域
212‧‧‧閘極
213‧‧‧閘極側壁間隔件
214‧‧‧金屬1材料
215‧‧‧金屬2材料
216‧‧‧最後金屬材料
217‧‧‧通孔導體
218‧‧‧鈍化材料/鈍化層/鈍化保護材料
219‧‧‧閘極氧化物材料
250A‧‧‧光偵測器/光偵測器裝置
250B‧‧‧調變器
251‧‧‧半導體材料
252‧‧‧氧化物材料
253‧‧‧矽製造材料/製造半導體材料
253a‧‧‧矽波導核心/波導
253b‧‧‧矽波導核心/波導/矽核心
254‧‧‧隔離區域
255‧‧‧絕緣材料/後端絕緣體
256‧‧‧絕緣材料/後端絕緣體/通孔1材料
257‧‧‧導體
261A‧‧‧摻雜區域
261B‧‧‧摻雜區域
262‧‧‧鍺(Ge)或矽鍺(SiGe)區域/光偵測器材料
263A‧‧‧歐姆接觸區域/歐姆接觸件
263B‧‧‧歐姆接觸區域/歐姆接觸件
263C‧‧‧歐姆接觸區域
263D‧‧‧歐姆接觸區域
264‧‧‧金屬1材料
265‧‧‧金屬2材料
266‧‧‧最後金屬材料
267‧‧‧鈍化材料
300‧‧‧步驟
310‧‧‧步驟
320‧‧‧步驟
330‧‧‧步驟
340‧‧‧步驟
350‧‧‧步驟
360‧‧‧步驟
370‧‧‧步驟
430‧‧‧步驟
440‧‧‧步驟
450‧‧‧步驟
圖1展示根據一所揭示實施例之製造於一單一CMOS半導體結構中之光子裝置及電子裝置;圖2展示根據一所揭示實施例之在一單一CMOS半導體結構中形成光子裝置及電子裝置之一方法;及圖3展示根據一所揭示實施例之在一單一CMOS半導體結構中形成光子裝置及電子裝置之一方法。
在以下詳細描述中,參考構成本發明之一部分之附圖,且附圖中依繪示方式展示可被實踐之特定實施例。應瞭解,相同元件符號表示全部圖式中之相同元件。足夠詳細地描述此等實施例以使熟悉此項
技術者能夠製造及使用該等實施例,且應瞭解,可對所揭示之該等特定實施例(下文僅詳細討論其等之部分)作出結構、材料、電性及程序變化。
術語「晶圓」及「基板」應被理解為可互換的且包含矽、絕緣體上矽(SOI)或藍寶石上矽(SOS)、摻雜及未摻雜半導體、由一底部半導體基座支撐之矽之磊晶材料、及其他半導體結構。此外,當參考以下描述中之一「晶圓」及「基板」時,先前程序步驟可用於在底部半導體結構或基座中或底部半導體結構或基座上形成區域、接面或材料層。另外,半導體無需基於矽,而是可基於矽鍺、鍺、砷化鎵或其他已知半導體材料。
光子裝置包含光子波導、調變器、解調變器及光偵測器,以及其他裝置。通常需要摻雜劑活化來實現主動光子裝置(例如光偵測器、調變器)功能且產生歐姆電接觸區域。在形成主動光子裝置及歐姆接觸件時,可藉由將原子摻雜劑植入至一半導體材料中且接著加熱該摻雜劑以使其活化而形成摻雜區域。以一高溫(例如攝氏1000度)加熱該摻雜劑需要:該摻雜劑活化步驟發生在金屬化之前,此係因為金屬化材料會因此高溫而受損壞。為此,在完成CMOS電路之前及在形成將光子裝置與電子裝置互連之金屬化材料之前形成光子裝置。在CMOS程序流程之後端處產生主動光子裝置之一挑戰為:在CMOS電路之金屬化發生之後,使用低溫(即,低於約攝氏500度)來防止CMOS電路及金屬化材料受損壞。
本文描述在一習知CMOS程序流程中整合光子裝置之方法。所揭示之實施例係關於在CMOS程序流程之後端處於一單一CMOS半導體結構上形成光子裝置及電子裝置之方法。使用低沈積溫度之多晶矽、鍺及矽鍺技術(諸如(例如)物理氣相沈積(PVD)、化學氣相沈積(CVD)、電漿增強CVD(PECVD)、旋塗玻璃(SOG)沈積及原子層沈積
(ALD))來形成光子裝置。所揭示之實施例亦利用電磁(諸如微波),其在約攝氏200度至約攝氏500度,較佳地,約攝氏300度至約攝氏400度之間之溫度處退火達至少5分鐘至高達2小時以使主動光子裝置及歐姆接觸件摻雜劑活化及退火。儘管能夠被吸收至被退火區域中之任何適當能量係適當的,然為方便起見,下文將僅討論微波能。基於微波之活化技術可有效地活化所要摻雜劑(例如含磷、銻、鎵、硼或砷摻雜原子),且不損及前端CMOS電路或金屬化材料以藉此實現在CMOS程序流程之後端處之光子裝置之完全整合。低溫微波退火亦導致更少摻雜劑遷移出(及遷移入)基板中之摻雜區域且導致摻雜區域內之摻雜劑濃度更均勻。
在一CMOS程序中之光子裝置之前端整合中,光子裝置通常由一SOI晶圓上之矽或多晶矽、鍺及矽鍺材料形成。後端整合之另一優點在於:光子裝置可由額外材料形成,若使用一前端程序,則該等額外材料會受用於形成電子裝置之處理影響。例如,後端處理可使用氮化矽來形成具有比多晶矽更佳之光子傳播之光子裝置。例如,不在前端處使用SOI基板上之矽或多晶矽來製造一波導核心,而是可在一後端程序中由一SOI基板上之氮化矽形成波導核心。
參考圖式,其中相同元件符號標示相同元件,圖1展示使用後端處理來製造以在相同支撐基板上形成一CMOS積體結構103上之一光子積體結構101的一半導體結構200之一實施例之一部分橫截面圖。作為一實例,光子積體結構101包含一光偵測器250A及一調變器250B。作為一實例,CMOS積體結構103包含製造為一電晶體之一電子裝置210。可使用下文結合圖2及圖3所描述之方法來製造半導體結構200。
CMOS積體結構103包括:一矽基板201;一埋藏氧化物(BOX)202,其由(例如)二氧化矽形成;一矽製造材料203;一閘極氧化物材料219;及交替金屬及絕緣材料,其等形成包含絕緣(例如SiO2
或BPSG)材料205、金屬1材料214、絕緣(例如SiO2或BPSG)材料206、金屬2材料215、最後金屬材料216及一鈍化材料218(例如二氧化矽)之一層間介電(ILD)金屬化結構。藉由通孔導體217將金屬1材料214連接至電子裝置210之下方電路。
使用熟悉此項技術者所知之習知CMOS程序來形成電子裝置210。電子裝置210包括:一摻雜井204、汲極植入區域211A及源極植入區域211B、閘極氧化物材料219上之一閘極212、及閘極側壁間隔件213。閘極212可由多晶矽形成。絕緣材料205覆蓋電子裝置210及矽製造材料203,矽製造材料203由埋藏氧化物(BOX)202及矽基板201支撐。
在此實施例中,光子積體結構101形成於CMOS積體結構103上,且包括形成於鈍化層218上之一半導體材料251、一氧化物材料252、其中形成光偵測器250A及調變器250B之一矽製造材料253。交替金屬及絕緣材料形成包含絕緣(例如SiO2或BPSG)材料255、金屬1材料264、絕緣(例如SiO2或BPSG)材料256、金屬2材料265、最後金屬材料266及鈍化材料267之一ILD金屬化結構。
光偵測器250A可包括形成於一矽波導核心253a上之一摻雜或未摻雜鍺(Ge)或矽鍺(SiGe)區域262。波導核心253a由包覆材料包圍,該包覆材料由氧化物材料252及隔離區域254(其可由二氧化矽(SiO2)形成)形成。絕緣材料255亦用作波導核心253a之包覆材料之部分。調變器250B可形成為一摻雜或未摻雜矽波導核心253b,其具有可由導體257連接以調變波導核心253b內之光之額外摻雜區域261A及261B。光子結構101亦可含有歐姆接觸區域263A、263B、263C及263D以產生與導體257之歐姆接觸。該等歐姆接觸區域可為(例如)高摻雜接觸區域或低溫形成矽化物(諸如Ni矽化物)。例如,光偵測器250A可含有歐姆接觸區域263A及263B,且調變器250B可含有歐姆接觸區域263C及
263D。歐姆接觸區域263C及263D可含有比摻雜區域261A及261B之摻雜劑數量高之摻雜劑數量。鍺(Ge)或矽鍺(SiGe)區域262可用作為光偵測器裝置250A中之光子偵測器。氧化物材料252及額外絕緣材料255及隔離區域254可用作為包圍矽波導核心253a及253b之包覆材料。可為二氧化矽或BPSG之絕緣材料255覆蓋光子裝置250及矽製造材料253。光子裝置250可使用比其上形成CMOS電子裝置210之埋藏氧化物(BOX)材料202(小於1微米)及矽製造材料203(小於200奈米)厚之氧化物材料252(大於1微米)及矽製造材料253(大於200奈米)。
光子結構101中之交替金屬及絕緣材料形成包含絕緣(例如SiO2或BPSG)材料255、256、金屬1材料264、金屬2材料265、最後金屬材料266及鈍化材料267之一ILD金屬化結構。絕緣材料255、256提供光偵測器250A及調變器250B之電及光學隔離。藉由導體257將金屬1材料264連接至下方光子裝置。作為結構101與103之間之電連接之一實例,接觸件207將積體光子結構101之金屬1材料264連接至積體CMOS結構103之最後金屬材料216。應瞭解,半導體結構200可由任何數目個電子裝置及光子裝置製造及由結構101與103之間之任何數目個接觸件207製造以在半導體結構200內形成一所要電子及光子配置。
圖1僅表示包含波導253a、253b及相關聯光偵測器250A及調變器250B之一光子電路。然而,可使用所描繪製造技術來將任何光子裝置整合於一積體CMOS結構103上,該技術使用微波活化能來使摻雜劑在約攝氏200度至約攝氏500度之一溫度範圍內、較佳地在約攝氏300度至約攝氏400度之範圍內活化以不影響下方積體CMOS電路103。
圖2展示根據一所揭示實施例之使用一CMOS程序流程中之光子裝置之後端整合來形成半導體結構200之一方法。首先,在步驟300中,使用已知CMOS程序技術來製造具有一或多個電子裝置210之一
CMOS半導體結構103。CMOS結構包含鈍化層218。在步驟310中,將光子結構101之相關聯材料沈積於CMOS積體結構103上。此等材料包含半導體材料251(例如矽)、氧化物材料252及一製造半導體材料253。將半導體材料251沈積於鈍化保護材料218上,將用於形成光子裝置250之具有適當厚度(例如大於1微米)之氧化物材料252沈積於半導體材料251上,及將用於光子裝置250之具有適當厚度(例如大於200微米)之矽製造材料253沈積於氧化物材料252上。用低溫沈積技術(例如物理氣相沈積(PVD)、化學氣相沈積(CVD)、電漿增強CVD(PECVD)、旋塗玻璃(SOG)沈積及原子層沈積(ALD))來沈積材料251、252及253。在步驟320中,使用(例如)光微影、蝕刻、填充及化學機械拋光(CMP)來在矽製造材料253中界定及蝕刻隔離區域254(例如淺溝渠隔離區域)以在半導體製造材料253中之所要位置處產生隔離區域254。隔離區域254界定其中將形成光子裝置(例如光偵測器250A及調變器250B)之製造材料253中之區域。
在步驟330中,於調變器250B之兩個隔離區域254之間之矽核心253b內形成摻雜區域261A、261B。在此步驟中,亦可形成其他摻雜區域,例如,可摻雜矽波導核心253b且亦可摻雜歐姆接觸區域263C、263D。該等摻雜劑為通常用於形成積體電路之摻雜劑,例如硼、磷、銻、鎵及砷。可形成原子摻雜劑濃度達每立方厘米約1x1016至約1x1021之該等摻雜區域。除形成摻雜區域之外,亦可添加低溫矽化物材料(諸如Ni)以形成歐姆接觸區域。在步驟340中,使用低溫微波退火來退火及活化摻雜區域261A及261B以及任何其他摻雜區域及矽化物材料。在形成主動光子裝置時,藉由將摻雜劑原子植入至半導體材料(例如矽製造材料253)中且接著加熱該摻雜劑以使其活化而形成摻雜區域(例如261A及261B)。可藉由在(例如)約1300瓦處之2.45 GHz操作之一空腔施料器微波系統內進行微波退火或(例如)藉由在約
1.5 GHz至約8.5 GHz之間之波長範圍內操作之一微波系統而達成主動光子裝置之摻雜劑活化,但可使用任何適合頻率及功率。使用一低溫來活化摻雜劑不會干擾下方CMOS結構103。該微波系統在至少約5分鐘至最多約2小時內將所製造之CMOS結構103及部分完成之光子積體結構101加熱至約攝氏200度至約攝氏500度之間,較佳地約攝氏300度至約攝氏400度之溫度。基於微波之活化技術可有效地活化所要摻雜劑(例如含磷、銻、鎵、硼或砷摻雜原子)。可重複步驟330及340以界定及活化額外摻雜區域及歐姆接觸區域。
在步驟350中,將鍺(或矽鍺)材料262沈積於用作一波導核心之矽材料253a上。亦將歐姆接觸件263A、263B植入至或添加至材料262中。在步驟360中,使用後端絕緣體255、256來形成一層間介電結構(ILD)且沈積金屬材料(例如金屬1材料264、通孔1材料256、金屬2材料265及最後金屬材料266之一或多者)以提供光子半導體結構之相關聯材料之間及至光子裝置250之電接觸。此外,形成結構101與103之間之接觸件207。絕緣體255與隔離區域254及氧化物材料252一起提供圍繞波導核心253a之包覆材料。光偵測器材料262偵測波導核心253a內之光。在形成ILD之全部金屬及絕緣體層之後,在步驟370中,將鈍化材料267沈積於CMOS半導體結構200上。
在此實施例中,步驟340中之使用微波退火程序之摻雜劑活化及退火發生在半導體及氧化物材料251、252、253步驟310、隔離區域254步驟320及摻雜區域步驟330之後,但在鍺(或矽鍺)沈積步驟360之前。在另一實施例中,如圖3中所展示,使用低溫微波退火之摻雜劑活化及退火步驟發生在鍺(或矽鍺)沈積步驟430之後及在摻雜或添加歐姆接觸區域263A、263B、263C、263D之後。在圖3中,步驟300至步驟320與圖2中之相同編號步驟相同。在步驟430中,將鍺(或矽鍺)材料262沈積於矽製造材料253上,即,沈積於波導253a上。在步驟
440中,除在調變器250B之矽核心253b內形成摻雜區域261A、261B以及歐姆接觸區域263C及263D(如上文參考圖2所描述)之外,亦於鍺材料262內形成歐姆接觸區域263A及263B以產生歐姆電接觸區域。歐姆接觸區域263A及263B可為(例如)高摻雜區域或低溫形成之矽化物(諸如Ni矽化物)。亦可摻雜矽核心253b。該等摻雜劑為通常用於形成積體電路之摻雜劑,例如硼、磷、銻、鎵及砷。在步驟450中,使用上文結合圖2之步驟340所描述之低溫微波退火來活化矽核心253b、摻雜區域261A及261B、及歐姆接觸區域263A、263B、263C及263D。圖3中之步驟370及步驟380與圖2中相同編號步驟相同。
儘管已詳細描述所揭示實施例,然應易於瞭解,本發明不受限於該等所揭示實施例。相反,該等所揭示實施例可經修改以併入前文未描述之任何數目個變動、改動、取代或等效配置。例如,儘管圖1展示由一例示性光偵測器、波導及調變器及一例示性電晶體製造之一半導體結構200之一部分橫截面圖,然應瞭解,所揭示實施例可經修改以由其他光子裝置(諸如(例如)調變器、解調變器、光源)以及其他電子裝置(諸如電晶體、二極體及其他)製造半導體結構200。據此,本發明不受限於所揭示實施例,而是僅受限於隨附申請專利範圍之範疇。
300‧‧‧步驟
310‧‧‧步驟
320‧‧‧步驟
330‧‧‧步驟
340‧‧‧步驟
350‧‧‧步驟
360‧‧‧步驟
370‧‧‧步驟
Claims (22)
- 一種用於製造一積體結構之方法,該方法包括:在含有一電子裝置之一經製造之CMOS結構上形成一第一半導體材料,其中使用一第二半導體材料形成該電子裝置,且該電子裝置形成於該第一半導體材料與該第二半導體材料之間;使用該第一半導體材料製造一光子裝置,使得該第一半導體材料位於該CMOS結構與該光子裝置之間,該光子裝置具有相關聯摻雜區域:及使用微波能來活化該等摻雜區域,使得該等摻雜區域被加熱至在約攝氏200度至約攝氏500度之範圍內之一溫度。
- 如請求項1之方法,其中該等摻雜區域被加熱至在約攝氏300度至約攝氏400度之範圍內之一溫度。
- 如請求項1之方法,其中該第一半導體材料比該CMOS結構之該電子裝置形成於其中之該第二半導體材料厚。
- 如請求項3之方法,其進一步包括:形成鄰近於該第一半導體材料之一埋藏氧化物材料。
- 如請求項4之方法,其中該埋藏氧化物材料具有大於或等於1微米之一厚度及該第一半導體材料具有大於或等於200奈米之一厚度。
- 如請求項1之方法,其中該光子裝置包括一光偵測器。
- 如請求項1之方法,其中該光子裝置係選自由一波導、一調變器、一解調變器及一光偵測器組成之一群組之裝置。
- 如請求項1之方法,其中用微波能加熱摻雜劑達至少約5分鐘。
- 如請求項8之方法,其中用微波能加熱摻雜劑高達約2小時。
- 如請求項1之方法,其中使用具有大於或等於約1.5GHz且小於或等於約8.5GHz之一頻率之微波來進行該活化步驟。
- 如請求項1之方法,其中使用具有約2.45GHz之一頻率及約1300瓦之一功率之微波來進行該活化步驟。
- 如請求項1之方法,其進一步包括:使用該第一半導體材料形成一波導及與該波導相關聯之一光偵測器材料。
- 如請求項12之方法,其中該活化發生在形成該光偵測器材料之前。
- 如請求項12之方法,其中該活化發生在形成該光偵測器材料之後。
- 如請求項13之方法,其中該光偵測器材料包括鍺及矽鍺之一者。
- 如請求項1之方法,其進一步包括:在一金屬化材料與該光子裝置之間形成一電連接。
- 如請求項16之方法,其進一步包括:在相關聯於該CMOS結構中之一電子裝置之一金屬化材料與相關聯於該光子裝置之一金屬化材料之間形成一電連接。
- 一種半導體結構,其包括:至少一電子裝置,其製造於一第一半導體材料上;及至少一光子裝置,其使用形成於該至少一電子裝置上方之一第二半導體材料所製造,該至少一光子裝置具有相關聯之微波活化摻雜劑植入物,其中該至少一電子裝置位於該第一半導體材料與該第二半導體材料之間。
- 如請求項18之半導體結構,其中該半導體材料形成該第一半導體基板上所形成之絕緣體上矽基板之部分。
- 如請求項18之半導體結構,其中該光子裝置選自由一波導、一調變器、一解調變器及一光偵測器組成之一群組。
- 如請求項18之半導體結構,其進一步包括該光子裝置與該至少一電子裝置之間之一電連接。
- 如請求項1之方法,其中在該已製造之CMOS結構上形成該第一半導體材料後製造該光子裝置。
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JP2015535389A (ja) | 2015-12-10 |
US20220381976A1 (en) | 2022-12-01 |
EP2891180B1 (en) | 2019-03-13 |
JP6154903B2 (ja) | 2017-06-28 |
US20200348472A1 (en) | 2020-11-05 |
CN104769716A (zh) | 2015-07-08 |
US10761275B2 (en) | 2020-09-01 |
WO2014035679A1 (en) | 2014-03-06 |
US20180299626A1 (en) | 2018-10-18 |
KR101742407B1 (ko) | 2017-05-31 |
US11402590B2 (en) | 2022-08-02 |
TW201417247A (zh) | 2014-05-01 |
US10094988B2 (en) | 2018-10-09 |
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