CN104183601B - 具有氧化物薄膜晶体管的平板显示装置及其制造方法 - Google Patents

具有氧化物薄膜晶体管的平板显示装置及其制造方法 Download PDF

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CN104183601B
CN104183601B CN201310728289.4A CN201310728289A CN104183601B CN 104183601 B CN104183601 B CN 104183601B CN 201310728289 A CN201310728289 A CN 201310728289A CN 104183601 B CN104183601 B CN 104183601B
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郑棋永
金杞泰
韩昌勋
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LG Display Co Ltd
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Abstract

本发明提供了一种具有氧化物薄膜晶体管的平板显示装置及其制造方法。具有氧化物薄膜晶体管的平板显示装置包括：缓冲膜，其形成在基板上；氧化物半导体层，其具有第一长度的宽度并且形成在缓冲膜上；栅极绝缘膜，其具有第二长度的宽度并且形成在氧化物半导体层上；栅电极，其具有第三长度的宽度并且形成在栅极绝缘膜上；层间绝缘膜，其形成在设置有栅电极的基板的整个表面；源电极和漏电极，其形成在层间绝缘膜上并且连接到氧化物半导体层；钝化膜，其形成在设置有源电极和漏电极的基板的整个表面上；以及像素电极，其形成在钝化膜上并且连接到漏电极。第一长度大于第二长度并且第二长度大于第三长度。

Description

具有氧化物薄膜晶体管的平板显示装置及其制造方法
技术领域
本发明涉及一种平板显示装置，并且更具体地，涉及一种具有氧化物薄膜晶体管的平板显示装置及其制造方法，其适于确保元件的可靠性和结构稳定性。
背景技术
诸如液晶显示装置的平板显示装置使用布置在各像素中的诸如薄膜晶体管的有源元件来驱动显示元件。显示装置的这样的驱动模式被称为主动矩阵驱动模式。在主动矩阵驱动模式中，薄膜晶体管被布置在各像素中并且用于驱动各像素。
当前，具有由非晶硅膜和多晶硅膜中的一种形成的沟道层的薄膜晶体管得到了最广泛的使用。
非晶硅膜能够在低于350℃的温度薄薄地沉积。然而，非晶硅的迁移率低于0.5cm2/Vs。由此，非晶硅难以在超级尺寸的屏幕中实现高分辨率和高驱动速度。另一方面，多晶硅具有几十至几百cm2/Vs的高迁移率。
鉴于此，非晶硅薄膜晶体管用于驱动像素，并且多晶硅薄膜晶体管用于驱动和控制整个画面或图片。
图1是示出根据现有技术的具有多晶硅薄膜晶体管的平板显示装置及其制造方法的截面图。
参考图1，使用多晶硅薄膜晶体管的平板显示装置包括形成在基板11上的薄膜晶体管30和连接到薄膜晶体管30的像素电极21。
薄膜晶体管30包括形成在基板11的整个表面上的缓冲膜12、形成在缓冲膜12上的半导体层13和形成在缓冲膜12的整个表面上以覆盖半导体层13的栅极绝缘膜15。而且，薄膜晶体管30包括形成在栅极绝缘膜15上的栅电极16a、形成在设置有栅电极16a的栅极绝缘膜15的整个表面上的层间绝缘膜17和形成在层间绝缘膜17上并且分别连接到半导体层13的源极区域14a和漏极区域14b的源电极18a和漏电极18b。
平板显示装置进一步包括形成在设置有源电极18a和漏电极18b的层间绝缘膜17上的钝化膜19。像素电极21形成在钝化膜19上并且通过形成在钝化膜19中的接触孔20连接到漏电极18b。
而且，制造这样的平板显示装置的方法包括在基板11上顺序地形成缓冲膜12、半导体层13、栅极绝缘膜15和栅电极16a，将掺杂物注入到半导体层13中，并且在设置有栅电极16a的栅极绝缘膜15上顺序地形成层间绝缘膜17、源电极18a和漏电极18b、钝化膜19以及像素电极21。
由多晶硅形成的半导体层13能够通过对非晶硅层进行结晶化来获得。通过非晶硅的结晶化获得的多晶硅半导体层13能够具有比较满意的结晶度，但是必须在1000℃以上的高温进行处理。
半导体层13的掺杂过程包括使用栅电极16a作为掩模形成低密度区域，并且使用暴露半导体层13的对应于源极区域14a和漏极区域14b的部分的光刻胶图案作为另一掩模形成高密度区域。低密度区域（未示出）用于减少薄膜晶体管30的截止电流。高密度区域变为源极区域14a和漏极区域14b。
然而，使用暴露半导体层13的对应于源极区域14a和漏极区域14b的部分的光刻胶图案作为掩模形成高密度区域除了形成栅电极16a的掩模过程之外还要求额外的掩模过程。
本申请要求2013年5月28日提交的韩国专利申请No.10-2013-0060259的优先权，通过引用将其整体并入这里。
发明内容
因此，本发明的实施方式涉及一种平板显示装置及其制造方法，其基本上避免了由于现有技术的限制和缺点导致的问题中的一个或多个。
实施方式用于提供一种具有氧化物薄膜晶体管的平板显示装置，其适于确保有效沟道长度，实施方式还提供了制造这样的平板显示装置的方法。
而且，实施方式用于提供一种具有氧化物薄膜晶体管的平板显示装置的制造方法，其适于减少掩模过程的数目。
在随后的描述中将会部分地阐述本发明的额外的优点、目的和特征，并且部分优点、目的和特征对于已经研究过下面所述的本领域技术人员来说将是显而易见的，或者部分优点、目的和特征将通过本发明的实践来知晓。通过在给出的描述及其权利要求以及附图中特别地指出的结构可以实现并且获得本发明的目的和其它的优点。
根据用于解决现有技术的问题的本发明的一般性方面，一种平板显示装置包括：缓冲膜，其形成在基板上；氧化物半导体层，其具有第一长度的宽度并且形成在缓冲膜上；栅极绝缘膜，其具有第二长度的宽度并且形成在氧化物半导体层上；栅电极，其具有第三长度的宽度并且形成在栅极绝缘膜上；层间绝缘膜，其形成在基板的整个表面上并且位于栅电极上；源电极和漏电极，其形成在层间绝缘膜上并且连接到氧化物半导体层；钝化膜，其形成在基板的整个表面上并且位于源电极和漏电极上；以及像素电极，其形成在钝化膜上并且连接到漏电极。第一长度大于第二长度并且第二长度大于第三长度。
根据用于解决现有技术的问题的本实施方式的另一一般性方面的具有氧化物薄膜晶体管的平板显示装置的制造方法包括：在基板上形成缓冲膜；在缓冲膜上形成具有第一长度的宽度的氧化物半导体层；在氧化物半导体层上形成具有第二长度的宽度的栅极绝缘膜和具有第三长度的宽度的栅电极；通过使用栅极绝缘膜对氧化物半导体层进行金属化来形成源极区域和漏极区域；在基板的整个表面上以及在栅电极上形成层间绝缘膜；在层间绝缘膜上形成分别连接到源极区域和漏极区域的源电极和漏电极；在基板的整个表面上并且在源电极和漏电极上形成钝化膜；以及在钝化膜上形成连接到漏电极的像素电极，其中，第一长度大于第二长度并且第二长度大于第三长度。
其它系统、方法、特征和优点将对于审视了下面的附图和详细描述的本领域技术人员来说是显而易见的。想要的是，所有这样的额外的系统、方法、特征和优点包括在该描述内，包括在本公开的范围内，并且由所附权利要求保护。在该部分中的任何部分都不应被视为对这些权利要求的限制。下面结合实施方式讨论进一步的方面和优点。将理解的是，本公开的前述一般性描述和下面的详细描述是示例性的和说明性的并且意在提供所附权利要求记载的本公开的进一步的说明。
附图说明
附图被包括进来以提供本发明的进一步理解，并且被并入本申请且构成本申请的一部分，示出了本发明的实施方式，并且与说明书一起用于说明本发明的原理。在附图中：
图1是示出根据现有技术的具有多晶硅薄膜晶体管的平板显示装置及其制造方法的截面图；
图2是示出根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置的平面图；
图3是示出沿着图2中的线I-I’截取的平板显示装置的截面图；
图4A至图4E是逐步骤地示出根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置的制造方法的截面图；以及
图5是示出通过应用根据本公开的实施方式的具有薄膜晶体管的平板显示装置的制造方法获得的元件的增强的性质的数据图。
具体实施方式
现在将参考在附图中示出的其具有氧化物薄膜晶体管的平板显示装置及其制造方法（示例）的本发明的实施方式。下面介绍的实施方式用作示例以便于将其精神传达给本领域技术人员。因此，这些实施方式可以以不同形状来实施，因此不限于这里描述的这些实施方式。在附图中，为了说明的方便起见，能够夸大装置的尺寸、厚度等等。在可能的情况下，将在包括附图的本公开中使用相同的附图标记来标识相同或类似的部件。
图2是示出根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置的平面图。图3是示出沿着图2中的线I-I’截取的平板显示装置的截面图。
参考图2和图3，根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置包括其上形成顶栅极薄膜晶体管的薄膜晶体管阵列基板100。
详细地，像素区域P由在基板101上布置为矩阵形状的多条选通线116和多条数据线118限定。薄膜晶体管形成在选通线116与数据线118的交叉处。薄膜晶体管用于切换将要传输到各像素的信号。连接到薄膜晶体管的像素电极121形成在像素区域中。
薄膜晶体管包括：形成在基板101上的缓冲膜102；半导体层113、顺序地堆叠在缓冲膜102上的栅极绝缘膜115和栅电极116a；以及连接到半导体层113的源电极118a和漏电极118b。
半导体层113具有第一长度L1的宽度。而且，半导体层113由包含氧离子的化合物形成。由化合物形成的半导体薄膜能够在相对较低的温度形成，并且形成在诸如塑料板、塑料膜或其它的基板上。而且，化合物的半导体薄膜具有非晶硅的几十倍以上的电子迁移率。因此，化合物的半导体薄膜受到关注而作为适合于实现至少超高清的高分辨率和240Hz以上的高速操作。
作为形成半导体层113的化合物的示例，能够使用从下述材料组中选择的材料，所述材料组包括非晶铟镓锌氧化物（a-IGZO）、非晶铟锡锌氧化物（a-ITZO）、铟镓氧化物（IGO）等等。
半导体层113包括沟道区域113a和源极区域114a和漏极区域114b。源极区域114a和漏极区域114b通过对半导体层113进行金属化的处理而形成。
形成在半导体层113上的栅极绝缘膜115具有第二长度L2的宽度。第二长度L2小于对应于半导体层113的宽度的第一长度L1，并且大于作为栅电极116a的宽度的第三长度L3。因此，本公开允许仅使用具有第二长度L2的宽度的栅极绝缘膜115来在没有任何额外的掩模过程的情况下执行半导体层113的金属化。而且，半导体层113的沟道区域113a能够形成有足够的长度。
栅极绝缘膜115能够由选自硅氧化物（SiO2）、硅氮化物（SiNx）和硅氧氮化物（SiON）的材料组的材料形成。栅电极116a能够由选择由钼（Mo）、铝（Al）、铜（Cu）和钼钛（MoTi）合金组成的材料组的至少一种材料形成。
层间绝缘膜117形成在基板101的整个表面之上并且位于栅电极116a上。
源电极118a和漏电极118b形成在层间绝缘膜117上以分别连接到半导体层113的源电极114a和漏电极114b。同时，连接到源电极118a的数据线118能够形成在像素区域P中，并且连接到像素区域P内的数据线118的数据焊盘118c能够形成在非像素区域中。数据焊盘118c用于将信号从外部传输到数据线118。
接下来，钝化膜119形成在包括像素区域P的基板101的整个表面之上。而且，暴露漏电极118b的一部分的接触孔120形成在钝化膜119中。此外，像素电极121形成在钝化膜119上以通过接触孔120连接到漏电极118b。
图4A至图4E是逐步骤地示出根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置的制造方法的截面图。
参考图4A，根据本公开的实施方式的制造具有氧化物薄膜晶体管的平板显示装置的方法首先不仅允许缓冲膜102形成在基板101上而且允许具有第一长度L1的宽度的半导体层113形成在缓冲膜112上。
半导体层113能够由包含氧离子的化合物半导体形成。详细地，半导体层113能够由能够在相对较低的温度在柔性基板上形成为薄膜并且具有高迁移率的氧化物材料形成。
例如，选自包括非晶铟镓锌氧化物（a-IGZO）、非晶铟锡锌氧化物（a-ITZO）、铟镓氧化物（IGO）等等的材料组的一种材料能够用于形成半导体层。
半导体层113能够使用气相沉积方法和光刻方法中的一种来形成。例如，半导体层113能够通过使用气相沉积方法形成IGZO等等的薄膜并且将薄膜图案化为想要的形状来获得。膜形成处理用于形成由IGZO等等中的一种形成的氧化物半导体烧结。因此，优选的是，将气相沉积方法中包括的溅射方法和脉冲激光沉积方法中的一种应用于半导体层113的形成。更优选地，溅射方法应用于半导体层113的形成以便于批量生产平板显示装置。
能够通过在与半导体层113的形成区域相对的IGZO的薄膜上形成光刻胶图案并且使用诸如磷酸、硝酸和醋酸的混合溶液、盐酸、硝酸、稀硫酸或其它的酸溶液来蚀刻薄膜来执行图案化处理。特别地，包含磷酸、硝酸和醋酸的溶液能够在短时间内移除IGZO膜的暴露部分。
如图4B中所示，栅极绝缘材料层115’和栅电极材料层116’在基板101的整个表面上顺序地形成在缓冲膜102和半导体层113上。
之后，具有第二长度L2的宽度的光刻胶图案130形成在栅电极材料层116’上。光刻胶图案130位于栅电极材料层116’的与栅极绝缘膜115（其将在之后形成，如图4C中所示）相反的区域上。具有第二长度L2的光刻胶图案130的宽度几乎等于栅极绝缘膜115（其将在之后形成，如图4C中所示）的宽度。
参考图4C，通过使用光刻胶图案130作为掩模蚀刻栅电极材料层116’来形成具有第三长度L3的宽度的栅电极116a。使用湿法蚀刻方法来执行该蚀刻处理。
如果栅电极116a与源电极118a和漏电极118b之间的距离变得较短（如图4E中所示），则产生寄生电容，并且此外，元件（即，薄膜晶体管）的性能劣化。因此，对应于栅电极116a的宽度的第三长度L3被设置到防止形成寄生电容的程度。然而，栅电极116具有与具有几乎相同的性能的普通薄膜晶体管的宽度类似的宽度。
另一方面，对应于光刻胶图案130的宽度的第二长度L2大于用于形成具有几乎相同的性能的普通薄膜晶体管的栅电极的现有技术的光刻胶图案的宽度。因此，与使用现有技术的光刻胶图案的另一蚀刻处理相比，能够执行使用光刻胶图案130作为掩模的蚀刻处理更长时间。
接下来，通过使用具有第二长度L2的宽度的光刻胶图案130作为掩模来蚀刻栅极绝缘材料层115’来形成栅极绝缘膜115。这时，能够使用干法蚀刻方法来执行栅极绝缘材料层115’的蚀刻处理。之后，从栅电极116a移除光刻胶图案130。
所形成的栅极绝缘膜115具有大于栅电极116a的宽度的第二长度L2的宽度。源电极118a和漏电极118b没有在其间引起任何电容，这与栅电极116a不同。因此，即使栅极绝缘膜115的宽度变得更宽，元件（即，薄膜晶体管）的性能也没有变化。
如图4D中所示，使用栅极绝缘膜115作为掩模对于半导体层113执行金属化处理。根据此，能够在半导体层113中形成源极区域114a和漏极区域114b。
如上所述，能够在不考虑寄生电容的情况下设置栅极绝缘膜115的宽度。然而，如果栅极绝缘膜115具有与栅电极116a相同的宽度，则半导体层130的金属化的部分能够在执行金属化处理时在栅电极116a下面扩展。由于此，沟道区域113a的宽度能够变得窄于栅电极116a的宽度。该短沟道结构能够将电场集中到半导体层130的源极区域114a和漏极区域114b并且引起帽载流子效应。换言之，短沟道结构变为元件（即，薄膜晶体管）的故障因素。
鉴于此，本公开允许栅极绝缘膜115形成为比栅电极116a更宽的宽度。
同时，栅极绝缘膜115能够具有比半导体层113的宽度更宽的宽度。换言之，栅极绝缘膜115能够形成为覆盖半导体层113的整个表面。由于此，栅极绝缘膜不能够在半导体层113的金属处理中用作掩模。
因此，必须就在形成了半导体层113之后执行金属化处理。为此，暴露半导体层113的其中将要形成源极区域和漏极区域的部分的掩模图案形成在半导体层113上。在对于半导体层113的由掩模图案暴露的部分执行金属化处理之后，从半导体层113移除掩模图案。
使用额外的掩模图案的上述金属化处理要求额外的掩蔽过程，这与使用栅极绝缘膜115作为掩模的金属化处理不同。由于此，使用掩模图案的金属化处理增加了制造时间和成本。
根据此，本公开将栅极绝缘膜115的宽度设置为比栅电极116a的宽度更宽，但是窄于半导体层113的宽度。
栅极绝缘膜115包括没有与栅电极116a交叠的尾部。因此，半导体层113的金属化部分不能够在栅电极116a下面扩展。因此，能够确保具有不小于栅电极116a的宽度的有效宽度的沟道区域113a
图5是示出通过应用根据本公开的实施方式的具有薄膜晶体管的平板显示装置的制造方法获得的元件的增强的性质的数据图。换言之，图5通过比较示出了使用具有尾部的栅极绝缘膜通过金属化处理和使用不具有任何尾部的栅极绝缘膜的另一金属化处理形成的元件的性质。
参考图5，与现有技术的方法相比，根据本公开的具有氧化物薄膜晶体管的平板显示装置的制造方法允许元件（即，氧化物薄膜晶体管）在小的沟道长度范围内获得较窄的阈值电压Vth的偏移宽度和较小的分布区域。因此，本公开能够优化元件的阈值电压Vth的范围。
例如，如果沟道具有大约6μm的长度，则现有技术的方法的元件具有-2.2V的平均阈值电压和对应于2.6V的阈值电压的偏移宽度（即，最大阈值电压与最小阈值电压之间的差），但是通过本公开的制造方法形成的元件具有-0.9V的平均阈值电压Vth和对应于0.4V的阈值电压Vth的偏移宽度（即，最大阈值电压Vth与最小阈值电压Vth之间的差）。
因此，根据本公开的具有氧化物薄膜晶体管的平板显示装置的制造方法即使在应用于必须缩短沟道的长度的小型显示装置的情况下也能够确保元件（即，氧化物薄膜晶体管）的可靠性和稳定性。
参考图4E，层间绝缘膜117形成在缓冲膜102和栅电极116a的整个表面上。而且，通过对层间绝缘膜117进行图案化来在层间绝缘膜117中形成暴露半导体层113的源极区域114a和漏极区域114b的接触孔。
接下来，连接到半导体层113的源电极118a和漏电极118b形成在层间绝缘膜117上。通过在层间绝缘膜上沉积金属膜以填充接触孔并且对金属膜进行图案化来获得源电极118a和漏电极118b。金属膜能够由钌Ru、锌Zn、铟In、锡Sn等等中的至少一种来形成。
之后，钝化膜119形成在层间绝缘膜117上以覆盖源电极118a和漏电极118b。而且，暴露漏电极118b的一部分的接触孔形成在钝化膜119中。此外，通过接触孔120连接到漏电极118b的像素电极121形成在钝化膜119上。
根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置是液晶显示装置。在该情况下，平板显示装置进一步包括堆叠在图4E的薄膜晶体管阵列基板上的液晶层（未示出）和滤色器阵列基板（未示出）。此外，平板显示装置包括布置在薄膜晶体管阵列基板100和滤色器阵列基板的后表面上的偏光板和布置在薄膜晶体管阵列基板100下面作为光源的背光单元。
或者，根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置能够是有机发光显示装置。在该情况下，图4E中所示的薄膜晶体管阵列基板100上的像素电极121变为阳极电极和阴极电极中的一个。
而且，有机发光层形成在各像素区域P内的阳极电极或阴极电极上并且被构造为密封像素区域P的密封基板与薄膜晶体管阵列基板组合，从而形成有机发光显示装置。
以该方式，具有顶栅极型的氧化物薄膜晶体管的平板显示装置能够确保半导体层的有效沟道长度。因此，平板显示装置能够增强元件（即，氧化物薄膜晶体管）的可靠性。
而且，根据本公开的实施方式的具有氧化物薄膜晶体管的平板显示装置的制造方法能够简化制造过程并且减少掩模过程的数目。因此，不仅能够增强产率，而且能够降低制造成本。
虽然已经仅对于上述实施方式限制性地说明了本公开，但是本领域技术人员将理解的是，本公开不限于这些实施方式，而是能够在不偏离本公开的精神的情况下进行各种改变或修改。因此，本公开的范围应该仅由所附权利要求及其等价物来确定而没有限制到详细描述。

Claims (10)

1.一种平板显示装置，所述平板显示装置具有氧化物薄膜晶体管，所述平板显示装置包括；
缓冲膜，所述缓冲膜形成在基板上；
氧化物半导体层，所述氧化物半导体层具有第一长度的宽度并且形成在所述缓冲膜上，其中，所述氧化物半导体层包括金属化的源极区域和金属化的漏极区域；
栅极绝缘膜，所述栅极绝缘膜具有第二长度的宽度并且通过对栅极绝缘材料层进行干法蚀刻而形成在所述氧化物半导体层上；
栅电极，所述栅电极具有第三长度的宽度并且通过对栅电极材料层进行湿法蚀刻而形成在所述栅极绝缘膜上；
层间绝缘膜，所述层间绝缘膜形成在所述基板的整个表面上并且位于所述栅电极上；
源电极和漏电极，所述源电极和所述漏电极形成在所述层间绝缘膜上并且连接到所述氧化物半导体层；
钝化膜，所述钝化膜形成在所述基板的整个表面上并且位于所述源电极和漏电极上；以及
像素电极，所述像素电极形成在所述钝化膜上并且连接到所述漏电极，
其中，所述第一长度大于所述第二长度并且所述第二长度大于所述第三长度，并且
其中，所述栅极绝缘膜包括没有与所述栅电极交叠而与所述氧化物半导体层的所述金属化的源极区域和所述金属化的漏极区域交叠的尾部。
2.根据权利要求1所述的平板显示装置，其中，所述氧化物半导体层包括沟道区域，并且其中，所述栅电极与所述沟道区域交叠。
3.根据权利要求1所述的平板显示装置，其中，所述栅电极由钼Mo、铝Al、铜Cu和钼钛MoTi合金中的至少一种形成。
4.根据权利要求1所述的平板显示装置，其中，所述栅极绝缘膜由选自由硅氧化物SiO2、硅氮化物SiNx和硅氧氮化物SiON组成的材料组的材料形成。
5.根据权利要求1所述的平板显示装置，其中，所述氧化物半导体层由选自由非晶铟镓锌氧化物a-IGZO、非晶铟锡锌氧化物a-ITZO和铟镓氧化物IGO组成的材料组的材料形成。
6.一种制造具有氧化物薄膜晶体管的平板显示装置的方法，所述方法包括：
在基板上形成缓冲膜；
在所述缓冲膜上形成具有第一长度的宽度的氧化物半导体层；
在所述氧化物半导体层上形成具有第二长度的宽度的栅极绝缘膜和具有第三长度的宽度的栅电极；
通过使用所述栅极绝缘膜作为掩模对所述氧化物半导体层进行金属化来形成源极区域和漏极区域；
在所述基板的整个表面上并且在所述栅电极上形成层间绝缘膜；
在所述层间绝缘膜上形成分别连接到所述源极区域和所述漏极区域的源电极和漏电极；
在所述基板的整个表面上并且在所述源电极和所述漏电极上形成钝化膜；以及
在所述钝化膜上形成连接到所述漏电极的像素电极，
其中，所述第一长度大于所述第二长度并且所述第二长度大于所述第三长度，
其中，形成所述栅极绝缘膜和所述栅电极的步骤包括：
在所述基板的整个表面上在所述氧化物半导体层上顺序地形成栅极绝缘材料层和栅电极材料层；
在所述栅电极材料层上形成具有所述第二长度的宽度的光刻胶图案；
通过使用所述光刻胶图案作为掩模对所述栅电极材料层进行湿法蚀刻来形成具有所述第三长度的宽度的所述栅电极；
通过使用所述光刻胶图案作为掩模对所述栅极绝缘材料层进行干法蚀刻来形成具有所述第二长度的宽度的所述栅极绝缘膜；以及
从所述栅电极移除所述光刻胶图案，
其中，所述栅极绝缘膜包括没有与所述栅电极交叠而与所述氧化物半导体层的所述源极区域和所述漏极区域交叠的尾部。
7.根据权利要求6所述的方法，其中，所述栅电极由钼Mo、铝Al、铜Cu和钼钛MoTi合金中的至少一种形成。
8.根据权利要求6所述的方法，其中，所述栅极绝缘膜由选自由硅氧化物SiO2、硅氮化物SiNx和硅氧氮化物SiON组成的材料组的材料形成。
9.根据权利要求6所述的方法，其中，所述氧化物半导体层由选自由非晶铟镓锌氧化物a-IGZO、非晶铟锡锌氧化物a-ITZO和铟镓氧化物IGO组成的材料组的材料形成。
10.根据权利要求6所述的方法，其中，所述第二长度被设置为：使得在所述氧化物半导体层的金属化之后，所述氧化物半导体层的沟道区域的宽度不小于所述栅电极的宽度。
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