TW475271B - N-type thin film transistor and its manufacturing method - Google Patents

Abstract

There are provided an N-type thin film transistor and its manufacturing method. The source/drain of the N-type thin film transistor is composed of metal. A constant charge layer with positive charge is formed at an interface in the oxide layer and close to a channel layer by plasma hydrogenizing process, so as to automatically induce a negative charge layer in an offset region of the channel layer for being used as an extension source/drain. Accordingly, the source/drain doping step and the subsequent annealing step are not required, thereby achieving the purpose of simplifying the manufacturing process and reducing the cost, and making the low temperature processing in the manufacturing easy.

Description

475271 V. Description of the invention α) [Field of the invention] The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to an n-type thin film transistor and a method for manufacturing the same. [Background of the Invention] Fig. 1 is a sectional view showing the structure of a conventional thin film transistor. In the figure, 2 indicates a substrate, and the substrate 2 may be a glass or quartz substrate; 5 indicates a semiconductor layer, and the semiconductor layer may be, for example, a polycrystalline stone (ρ ο I ysiiic ο η) layer; 4 indicates formation The doped region in the abundance conductor layer 5 is used as a source / drain of a thin film transistor; 6 represents a gate oxide layer; 8 represents a gate electrode. The conventional thin film transistor described above must be doped with source / drain electrodes and then tempered, so the implementation steps are complicated, the cost is very high, and it is not conducive to lowering the temperature of the process. [Summary of the Invention] In view of this, the main purpose of the present invention is to provide an n-type thin film transistor and a method for manufacturing the same. The source / drain of the thin film transistor is composed of metal and is hydrogenated by plasma. Processed to form a positively charged fixed charge layer at the interface near the channel layer in the oxide layer, to automatically induce a negative charge layer in the offset area of the channel layer as an extension source / drain (extension S) 〇urce / drain). Therefore, the conventional source / drain doping step of the thin film transistor and the subsequent effect of simplifying the manufacturing process and reducing costs can be omitted, and the tempering process can be achieved, thereby achieving another purpose of the present invention. ^ Providing 1 ^ Low temperature after completion. A method for manufacturing an n-type thin film transistor is used to manufacture the aforementioned n-type thin film transistor. In order to achieve the above-mentioned object, the present invention provides " a type of η-type thin film electricity

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475271 V. Description of the invention (2) Crystal including: 'substrate, a semiconductor layer 5 is formed on the surface of the above substrate, and active / drain electrodes are formed on both edge sides, and a channel region is formed between the source / drain electrodes; A dielectric layer is formed on the surface of the semiconductor layer, and the source / drain electrodes on both edge sides of the semiconductor layer are exposed, and there are positive electric charges on both edge sides of the layer. A gate layer is formed on the dielectric layer. A surface of the layer; and a protective layer formed on the surface of the gate layer and the dielectric layer. In addition, in order to achieve the above-mentioned manufacturing method of the n-type thin film transistor, another object of the present invention is to provide the following steps: Provide the above-mentioned plasma forming the formation formation side so as to remove the above-mentioned semiconducting metal and a substrate having a dielectric layer being formed; a semiconductor, a dielectric layer, and a gate layer; the dielectric layer exposes the above-mentioned electric charges; a protective layer, and In J1, the surface of the insulating layer is transformed into the surface of the insulating substrate; the surface of the conductor layer; the surface of the electrical layer, and the two edge layers are located on the above and above the above and above the above. The above-mentioned dielectric layer exposed on both edge sides of the gate layer is exposed from the semi-conductive layer on the gate located on both sides of the edge of the two-layered protective layer and the dielectric layer on the edge side having the positive electric charge is exposed; the edge side is exposed; The dielectric layer so that the part is exposed; and the side portions 5 on both edges of the body layer to define I w 1! II 1 1 lirnm \ W \ Sra 1 1 0522-5730TWF.ptd page 5 475271 5. Description of the invention (3 ) Source / Impolar. [Brief description of the drawings] FIG. 1 is a sectional view showing the structure of a conventional thin film transistor. Figures 2a to 2i are cross-sectional views showing the manufacturing process of the n-type thin film transistor of the present invention. Fig. 3 is a sectional explanatory view showing an n-type thin film transistor of the present invention. FIG. 4 is a graph showing a characteristic of a drain current (Id) versus a gate voltage (Vg) of an n-type thin film transistor of the present invention. [Symbol description] 4 ~ source / drain area: 6 ~ gate oxide layer 10 ~ substrate; 2 2 ~ source / drain area 2 6 compensation area; 40 ~ gate layer; 60 ~ metal layer. 2 ~ substrate; 5 ~ semiconductor layer 8 ~ gate; 20 ~ semiconductor layer 2 4 channel area; 30 ~ dielectric layer; 50 ~ protective layer; [Detailed description of the invention] Features and advantages can be made clearer The above and other objects of the invention are obvious and easy to understand. Hereinafter, preferred embodiments are described in detail with the accompanying drawings as follows: [Embodiment] Referring to FIG. 2a to FIG. 2i, this 2a Figures 2 to 2i are cross-sectional views showing the manufacturing process of the n-type thin film transistor of the present invention. First, as shown in FIG. 2a, an insulating substrate 10 is provided, and hereby

0522-5730TWF.ptd Page 6 475271 V. Description of the invention (4) ____ Surface formation of edge substrate ίο-The material of Feng can be selected from, for example, Si 0 and α. Here, the insulating substrate 1 (the layer 20 may be, for example, one of polycrystalline silicon and quartz crystal, and the above-mentioned semiconductor is, as shown in FIG. 2b, a dielectric layer 30. Here, ⑽ The surface formation method of the conductor layer 20 (hereinafter referred to as CVD, etc.). For example, by chemical vapor deposition, the oxide layer 5 can be, for example, -20% of the oxide layer 5, and the oxide layer, such as silicon oxide. (S i 02) layer. As shown in FIG. 2C of the receiver 1, 5 is on the island-like interpolar layer 4. 'Make the two edge sides of the above; surface: ί-the above-mentioned interpolar layer 4. The composition may be For example ;;, ". Layer ... here, out of top: mediation i: 2 2 κ: 2 gate layer 40 exposed on both edge sides (as shown in Figure 2e). Shi Sheng, snow p / to Make it have a positive electric charge)) and gas, ν, di Erqiu hydrogenation treatment is ~ ~ 3 hours in the presence of a mixed gas with pedigree and lice ^ U2) ... and preferably 3 hours ... Huaxiao = 'As shown in Figure 2e, a protective layer 5 ° is formed on the surface of the above gate layer 40 and the above: and the bismuth of water and bismuth on both edges has been deposited by the lice phase method (hereinafter referred to as PECVD ) The formed compound layer: This oxide layer can be, for example, a silicon dioxide (Si02) layer. As shown in FIG. 2f after the hole, the exposed dielectric layer 50 is removed ^ In order to make the two sides of the above-mentioned semiconductor layer 20 appear as follows: As shown in FIG. 2δ, the person on the substrate 10, the semiconductor layer 20, and the thunder

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Description of the invention (5) The surface of the layer 30 and the protective layer 50 can be imported only from the above-mentioned semiconductors "·; ::! To form—the metal layer 60. Here, the metal layer 6 is formed. The above: ΪΓ 二 = The surface of the exposed part of the edge side is abbreviated as the PVD method to shape the surface. The ri. The thickness of nickel and aluminum is ~ 50nm. 乂 · 4 丁. The thickness of the metal layer formed is then followed by a heat treatment step so that the edge portion of the semiconductor substrate and the metal layer 6 described above. A 卞 4 卞, 宁 2, 宁, Ningcha mountain, Dian /, 鸯 belong to b (j reaction to form a metal compound, which is defined as the source / drain electrode 22, and located at the source / drain electrode, b is 24, The result is as shown in Figure 2h, where ^ J of ^ is a through-force zone ^ ^ φ ^ ^ ^ " The heat treatment step on Λ can be a copper T such as / == atmosphere T, in a rapid tempering furnace by 5. Cao C 2 = execution time of 2 to 2 minutes; In addition, the second 3 is also performed in the hot furnace tube at a temperature range of 25 to 50,000, the earth knife clock to 2 hours of execution Time to do it. I 〇- 占 Γί: Remove the other metal layers that have not reacted to form metal compounds, that is, the Ώ-type thin film transistor of the present invention as shown in the figure. The above-mentioned "response metal layer can be easily cut as h2s〇4 It can be removed by using a mixed solution; it can also be removed by using a mixed solution of, for example, NH4OH, ± 0, and 10. See Figure 3, Figure 3 shows the fourth type of thin film transistor of the present invention. In the figure, 2 and 6 show compensation (0ffse 7) & located in the channel area. As shown in FIG. 3, the n 槊 thin film transistor of the present invention uses a plasma hydrogenation process to make oxides. In the layer 30, a positively charged fixed charge layer is formed at the interface near the channel layer 24, so the positively charged solid ^ cladding layer can be induced in the compensation area 2 g of the channel layer 24. ~ Negative Charge Layer

〇522-5730TWF.ptd Page 8 475271 I V. Description of the invention (6) I will be used as the extension of the thin film transistor # source / drain (extension source I „k / drain). Therefore, it is possible to omit the learning source / ¾ The extreme doping steps and subsequent tempering procedures can achieve the effect of simplifying the process, reducing costs, and reducing the temperature of the process. In addition, Figure 4 shows the n-type thin film transistor of the present invention The characteristic diagram of the drain current Id vs. the gate voltage (Vg) is a graph of the results of 岀 obtained under the conditions of channel length (L · I) / channel width (W) = 40/50.甴 此 | The change of the characteristic curve can verify the characteristic cancer performance of 5n thin film transistor

ipresent. I Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

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Claims (1)

475271 j 六 、 Scope of patent application | L An n-type thin film transistor, including: I a substrate; | Ding body layer formed on the surface of the above substrate, and on both sides of the edge | forming active / drain, and source / drain There is a channel between the poles; j A dielectric layer 5 is formed on the surface 5 of the semiconducting layers and exposes the source / drain electrodes on both sides of the semiconducting body layer, and has a positive edge on the rain edge side of the layer. μ I electrical charge; I. j a gate layer 5 is formed on the surface of the dielectric layer; and a protective layer 5 is formed on the gate layer and the surface of the dielectric layer. 2. The n-type thin film transistor according to item 1 of the scope of the patent application, wherein the material of the substrate is selected from one of Si% and quartz. I 3. The n-type thin film transistor according to item 1 of the scope of the patent application, wherein the semiconductor layer is a polycrystalline silicon layer. '! 4 · The η-type thin film transistor described in item 1 of the scope of patent application, wherein the material of the source / drain is nickel silicide. 5. The n-type thin film transistor as described in item 1 of the patent application, wherein the foregoing is described above. The dielectric layer is an oxide layer formed by a CVD method. 6. The n-type thin film transistor according to item 5 of the scope of the patent application, wherein the oxide layer is a silicon dioxide layer. The H-type thin film transistor described in item i of the above item, the application material of the above gate layer is metal σ. K, +, ί π η described in item 1 of the patent scope Thin film transistor, where i, 'y, ΰ s are oxide layers formed by PECVD method. i. Scope of patent application 、 9 · The thin film transistor as described in item 8 of Shenmeng's patent scope, wherein the above oxide layer is a silicon dioxide layer. ^! | 10β— ^ η thin film transistor manufacturing method includes the following steps: j providing a substrate; 1 forming a semiconductor layer on the surface of the above-mentioned insulating substrate; 1 forming a dielectric layer on the surface of the above-mentioned semiconductor layer; In: the surface of the dielectric layer is described, and the above-mentioned dielectric lightning transport exposed on both edges of the gate layer by hydrogenation of the plasma at the two edges has a positive electric charge; a dielectric layer is formed on the gate layer and The surface of the electrical layer having a positive electric charge, and the dielectric layer exposed on both edge sides is exposed; 'so that the dielectric chips exposed on the two edge sides of the protective layer are removed, and the two edge side portions of the semiconductor layer are removed. Exposure; and metallization of both edge-side source / drain electrodes of the semiconductor layer exiting as defined above. ^ 11 · As described in the scope of the patent application No. 丨 〇 In the thin thin film, ，, Gan A > ^ ^ Bao Riyue Qi I method /, I The material of the above substrate is selected from Si〇2 And Quartz ”: Fang Shen: Each method of making n-type thin m transistor described in item u of the patent scope 'where the above-mentioned semiconductor layer is a polycrystalline silicon layer. I 3. As for patent application scope No. 10 The manufacturing method of the n-type thin crystalline thin film described in the above item, wherein the dielectric layer is a garment made by CVD method 475271 VI. Patent application park 1 4. The manufacturing method of the η-type thin film transistor as described in item 10 of the scope of patent application, wherein the structure of the above gate electrode layer is made of metal. 15. The method for manufacturing an η-type thin film transistor according to item iO in the scope of the patent application, wherein the above-mentioned plasma hydrogenation step is performed by performing a predetermined time under an atmosphere in which a mixed gas of hydrogen and nitrogen exists. 1 6. The method for manufacturing an η-type thin film transistor according to item 15 of the scope of the patent application, wherein the predetermined time is 1 to 3 hours. ί 7. The method for manufacturing an n-type thin film transistor as described in item 10 of the scope of the patent application, wherein the protective layer is an oxide layer formed by a PECVD method. 1 8. The method for manufacturing an n-type thin film transistor according to item 17 in the scope of the patent application, wherein the above oxide layer is a dioxide > 5th layer. 19. The method for manufacturing an η-type thin film transistor according to item 10 of the scope of the patent application, wherein the metallization step includes the following steps: forming a metal layer on a surface of both edge side portions of the exposed semiconductor layer; A heat treatment step is performed to define the source / drain electrodes by reacting the two edges of the semiconductor layer with the metal layer to form a metallization 5; and removing other metallization layers that are not reacted to the metallization. 20. The method for manufacturing an n-type thin film transistor according to item 19 of the scope of the patent application, wherein the metal layer is formed by a PVD method. 2 1. The method for manufacturing an η-type thin film transistor according to item 19 in the scope of the patent application, wherein the material of the metal layer is selected from one of titanium, nickel, and hafnium 0522-5730TWF.ptd Page 12 475271 6. Scope of Patent Application I! I capsule 丨: I 2 2. The manufacturing method of the η-type thin film transistor described in item 19 of the application patent I I | manufacturing method, wherein the thickness of the above metal layer is ≦ Onm˜5 〇ηοι. | | 23. The manufacturing method of the η-type thin film transistor described in item 19 of the scope of patent application! I manufacturing method, wherein the above heat treatment step is in a predetermined atmosphere-a predetermined application | I temperature range and a predetermined execution time The next step is to carry out in a rapid tempering furnace. 0 I ί ii I 24. Production of the η-type thin film transistor as described in item 23 of the scope of patent application! I manufacturing method, wherein the predetermined atmosphere is argon and The above-mentioned predetermined execution temperature range of nitrogen 5 is 500 ~ 600 ° C, and the above-mentioned predetermined execution time is 30 seconds ~ 2 minutes ^ I. PI! 2 5. The manufacturing method of the η-type thin film transistor described in item 19 of the scope of patent application | i § |, the above-mentioned heat treatment step is applied in a predetermined atmosphere, a predetermined temperature range and It is performed in a hot furnace tube for a predetermined execution time. I 26. The manufacturing method of the η-type thin film transistor described in item 25 of the scope of patent application, wherein the above-mentioned predetermined atmosphere is argon and nitrogen, and the above-mentioned predetermined execution j 1 temperature range is 2 5 0 ~ 5 0 0 ° C, the above stated execution time is 10 minutes to 2 hours | hours. I [27. The manufacturing method of the η-type thin film transistor described in item 19 of the scope of the patent application, wherein the step of removing the unreacted metal layer is performed by using a mixed solution of team 804 and H 2 o 2.丨 | 28. The manufacturing method of the η-type thin film transistor described in item 19 of the scope of patent application, wherein the step of removing the unreacted metal layer is a method of mixing NH40H, H2 02 and 1120. get on. | 0522-5730TWF.ptd Page 13