WO2013143311A1 - 晶体管的制作方法、晶体管、阵列基板以及显示装置 - Google Patents

晶体管的制作方法、晶体管、阵列基板以及显示装置 Download PDF

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Publication number
WO2013143311A1
WO2013143311A1 PCT/CN2012/085476 CN2012085476W WO2013143311A1 WO 2013143311 A1 WO2013143311 A1 WO 2013143311A1 CN 2012085476 W CN2012085476 W CN 2012085476W WO 2013143311 A1 WO2013143311 A1 WO 2013143311A1
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Prior art keywords
region
layer
gate
source
insulating
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PCT/CN2012/085476
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English (en)
French (fr)
Inventor
姜春生
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京东方科技集团股份有限公司
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Priority to US13/876,630 priority Critical patent/US8889444B2/en
Priority to JP2015502061A priority patent/JP6055077B2/ja
Priority to KR1020137008589A priority patent/KR101467711B1/ko
Priority to EP12830912.7A priority patent/EP2667404B1/en
Publication of WO2013143311A1 publication Critical patent/WO2013143311A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Definitions

  • Embodiments of the present invention relate to a method of fabricating a transistor, a transistor, an array substrate, and a display device. Background technique
  • Oxide TFT An Oxide Thin Film Transistor (Oxide TFT) is used as a driver for a pixel region, and is used to control the rotation of the liquid crystal in a back panel of a liquid crystal display (LCD) such that pixel regions generate different gray scales;
  • AMOLED Active Matrix/Organic Light Emitting Diode
  • it is used to control the brightness of the electroluminescent layer such that the pixel regions generate different gray levels.
  • the process of fabricating the double bottom gate OTFT is as follows:
  • a layer of metal typically molybdenum metal, is deposited on the substrate, and a double bottom gate structure comprising two identical gate metal layers 101 is formed after etching, that is, the Gate layer 101, as shown in FIG. 1A;
  • a layer of insulating material is laid on the Gate layer 101 to form a Gate Insulator (GI) layer 102 as shown in FIG. 1B;
  • GI Gate Insulator
  • an Indium Gallium Zinc Oxide is deposited on the GI layer 102 to form an IGZO layer 103 as shown in FIG. 1C, and the IGZO layer can serve as a semiconductor layer of the OTFT;
  • an inorganic non-metal material is deposited on the IGZO layer 103, and a barrier layer 104 is formed after etching, as shown in FIG. 1D.
  • the barrier layer is used to prevent IGZO from being destroyed when the source metal layer and the drain metal layer are subsequently etched.
  • a layer of metal is deposited on the barrier layer 104, and after etching, a source metal layer 106 as a source, a drain metal layer 105 as a drain, and an intermediate metal layer 107 are formed, as shown in FIG. 1E;
  • PVX is deposited on the source metal layer, the drain metal layer, and the intermediate metal layer to form an insulating layer 108, as shown in Fig. 1F.
  • the working principle of OTFT is as follows: First, a digital signal is added to the source metal layer, that is, a Data signal. Second, a voltage is applied to the gate metal layer. When the voltage is greater than a certain value, the IGZO layer starts to conduct, and carriers can be formed in the IGZO layer. At this time, the digital signal added on the source metal layer is transferred to the drain metal layer through the carrier, so that the electroluminescent material connected to the drain emits light;
  • the OTFT of the double-gate structure fabricated by the prior art has a large area occupied by the pixel region.
  • the width of the double bottom gate is at least 40 ⁇ m, which has a large influence on the aperture ratio of the array substrate having a pixel size of 50 200 ⁇ m.
  • the aperture ratio refers to the ratio of the area of the actual permeable area to the total area of the unit pixel in the unit pixel. Obviously, the higher the aperture ratio, the higher the light transmittance. Therefore, when the area of the double bottom gate is larger, the aperture is opened. The smaller the rate, the lower the light transmittance. Summary of the invention
  • An embodiment of the present invention provides a method of fabricating a transistor, including: forming a first source and drain metal layer on a substrate; forming an insulating layer on the first source and drain metal layers; The layer includes a first insulating region and a second insulating region, the first insulating region and the second insulating region are oppositely disposed with respect to a center line of the first source and drain metal layers with a blank region therebetween; Forming a gate metal layer thereon; the gate metal layer includes a first gate region and a second gate region, and the first gate region covers the first insulating region, and the second gate region covers a second insulating region; a gate insulating layer formed on the gate metal layer; a semiconductor layer formed on the gate insulating layer; an orthographic projection region of the semiconductor layer covering the first source and drain An etch stop layer is formed on the semiconductor layer; an orthographic projection area of the etch stop layer covers a blank area between the first insulating region and the second insulating region; Forming a second
  • An insulating layer is formed on the second source and drain metal layers.
  • a transistor including: a substrate and a first source and drain metal layer on the substrate; and a first insulating region covering a portion of the first source and drain metal layers And a second insulating region, the first insulating region and the second insulating region are opposite to the first source And a drain metal layer center line oppositely disposed with a blank region therebetween; a first gate region covering the first insulating region and a second gate region covering the second insulating region; covering the first gate a gate region, a gate insulating layer of the second gate region; a semiconductor layer on the gate insulating layer, and an orthographic projection region of the semiconductor layer covers the first source and drain metal layers; An etch stop layer on the semiconductor layer, and an orthographic projection area of the etch stop layer covers the blank region; a source region and a drain region respectively located on the etch barrier layer; An orthographic projection region formed by the polar region covers an overlapping portion of the semiconductor layer and the first gate region; and the orthographic projection region formed by
  • Still another embodiment of the present invention provides an array substrate including the above-described crystal tube.
  • Yet another embodiment of the present invention provides a display device including the above array substrate.
  • the structure of the left OTFT from bottom to top is: a source and a drain metal layer, a first insulating region, a first gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a source region; and a structure of the right OTFT from bottom to top is: a first source And a drain metal layer, a second insulating region, a second gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a source region; it can be seen that the two OTFTs formed by the method share a first source And a drain metal layer, the first source and drain metal layers being used as a source metal layer in one of the OTFTs and as a drain metal layer in the other OTFT, and each of the OTFTs has its own gate; And the source, the gate and the drain metal layer, a first insulating region, a first gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a
  • FIG. 1A is a schematic structural view showing a first structure formed in a process of fabricating a transistor in the prior art
  • FIG. 1B is a schematic structural view showing a second structure in a process of fabricating a transistor in the prior art
  • FIG. 1C is a transistor fabricated in the prior art
  • FIG. 1D is a schematic structural view of forming a fourth structure in the process of fabricating a transistor in the prior art
  • FIG. 1E is a schematic structural view of forming a fifth structure in the process of fabricating a transistor in the prior art
  • 1F is a schematic structural view of forming a sixth structure in a process of fabricating a transistor in the prior art
  • FIG. 2A is a schematic structural view of a metal layer of a transistor according to an embodiment of the present invention
  • 2B is a schematic diagram of a first structure of a transistor according to an embodiment of the present invention.
  • 2C is a schematic diagram of a second structure of a transistor according to an embodiment of the present invention.
  • 2D is a schematic diagram of a third structure of a transistor according to an embodiment of the present invention.
  • 2E is a schematic view showing a fourth structure of a transistor according to an embodiment of the present invention.
  • 2F is a schematic diagram showing a fifth structure of a transistor according to an embodiment of the present invention.
  • 2G is a schematic diagram of a sixth structure of a transistor according to an embodiment of the present invention.
  • 2H is a schematic diagram showing a seventh structure of a transistor according to an embodiment of the present invention.
  • FIG. 3 is a structural diagram of another transistor according to an embodiment of the present invention. detailed description
  • two OTFTs sharing the same first source and drain metal layers can be obtained; as shown in FIG. 2H, the structure of the left OTFT from bottom to top is: a source and a drain metal layer, a first insulating region, a first gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a source region; and a structure of the right OTFT from bottom to top is: a first source And a drain metal layer, a second insulating region, a second gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a source region; it can be seen that the two OTFTs formed by the method share a first source And a drain metal layer, the first source and drain metal layers being used as a source metal layer in one of the OTFTs and as a drain metal layer in the other OTFT, and each OTFT has its own And the source, the gate and the drain of the two OT
  • a manufacturing method according to an embodiment of the present invention includes the following steps:
  • Step 21 forming a first source and drain metal layer on the substrate
  • Step 22 forming an insulating layer on the first source and drain metal layers;
  • the insulating layer includes a first insulating region and a second insulating region, and the first insulating region partially covers the first source And one side of the drain metal layer;
  • the second insulating region partially covers the other side of the first source and drain metal layers; the remaining portions of the first insulating region and the second insulating region are located On the substrate;
  • Step 23 forming a gate metal layer on the insulating layer;
  • the gate metal layer includes a first gate region and a second gate region, and the first gate region covers the first insulating region, The second gate region covers the second insulating region;
  • Step 24 forming a gate insulating layer on the gate metal layer
  • Step 25 forming a semiconductor layer on the gate insulating layer; an orthographic projection region of the semiconductor layer covers the first source and drain metal layers;
  • Step 26 forming an etch stop layer on the semiconductor layer; an orthographic projection area of the etch stop layer covers a blank area between the first insulating region and the second insulating region;
  • Step 27 forming a second source and drain metal layer on the etch barrier layer; the second source and drain metal layers including a source and drain regions of the second source and drain metal a front projection region formed by the source region covers an overlapping portion of the semiconductor layer and the first gate region; and an orthographic projection region formed by the drain region covers an overlap of a semiconductor layer and a second gate region section;
  • Step 28 forming an insulating layer on the second source and drain metal layers.
  • forming a gate insulating layer on the gate metal layer includes, but is not limited to, a method of: chemically vapor depositing a silicon nitride-based or silicon oxide-based layer on the gate metal layer to form a gate insulating layer.
  • a portion corresponding to a blank region between the first insulating region and the second insulating region may be left, and a gate of the blank region may be etched away. Extremely insulating layer.
  • forming a semiconductor layer on the gate insulating layer includes, but is not limited to, a method of: sputtering an indium gallium oxide on the gate insulating layer, and forming a semiconductor layer after etching.
  • forming an insulating layer on the second source and drain metal layers includes, but is not limited to, the following methods:
  • An insulating material is chemically vapor deposited on the second source and drain metal layers to form an insulating layer.
  • two OTFTs can share a first source and drain metal layer; that is, the first source and drain metal layers can serve as a source in one of the OTFTs, and the other As the drain of the OTFT, it can be seen that the structure can reduce the area occupied by the source/drain in the prior art;
  • the gate, the source, and the drain of each OTFT are located in the vertical direction, which reduces the area occupied by the OTFT compared with the OTFT structure in the prior art, and thus can be improved.
  • the aperture ratio of the array substrate is located in the vertical direction, which reduces the area occupied by the OTFT compared with the OTFT structure in the prior art, and thus can be improved.
  • an embodiment of the present invention provides a method for fabricating a transistor, by which a dual-gate OTFT having a vertical structure of the same source/drain metal layer can be obtained, thereby greatly reducing OTFT.
  • the area occupied is increased by the aperture ratio of the array substrate as follows:
  • Step 1 as shown in FIG. 2A, forming a first source and drain metal layer 31 on the substrate;
  • the first source and drain metal layers 31 may be formed by sputtering a layer of metal on the substrate after etching;
  • the first source and drain metal layers 31 may be made of a metal such as molybdenum, molybdenum/aluminum/molybdenum.
  • the first source/drain metal layer serves as the source of one of the OTFTs, it serves as the drain of the other OTFT.
  • Step 2 as shown in FIG. 2B, an insulating layer including a first insulating region 32 and a second insulating region 33 is formed on the first source and drain metal layers 31, and the first insulating region 32 partially covers the first source And one side of the drain metal layer 31; the second insulating region 33 partially covers the other side of the first source and drain metal layers 31; the remaining portions of the first insulating region 32 and the second insulating region 33 are located on the substrate on;
  • an insulating layer can be formed by suspending a layer of insulating material on the first source and drain metal layers 31.
  • first insulating region 32 and the second insulating region 33 there is a blank area between the formed first insulating region 32 and the second insulating region 33.
  • first insulating region 32 and the second insulating region 33 are oppositely disposed with respect to a center line of the first source and drain metal layers, and a portion of the first source and drain metal layers are covered on both sides of the center line. And exposing the first source and drain metal layers in the blank region.
  • the insulating material used may be a photo-sensitive resin material such as PDI 1000, in which case a photo-etching process (hoto) may be used.
  • Step 3 as shown in FIG. 2C, forming a gate metal layer including the first gate region 34 and the second gate region 35 on the insulating layer, and the first gate region 34 covers the first insulating region 32, and second The gate region 35 covers the second insulating region 33;
  • a gate metal layer can be formed by sputtering a metal on the insulating layer and etching.
  • first gate region 34 and the second gate region 35 also have an interval corresponding to a blank region between the first insulating region 32 and the second insulating region 33.
  • the metal used in this step is a metal such as molybdenum, molybdenum/aluminum/molybdenum.
  • Step 4 as shown in FIG. 2D, forming a gate insulating layer 36 on the gate metal layer, and etching the gate insulating layer of the blank region (ie, the bottom of the U-shaped structure in the figure) by dry etching;
  • the gate insulating layer 36 can be formed by chemical vapor deposition of a silicon nitride-based or silicon oxide-based compound on the gate metal layer.
  • the gate insulating layer corresponding to the blank region is etched away, but embodiments of the present invention are not limited thereto. In other embodiments in accordance with the invention, a gate insulating layer corresponding to the blank region may also be retained.
  • Step 5 forming a semiconductor layer 37 on the gate insulating layer 36, as shown in FIG. 2E; the semiconductor layer 37 forms an orthographic projection region covering the first source and drain metal layers 31;
  • indium gallium oxide can be sputtered on the gate insulating layer 36 (Indium Gallium Zinc)
  • Oxide, IGZO), a semiconductor layer 37 is formed after etching.
  • Step 6 forming an etch stop layer 38 on the semiconductor layer 37, as shown in FIG. 2F; the erbium barrier layer 38 forms an orthographic projection area covering a blank area between the first insulating region 32 and the second insulating region 33;
  • an etch stop can be formed by sputtering an inorganic non-metal material on the semiconductor layer 37.
  • Step 7 forming a second source and drain metal layer including a source region 39 and a drain region 310 on the etch barrier layer 38, as shown in FIG. 2G; wherein the source region 39 forms an orthographic projection region covering the semiconductor An overlapping portion of the layer 37 and the first gate region 34; an orthographic projection region formed by the drain region 310 covers an overlapping portion of the semiconductor layer 37 and the second gate region 35;
  • a second source and drain metal layer can be formed by etching a metal on the etch stop layer 38 after etching;
  • the metal used in this step is molybdenum, molybdenum/aluminum/molybdenum, and the like.
  • Step eight forming an insulating layer 311 on the second source and drain metal layers, as shown in Fig. 2H.
  • the insulating layer 311 can be formed by chemical vapor deposition of an insulating material on the second source and drain metal layers.
  • the insulating material used in this step may be SiOx.
  • the blank region is located at an intermediate position between the first source and drain metal layers 31, that is, the shape of the orthographic projection region of the first insulating region 32 formed on the first source and drain metal layers 31 and the second insulation
  • the area of the orthographic projection area formed on the first source and drain metal layers 31 of the region 33 is the same; the area of the orthographic projection area formed by the first insulating region 32 on the first source and drain metal layers 31 and the second
  • the area of the orthographic projection area formed on the first source and drain metal layers 31 of the insulating region 33 is equal.
  • the shape of the orthographic projection region produced by the first gate region 34 on the substrate is the same as the shape of the orthographic projection region produced by the second gate region 35 on the substrate; the orthographic projection of the first gate region 34 on the substrate
  • the area of the area is equal to the area of the orthographic projection area produced by the second gate region 35 on the substrate.
  • the shape of the orthographic projection region generated on the substrate by the source region 39 is the same as the shape of the orthographic projection region generated on the substrate by the drain region 310; the area and the drain of the orthographic projection region generated on the substrate by the source region 39.
  • the area of the orthographic projection area produced by the area 310 on the substrate is equal.
  • a dual-gate OTFT having a vertical structure can be obtained.
  • a blank region is used as a boundary line, and the left and right sides respectively include an OTFT having a vertical structure; and the structure of the OTFT formed on the left side from the bottom to the top includes a first source and drain metal layer 31, a first insulating region 32, a first gate region 34, a gate insulating layer 36, a semiconductor layer 37, an etch stop layer 38, and a source region 39;
  • the structure of the OTFT formed from the bottom to the top includes: a first source and a drain gold The dying layer 31, the second insulating region 33, the second gate region 35, the gate insulating layer 36, the semiconductor layer 37, the etch stop layer 38, and the drain region 310.
  • the source region 39 should implement the drain function; when the first source and drain metal layers 31 are on the right side
  • the drain region 310 should implement the source function.
  • the width of the first source and drain metal layer 31 is 4 micrometers, the length is 2 micrometers, the width of the blank region is 3.8 ⁇ m, and the length is 2 ⁇ m, the OTFT on the left side is taken as an example, the first source and The width of the overlapping region of the drain metal layer 31 and the source region 39 in the vertical direction is ⁇ . ⁇ .
  • the electric field intensity is relatively large, and the electrical performance requirement can be satisfactorily satisfied, so that a good switching effect can be obtained.
  • the width of the source region 39 and the drain region 310 may be 4 micrometers, respectively, and the width of the blank region is 3.8 ⁇ m.
  • the width of the double-gate OTFT having a vertical structure formed at this time is less than 12 micrometers, which is much smaller than 40 microns in the prior art.
  • the embodiment of the present invention provides a transistor, the transistor including: a first insulating region partially covering a side of a first source and drain metal layer; partially covering the first source and drain a second insulating region on the other side of the polar metal layer; and the remaining portions of the first insulating region and the second insulating region are on the substrate;
  • first gate region covering the first insulating region
  • second gate region covering the second insulating region
  • a semiconductor layer on the gate insulating layer, and an orthographic projection region of the semiconductor layer covers the first source and drain metal layers;
  • An etch stop layer on the semiconductor layer, and an orthographic projection area of the etch stop layer covers the blank region;
  • an orthographic projection region formed by the source region covers an overlapping portion of the semiconductor layer and the first gate region; Forming the orthographic projection area to cover an overlapping portion of the semiconductor layer and the second gate region;
  • first insulating region and the second insulating region have the same or similar area of the orthographic projection regions produced on the first source and drain metal layers.
  • the first projection area and the second projection area have the same or similar area of the orthographic projection area produced on the substrate.
  • the source region and the drain region have the same shape and equal area of the positive projection regions produced on the substrate.
  • the width of the orthographic projection area of the first gate region and the second gate region formed on the first source and drain metal layers is 0.1 micron.
  • the embodiment of the invention further provides an array substrate, wherein the array substrate comprises the above transistor.
  • the embodiment of the invention further provides a display device, which comprises the above array substrate.
  • the structure of the left OTFT from bottom to top is: a source and a drain metal layer, a first insulating region, a first gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a source region; and a structure of the right OTFT from bottom to top is: a first source And a drain metal layer, a second insulating region, a second gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a source region; it can be seen that the two OTFTs formed by the method share a first source And a drain metal layer, the first source and drain metal layers being used as a source metal layer in one of the OTFTs and as a drain metal layer in the other OTFT, and each of the OTFTs has its own gate; And the source, the gate and the drain metal layer, a first insulating region, a first gate region, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a
  • the width of the source region and the drain region of the transistor provided by the embodiment of the present invention may be 4 micrometers, and the width of the blank region is 3.8 ⁇ m.
  • the width of the double-gate OTFT having a vertical structure formed at this time is smaller than 12 microns, much smaller than the 40 microns in the prior art.
  • the gate insulating layer 36 is formed on the gate metal layer, so that the gate insulating layer of the blank region (ie, the bottom of the U-shaped structure in the drawing) is etched.
  • the gate insulating layer may also cover the blank regions of the first insulating region and the second insulating region, and the specific structure is as shown in FIG. 3.
  • FIG. 3 is a structural diagram of another transistor according to an embodiment of the present invention. Since the thickness of the gate insulating layer is thin, the semiconductor layer can break through the gate insulating layer and the first source and drain at this time.
  • the pole metal layers are connected to each other to realize the function of the TFT.
  • the embodiment of the present invention is not limited to the OTFT, and may be other TFTs such as a-si, low temperature polysilicon, or the like.

Abstract

提供一种晶体管的制作方法、晶体管、阵列基板以及显示装置。晶体管的制作方法包括：形成第一源极和漏极金属层（31）；在第一源极和漏极金属层上形成包含第一绝缘区域（32）和第二绝缘区域（33）的绝缘层；在绝缘层上形成包含第一栅极区域（34）和第二栅极区域（35）的栅极金属层；在栅极金属层上形成栅极绝缘层（36）；在栅极绝缘层形成半导体层（37）；在半导体层上形成刻蚀阻挡层（38）；在刻蚀阻挡层上形成包括源极区域（39）和漏极区域（310）的第二源极和漏极金属层；在第二源极和漏极金属层上形成绝缘层（311）。通过该方法制作的晶体管可提高阵列基板的开口率。

Description

晶体管的制作方法、 晶体管、 阵列基板以及显示装置 技术领域
本发明的实施例涉及晶体管的制作方法、 晶体管、 阵列基板以及显示装 置。 背景技术
氧化物薄膜场效应晶体管（ Oxide Thin Film Transistor, Oxide TFT )作为 像素区域的驱动器， 在液晶显示器（Liquid Crystal Display, LCD )的背板中 用于控制液晶的旋转使得像素区域产生不同的灰阶； 在有源矩阵有机发光二 极体面板（Active Matrix/Organic Light Emitting Diode, AMOLED )中， 用于 控制电致发光层的亮度， 使得像素区域产生不同的灰阶。 如图 1A至图 1F所 示， 制作双底栅 OTFT的流程如下：
第一、 在基板上沉积一层金属， 一般是钼金属， 刻蚀后形成包括两个相 同的栅极金属层 101的双底栅结构， 即 Gate层 101 , 如图 1A所示；
第二、 在 Gate层 101上铺设一层绝缘材料， 形成如图 1B所示的栅极绝 缘（ Gate Insulator, GI )层 102;
第三、 在 GI层 102上铺设铟镓辞氧化物 (Indium Gallium Zinc Oxide, IGZO), 形成如图 1C所示的 IGZO层 103 , IGZO层可作为 OTFT的半导体 层；
第四、 在 IGZO层 103上沉积无机非金属材料， 刻蚀后形成阻挡层 104, 如图 1D所示图形； 阻挡层用于防止在后续刻蚀源极金属层和漏极金属层时 破坏 IGZO层；
第五、 在阻挡层 104上沉积一层金属， 刻蚀后分别形成作为源极的源极 金属层 106, 作为漏极的漏极金属层 105, 以及中间金属层 107, 如图 1E所 示；
第六、 在源极金属层、 漏极金属层以及中间金属层上沉积 PVX, 形成绝 缘层 108, 如图 1F所示。
以 AMOLED中的双底栅 OTFT为例， OTFT的工作原理如下： 首先， 为源极金属层加上数字信号即 Data信号； 其次， 为栅极金属层加 电压， 当电压大于一定值时， IGZO层开始导通， 此时可在 IGZO层中形成 载流子。 此时增加在源极金属层上的数字信号就会通过载流子传递到漏极金 属层上， 使得与漏极相连的电致发光材料发光；
但本发明人发现， 使用现有技术制作的双底栅结构的 OTFT, 其在像素 区域所占的面积较大， 例如， 如果 OTFT釆用的长宽比值为： W/L=18/9, 则 可得出双底栅的宽度最小为 40μπι, 这样对于像素尺寸为 50 200μπι的阵列 基板的开口率的影响较大。 开口率是指在单元像素内， 实际可透光区的面积 与单元像素总面积的比率， 显然开口率越高， 光透过率也越高， 因此， 当双 底栅的面积越大则开口率越小， 光透过率也越低。 发明内容
本发明的一个实施例提供一种晶体管的制作方法， 包括： 在基板上形成 第一源极和漏极金属层； 在所述第一源极和漏极金属层上形成绝缘层； 所述 绝缘层包含第一绝缘区域和第二绝缘区域， 所述第一绝缘区域和第二绝缘区 域相对于第一源极和漏极金属层中心线相对设置且其间具有一空白区域； 在 所述绝缘层上形成栅极金属层； 所述栅极金属层包含第一栅极区域和第二栅 极区域， 且所述第一栅极区域覆盖所述第一绝缘区域， 所述第二栅极区域覆 盖所述第二绝缘区域； 在所述栅极金属层上形成栅极绝缘层； 在所述栅极绝 缘层上形成半导体层； 所述半导体层的正投影区域覆盖所述第一源极和漏极 金属层； 在所述半导体层上形成刻蚀阻挡层； 所述刻蚀阻挡层的正投影区域 覆盖所述第一绝缘区域与所述第二绝缘区域之间的空白区域； 在所述刻蚀阻 挡层上形成第二源极和漏极金属层； 所述第二源极和漏极金属层包括源极区 域和漏极区域； 所述源极区域形成的正投影区域覆盖所述半导体层与所述第 一栅极区域的重叠部分； 所述漏极区域形成的正投影区域覆盖半导体层与第 二栅极区域的重叠部分； 以及
在所述第二源极和漏极金属层上形成绝缘层。
本发明的另一个实施例提供一种晶体管， 包括： 基板以及位于所述基板 上的第一源极和漏极金属层； 覆盖部分所述第一源极和漏极金属层的第一绝 缘区域和第二绝缘区域， 所述第一绝缘区域和第二绝缘区域相对于第一源极 和漏极金属层中心线相对设置且其间具有一空白区域； 覆盖所述第一绝缘区 域的第一栅极区域以及覆盖所述第二绝缘区域的第二栅极区域； 覆盖所述第 一栅极区域、 所述第二栅极区域的栅极绝缘层； 位于所述栅极绝缘层上的半 导体层， 且所述半导体层的正投影区域覆盖所述第一源极和漏极金属层； 位 于所述半导体层上的刻蚀阻挡层， 且所述刻蚀阻挡层的正投影区域覆盖所述 空白区域； 分别位于所述刻蚀阻挡层上的源极区域和漏极区域； 所述源极区 域形成的正投影区域覆盖所述半导体层与所述第一栅极区域的重叠部分； 所 述漏极区域形成的所述正投影区域覆盖所述半导体层与所述第二栅极区域的 重叠部分； 以及覆盖所述源极区域、 所述漏极区域、 所述栅极绝缘层以及所 述刻蚀阻挡层的绝缘层。
本发明的再一个实施例提供一种阵列基板， 所述阵列基板包括上述晶体 管。
本发明的又一个实施例提供一种显示装置， 所述显示装置包括上述阵列 基板。
釆用本发明实施例提供的晶体管制作方法， 可获得两个共用同一个第一 源极和漏极金属层的 OTFT;如图 2H所示，左侧的 OTFT由下至上的结构为： 第一源极和漏极金属层、 第一绝缘区域、 第一栅极区域、 栅极绝缘层、 半导 体层、 刻蚀阻挡层以及源极区域； 右侧 OTFT由下至上的结构为： 第一源极 和漏极金属层、 第二绝缘区域、 第二栅极区域、 栅极绝缘层、 半导体层、 刻 蚀阻挡层以及源极区域； 可见， 使用该方法形成的两个 OTFT共用一个第一 源极和漏极金属层， 该第一源极和漏极金属层可在其中一个 OTFT中作为源 极金属层， 在另一个 OTFT中作为漏极金属层， 并且每一个 OTFT都有自己 的栅极； 并且这两个 OTFT的源极、 栅极以及漏极分别形成在垂直方向上， 因此， 通过本方法形成的具有垂直结构的双栅 OTFT, 可大大减少现有技术 中双底栅结构的晶体管在像素区域所占的面积， 可提高阵列基板的开口率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。 图 1 A为现有技术中制作晶体管的过程中形成第一结构的结构示意图； 图 1B为现有技术中制作晶体管的过程中形成第二结构的结构示意图； 图 1C为现有技术中制作晶体管的过程中形成第三结构的结构示意图； 图 1D为现有技术中制作晶体管的过程中形成第四结构的结构示意图； 图 1E为现有技术中制作晶体管的过程中形成第五结构的结构示意图； 图 1F为现有技术中制作晶体管的过程中形成第六结构的结构示意图； 图 2A为本发明实施例提供的晶体管的金属层的结构示意图；
图 2B为本发明实施例提供的晶体管的第一结构示意图；
图 2C为本发明实施例提供的晶体管的第二结构示意图；
图 2D为本发明实施例提供的晶体管的第三结构示意图；
图 2E为本发明实施例提供的晶体管的第四结构示意图；
图 2F为本发明实施例提供的晶体管的第五结构示意图；
图 2G为本发明实施例提供的晶体管的第六结构示意图；
图 2H为本发明实施例提供的晶体管的第七结构示意图；
图 3是本发明实施例提供的另外一种晶体管结构图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
釆用本发明实施例提供的晶体管制作方法， 可获得两个共用同一个第一 源极和漏极金属层的 OTFT;如图 2H所示，左侧的 OTFT由下至上的结构为： 第一源极和漏极金属层、 第一绝缘区域、 第一栅极区域、 栅极绝缘层、 半导 体层、 刻蚀阻挡层以及源极区域； 右侧 OTFT由下至上的结构为： 第一源极 和漏极金属层、 第二绝缘区域、 第二栅极区域、 栅极绝缘层、 半导体层、 刻 蚀阻挡层以及源极区域； 可见， 使用该方法形成的两个 OTFT共用一个第一 源极和漏极金属层， 该第一源极和漏极金属层可在其中一个 OTFT中作为源 极金属层， 在另一个 OTFT中作为漏极金属层， 并且每一个 OTFT都有自己 的栅极； 并且这两个 OTFT的源极、 栅极以及漏极分别形成在垂直方向上， 因此， 通过本发法形成的具有垂直结构的双栅 OTFT, 可大大减少现有技术 中双底栅结构的晶体管在像素区域所占的面积， 可提高阵列基板的开口率。 供的附图中。 根据本发明实施例的制造方法包括如下步骤：
步骤 21 , 在基板上形成第一源极和漏极金属层；
步骤 22, 在所述第一源极和漏极金属层上形成绝缘层； 所述绝缘层包含 第一绝缘区域和第二绝缘区域， 且所述第一绝缘区域部分覆盖所述第一源极 和漏极金属层的一侧； 所述第二绝缘区域部分覆盖所述第一源极和漏极金属 层的另一侧； 所述第一绝缘区域和所述第二绝缘区域的其余部分位于所述基 板上；
步骤 23 , 在所述绝缘层上形成栅极金属层； 所述栅极金属层包含第一栅 极区域和第二栅极区域， 且所述第一栅极区域覆盖所述第一绝缘区域， 所述 第二栅极区域覆盖所述第二绝缘区域；
步骤 24, 在所述栅极金属层上形成栅极绝缘层；
步骤 25 , 在所述栅极绝缘层上形成半导体层； 所述半导体层的正投影区 域覆盖所述第一源极和漏极金属层；
步骤 26, 在所述半导体层上形成刻蚀阻挡层； 所述刻蚀阻挡层的正投影 区域覆盖所述第一绝缘区域与所述第二绝缘区域之间的空白区域；
步骤 27 , 在所述刻蚀阻挡层上形成第二源极和漏极金属层； 所述第二源 极和漏极金属层包括源极区域和漏极区域的第二源极和漏极金属层； 所述源 极区域形成的正投影区域覆盖所述半导体层与所述第一栅极区域的重叠部 分； 所述漏极区域形成的正投影区域覆盖半导体层与第二栅极区域的重叠部 分；
步骤 28, 在所述第二源极和漏极金属层上形成绝缘层。
例如， 在所述栅极金属层上形成栅极绝缘层包括但不限于以下方法： 在所述栅极金属层上化学气相沉积氮化硅系或氧化硅系， 形成栅极绝缘 层。
例如， 在形成所述栅极绝缘层后， 可以保留对应于所述第一绝缘区域和 所述第二绝缘区域之间的空白区域的部分， 也可以蚀刻掉所述空白区域的栅 极绝缘层。
例如， 在所述栅极绝缘层上形成半导体层包括但不限于以下方法： 在所述栅极绝缘层上溅射铟镓辞氧化物， 刻蚀后形成半导体层。
例如， 在所述第二源极和漏极金属层上形成绝缘层包括但不限于以下方 法：
在所述第二源极和漏极金属层上化学气相沉积绝缘材料， 形成绝缘层。 釆用本发明实施例提供的方法， 两个 OTFT可共用一个第一源极和漏极 金属层； 即该第一源极和漏极金属层在其中一个 OTFT中可作为源极， 在另 一个 OTFT中可作为漏极， 可见， 该结构可以减小现有技术中的源 /漏极所占 面积；
釆用本发明实施例提供的方法， 每个 OTFT的栅极、 源极以及漏极位于 垂直方向上， 与现有技术中的 OTFT结构相比， 减小了 OTFT所占面积， 因 此， 可提高阵列基板的开口率。
以下以具体实施例进行介绍：
实施例：
如图 2A-图 2H所示， 本发明实施例提供一种晶体管的制作方法， 通过 该制作方法可得到共用同一源 /漏极金属层的、 具有垂直结构的双栅 OTFT, 因此可大大减少 OTFT所占面积， 提高阵列基板的开口率， 具体如下：
步骤一， 如图 2A所示， 在基板上形成第一源极和漏极金属层 31 ;
例如， 可通过在基板上溅射一层金属， 刻蚀后形成第一源极和漏极金属 层 31 ;
在一个示例中， 本第一源极和漏极金属层 31可以使用钼、 钼 /铝 /钼等金 属。
例如， 当该第一源 /漏金属层作为其中一个 OTFT的源极时， 则作为另一 个 OTFT的漏极。
步骤二， 如图 2B所示， 在第一源极和漏极金属层 31上形成包含第一绝 缘区域 32和第二绝缘区域 33的绝缘层，且第一绝缘区域 32部分覆盖第一源 极和漏极金属层 31的一侧； 第二绝缘区域 33部分覆盖第一源极和漏极金属 层 31的另一侧；第一绝缘区域 32和第二绝缘区域 33的其余部分位于所述基 板上； 例如，可通过在第一源极和漏极金属层 31上悬涂一层绝缘材料，刻蚀后 形成绝缘层。
例如， 形成的第一绝缘区域 32与第二绝缘区域 33之间存在空白区域。 例如， 第一绝缘区域 32和第二绝缘区域 33相对于第一源极和漏极金属 层中心线相对设置， 在所述中心线两侧均覆盖部分所述第一源极和漏极金属 层， 且在所述空白区域露出所述第一源极和漏极金属层。
在一个示例中， 为了简化制作过程中的工艺复杂度， 使用的绝缘材料可 以是具有光感性的树脂材料， 例如 PDI1000 , 此时， 可以使用光刻蚀工艺 ( hoto ) 。
步骤三， 如图 2C所示， 在绝缘层上形成包含第一栅极区域 34和第二栅 极区域 35的栅极金属层， 且第一栅极区域 34覆盖第一绝缘区域 32 , 第二栅 极区域 35覆盖第二绝缘区域 33;
例如， 可通过在绝缘层上溅射金属， 刻蚀后形成栅极金属层。
例如， 第一栅极区域 34和第二栅极区域 35之间也具有对应于第一绝缘 区域 32和第二绝缘区域 33之间的空白区域的间隔。
在一个示例中， 本步骤使用的金属为钼、 钼 /铝 /钼等金属。
步骤四， 如图 2D所示， 在栅极金属层上形成栅极绝缘层 36, 利用干刻 技术将所述空白区域（即图中的 U形结构底部） 的栅极绝缘层刻蚀；
例如，可通过在栅极金属层上化学气相沉积氮化硅系或氧化硅系化合物， 形成栅极绝缘层 36。 在该实施例中， 对应于所述空白区域的栅极绝缘层被刻 蚀掉， 但本发明的实施例不限于此。 在根据本发明的其他实施例中， 也可以 保留对应于所述空白区域的栅极绝缘层。
步骤五， 在栅极绝缘层 36上形成半导体层 37, 如图 2E所示； 该半导体 层 37形成的正投影区域覆盖第一源极和漏极金属层 31 ;
例如，可通过在栅极绝缘层 36上溅射铟镓辞氧化物 (Indium Gallium Zinc
Oxide, IGZO), 刻蚀后形成半导体层 37。
步骤六， 在半导体层 37上形成刻蚀阻挡层 38, 如图 2F所示； 该刻蚀阻 挡层 38形成的正投影区域覆盖第一绝缘区域 32与第二绝缘区域 33之间的空 白区域；
例如，可通过在半导体层 37上溅射无机非金属材料，刻蚀后形成刻蚀阻 步骤七， 在刻蚀阻挡层 38上形成包括源极区域 39和漏极区域 310的第 二源极和漏极金属层， 如图 2G所示； 其中源极区域 39形成的正投影区域覆 盖半导体层 37与第一栅极区域 34的重叠部分； 漏极区域 310形成的正投影 区域覆盖半导体层 37与第二栅极区域 35的重叠部分；
例如，可通过在刻蚀阻挡层 38上溅射金属，刻蚀后形成第二源极和漏极 金属层；
在一个示例中， 本步骤使用的金属为钼、 钼 /铝 /钼等。
步骤八， 在第二源极和漏极金属层上形成绝缘层 311 , 如图 2H所示。 例如， 可通过在第二源极和漏极金属层上化学气相沉积绝缘材料， 形成 绝缘层 311。
在一个示例中， 本步骤中使用的绝缘材料可以为 SiOx。
例如， 空白区域位于第一源极和漏极金属层 31的中间位置， 即第一绝缘 区域 32在第一源极和漏极金属层 31上形成的正投影区域的形状与所述第二 绝缘区域 33在第一源极和漏极金属层 31上形成的正投影区域的形状相同； 第一绝缘区域 32在第一源极和漏极金属层 31上形成的正投影区域的面积与 第二绝缘区域 33在第一源极和漏极金属层 31上形成的正投影区域的面积相 等。
例如，第一栅极区域 34在基板上产生的正投影区域的形状与第二栅极区 域 35在基板上产生的正投影区域的形状相同； 第一栅极区域 34在基板上产 生的正投影区域的面积与第二栅极区域 35 在基板上产生的正投影区域的面 积相等。
例如， 源极区域 39 在基板上产生的正投影区域的形状与漏极区域 310 在基板上产生的正投影区域的形状相同；源极区域 39在基板上产生的正投影 区域的面积与漏极区域 310在基板上产生的正投影区域的面积相等。
根据上述步骤可获得具有垂直结构的双栅 OTFT,如图 2H所示，以空白 区域为分界线， 左右两侧分别包括一个具有垂直结构的 OTFT; 其左侧从下 至上形成的 OTFT 的结构包括： 第一源极和漏极金属层 31、 第一绝缘区域 32、 第一栅极区域 34、 栅极绝缘层 36、 半导体层 37、 刻蚀阻挡层 38、 以及 源极区域 39; 其右侧从下至上形成的 OTFT的结构包括： 第一源极和漏极金 属层 31、第二绝缘区域 33、第二栅极区域 35、栅极绝缘层 36、半导体层 37、 刻蚀阻挡层 38、 以及漏极区域 310。
例如， 当第一源极和漏极金属层 31在左侧的 OTFT中实现源极的功能 时， 源极区域 39应当实现漏极功能； 当第一源极和漏极金属层 31在右侧的 OTFT中实现漏极的功能时， 漏极区域 310应当实现源极功能。
例如， 当第一源极和漏极金属层 31的宽度为 4微米， 长度为 2微米， 空 白区域的宽度为 3.8μπι, 长度为 2μπι, 则以左侧的 OTFT为例， 第一源极和 漏极金属层 31与源极区域 39在垂直方向上的重叠区域的宽度为 Ο.ΐμπι, 此 时电场强度比较大， 可较好的满足电学性能的要求， 因此可获得较好的开关 效果。
在一个示例中， 源极区域 39与漏极区域 310的宽度可分别为 4微米， 空 白区域的宽度为 3.8μπι, 此时形成的具有垂直结构的双栅 OTFT的宽度小于 12微米， 远远小于现有技术中的 40微米。
如图 2H所示， 本发明是实施例提供一种晶体管， 所述晶体管包括： 部分覆盖第一源极和漏极金属层一侧的第一绝缘区域； 部分覆盖所述第 一源极和漏极金属层另一侧的第二绝缘区域； 且所述第一绝缘区域和所述第 二绝缘区域的其余部分位于所述基板上；
覆盖所述第一绝缘区域的第一栅极区域； 覆盖所述第二绝缘区域的第二 栅极区域；
覆盖所述第一栅极区域、 所述第二栅极区域的栅极绝缘层；
位于所述栅极绝缘层上的半导体层， 且所述半导体层的正投影区域覆盖 所述第一源极和漏极金属层；
位于所述半导体层上的刻蚀阻挡层 , 且所述刻蚀阻挡层的正投影区域覆 盖所述空白区域；
分别位于所述刻蚀阻挡层上的源极区域和漏极区域； 所述源极区域形成 的正投影区域覆盖所述半导体层与所述第一栅极区域的重叠部分； 所述漏极 区域形成的所述正投影区域覆盖所述半导体层与所述第二栅极区域的重叠部 分；
覆盖所述源极区域、 所述漏极区域、 所述栅极绝缘层以及所述刻蚀阻挡 层的绝缘层。 在一个示例中， 第一绝缘区域与所述第二绝缘区域在所述第一源极和漏 极金属层上产生的正投影区域的形状相同、 面积相等。
在一个示例中， 所述第一栅极区域与所述第二栅极区域在所述基板上产 生的正投影区域的形状相同、 面积相等。
在一个示例中， 所述源极区域与所述漏极区域在所述基板上产生的正投 影区域的形状相同、 面积相等。
在一个示例中， 所述第一栅极区域与所述第二栅极区域在所述第一源极 和漏极金属层上形成的正投影区域的宽度值为 0.1微米。
本发明实施例还提供一种阵列基板， 该阵列基板包括上述晶体管。
本发明实施例还提供一种显示装置， 该显示装置包括上述阵列基板。 综上所述， 有益效果：
釆用本发明实施例提供的晶体管制作方法， 可获得两个共用同一个第一 源极和漏极金属层的 OTFT;如图 2H所示，左侧的 OTFT由下至上的结构为： 第一源极和漏极金属层、 第一绝缘区域、 第一栅极区域、 栅极绝缘层、 半导 体层、 刻蚀阻挡层以及源极区域； 右侧 OTFT由下至上的结构为： 第一源极 和漏极金属层、 第二绝缘区域、 第二栅极区域、 栅极绝缘层、 半导体层、 刻 蚀阻挡层以及源极区域； 可见， 使用该方法形成的两个 OTFT共用一个第一 源极和漏极金属层， 该第一源极和漏极金属层可在其中一个 OTFT中作为源 极金属层， 在另一个 OTFT中作为漏极金属层， 并且每一个 OTFT都有自己 的栅极； 并且这两个 OTFT的源极、栅极以及漏极形成在垂直方向上， 因此， 通过本发法形成的具有垂直结构的双栅 OTFT, 可大大减少现有技术中双底 栅结构的晶体管在像素区域所占的面积， 可提高阵列基板的开口率。
在一个示例中， 本发明实施例提供的晶体管的源极区域与漏极区域的宽 度可分别为 4微米， 空白区域的宽度为 3.8μπι, 此时形成的具有垂直结构的 双栅 OTFT的宽度小于 12微米， 远远小于现有技术中的 40微米。
需要说明的是，根据上述的实施例，在栅极金属层上形成栅极绝缘层 36, 使所述空白区域（即图中的 U形结构底部）的栅极绝缘层被刻蚀。 然而， 栅 极绝缘层也可以覆盖所述第一绝缘区域和第二绝缘区域的空白区域， 具体结 构如图 3所示。 图 3是本发明实施例提供的另外一种晶体管结构图。 由于栅 极绝缘层的厚度较薄， 此时半导体层能够击穿该栅极绝缘层与第一源极、 漏 极金属层连通， 能够实现该 TFT的功能。
本发明的实施例并不局限于 OTFT中， 也可以是其他的 TFT, 如 a-si、 低温多晶硅等。
尽管已描述了本发明的优选实施例， 但本领域内的技术人员一旦得知了 基本创造性概念， 则可对这些实施例作出另外的变更和修改。 所以， 所附权 利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种晶体管的制作方法， 包括：
在基板上形成第一源极和漏极金属层；
在所述第一源极和漏极金属层上形成绝缘层； 所述绝缘层包含第一绝缘 区域和第二绝缘区域， 所述第一绝缘区域和第二绝缘区域相对于第一源极和 漏极金属层的中心线相对设置且其间具有一空白区域；
在所述绝缘层上形成栅极金属层； 所述栅极金属层包含第一栅极区域和 第二栅极区域， 且所述第一栅极区域覆盖所述第一绝缘区域， 所述第二栅极 区域覆盖所述第二绝缘区域；
在所述栅极金属层上形成栅极绝缘层；
在所述栅极绝缘层上形成半导体层； 所述半导体层的正投影区域覆盖所 述第一源极和漏极金属层；
在所述半导体层上形成刻蚀阻挡层； 所述刻蚀阻挡层的正投影区域覆盖 所述第一绝缘区域与所述第二绝缘区域之间的空白区域；
在所述刻蚀阻挡层上形成第二源极和漏极金属层； 所述第二源极和漏极 金属层包括源极区域和漏极区域； 所述源极区域形成的正投影区域覆盖所述 半导体层与所述第一栅极区域的重叠部分； 所述漏极区域形成的正投影区域 覆盖半导体层与第二栅极区域的重叠部分； 以及
在所述第二源极和漏极金属层上形成绝缘层。
2、如权利要求 1所述的方法，还包括，在所述栅极金属层上形成栅极绝 缘层后且在形成所述半导体层之前，将所述空白区域的栅极绝缘层进行刻蚀。
3、如权利要求 1或 2所述的方法， 其中， 在所述栅极绝缘层上形成半导 体层包括：
在所述栅极绝缘层上溅射铟镓辞氧化物， 刻蚀后形成半导体层。
4、 如权利要求 1-3中任一项所述的方法， 其中， 在所述半导体层上形成 刻蚀阻挡层包括：
在所述半导体层上溅射无机非金属材料， 刻蚀后形成刻蚀阻挡层。
5、 如权利要求 1-4中任一项所述的方法， 其中， 在所述第二源极和漏极 金属层上形成绝缘层包括： 在所述第二源极和漏极金属层上化学气相沉积绝缘材料， 形成绝缘层。
6、 如权利要求 1-5中任一项所述的方法， 其中， 所述第一绝缘区域和所 述第二绝缘区域形成为在所述中心线两侧均覆盖部分所述第一源极和漏极金 属层， 且在所述空白区域露出所述第一源极和漏极金属层。
7、 一种晶体管， 包括：
基板以及位于所述基板上的第一源极和漏极金属层；
覆盖部分所述第一源极和漏极金属层的第一绝缘区域和第二绝缘区域， 所述第一绝缘区域和第二绝缘区域相对于第一源极和漏极金属层的中心线相 对设置且其间具有一空白区域；
覆盖所述第一绝缘区域的第一栅极区域以及覆盖所述第二绝缘区域的第 二栅极区域；
覆盖所述第一栅极区域、 所述第二栅极区域的栅极绝缘层；
位于所述栅极绝缘层上的半导体层， 且所述半导体层的正投影区域覆盖 所述第一源极和漏极金属层；
位于所述半导体层上的刻蚀阻挡层， 且所述刻蚀阻挡层的正投影区域覆 盖所述空白区域；
分别位于所述刻蚀阻挡层上的源极区域和漏极区域； 所述源极区域形成 的正投影区域覆盖所述半导体层与所述第一栅极区域的重叠部分； 所述漏极 区域形成的所述正投影区域覆盖所述半导体层与所述第二栅极区域的重叠部 分； 以及
覆盖所述源极区域、 所述漏极区域、 所述栅极绝缘层以及所述刻蚀阻挡 层的绝缘层。
8、根据权利要求 7所述的晶体管， 其中， 所述栅极绝缘层还覆盖所述空 白区域。
9、如权利要求 7或 8所述的晶体管， 其中 , 所述第一绝缘区域与所述第 二绝缘区域在所述第一源极和漏极金属层上产生的正投影区域的形状相同、 面积相等。
10、 如权利要求 7-9中任一项所述的晶体管， 其中， 所述第一栅极区域 与所述第二栅极区域在所述基板上产生的正投影区域的形状相同、面积相等。
11、 如权利要求 7-10中任一项所述的晶体管， 其中， 所述第一栅极区域 与所述第二栅极区域在所述第一源极和漏极金属层上形成的正投影区域的宽 度值为 0.1微米。
12、 如权利要求 7-11中任一项所述的晶体管， 其中， 所述第一绝缘区域 和所述第二绝缘区域在所述中心线两侧均覆盖部分所述第一源极和漏极金属 层， 且在所述空白区域露出所述第一源极和漏极金属层。
13、 一种阵列基板， 包括如权利要求 7-12中任一项所述的晶体管。
14、 一种显示装置， 包括如权利要求 13所述的阵列基板。
PCT/CN2012/085476 2012-03-30 2012-11-28 晶体管的制作方法、晶体管、阵列基板以及显示装置 WO2013143311A1 (zh)

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CN104317126B (zh) * 2014-11-13 2017-02-01 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
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US8889444B2 (en) 2014-11-18
CN102683193A (zh) 2012-09-19
KR20130120456A (ko) 2013-11-04
US20140054701A1 (en) 2014-02-27
KR101467711B1 (ko) 2014-12-01
EP2667404B1 (en) 2019-04-24
JP2015517206A (ja) 2015-06-18
CN102683193B (zh) 2014-07-23

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