WO2017166167A1 - 场效应管及其制造方法 - Google Patents

场效应管及其制造方法 Download PDF

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Publication number
WO2017166167A1
WO2017166167A1 PCT/CN2016/077991 CN2016077991W WO2017166167A1 WO 2017166167 A1 WO2017166167 A1 WO 2017166167A1 CN 2016077991 W CN2016077991 W CN 2016077991W WO 2017166167 A1 WO2017166167 A1 WO 2017166167A1
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Prior art keywords
layer
insulating layer
gate insulating
source
gate structure
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PCT/CN2016/077991
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English (en)
French (fr)
Inventor
秦旭东
徐慧龙
张臣雄
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2016/077991 priority Critical patent/WO2017166167A1/zh
Priority to EP16895948.4A priority patent/EP3410492B1/en
Priority to CN201680059335.8A priority patent/CN108463889B/zh
Priority to TW106102942A priority patent/TWI622173B/zh
Publication of WO2017166167A1 publication Critical patent/WO2017166167A1/zh
Priority to US16/119,415 priority patent/US10600917B2/en

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Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a field effect transistor and a method of fabricating the same.
  • the field effect transistor is a common electronic component.
  • a silicon-based semiconductor material is generally used to prepare a field effect transistor.
  • a two-dimensional material such as graphene may be used instead of the silicon-based semiconductor material.
  • a field effect transistor based on a graphene material is prepared. Because the graphene material has the advantages of two-dimensional characteristics, high mobility, high saturation speed, etc., the above-mentioned FET-based FET can have better frequency characteristics than the conventional silicon-based FET, for example, Higher cutoff frequency.
  • embodiments of the present invention provide a field effect transistor and a method of fabricating the same.
  • the technical solution is as follows.
  • a field effect transistor comprising:
  • a substrate layer 101 having a first gate structure 1032A and a recess in the upper surface of the substrate layer 101 a second gate structure 1032B;
  • a bottom gate insulating layer 1022 covering the upper surface of the substrate layer 101;
  • top gate insulating layer 1021 covering the upper surface of the channel layer 106
  • the lower surface of the top gate insulating layer 1021 is provided with: the first source 1041, the second source 1042, and a drain 105 disposed between the first source 1041 and the second source 1042.
  • the top surface of the top gate insulating layer 1021 is provided with a third gate structure 1031C and a fourth gate structure 1031D;
  • the third gate structure 1031C is disposed in the first projection region of the first gate structure 1032A on the top gate insulating layer 1021, and the first projection region is located at the first source 1041 and the drain Between poles 105;
  • the fourth gate structure 1031D is disposed in the second projection region of the second gate structure 1032B on the top gate insulating layer 1021, and the second projection region is located in the second source 1042 and the drain Between the poles 105.
  • the two edges of the first projection area respectively coincide with the edge of the first source 1041 and the edge of the drain 105, and the second projection area The two edges coincide with the edge of the second source 1042 and the edge of the drain 105, respectively.
  • an area of the third gate structure 1031C is less than or equal to an area of the first projection area
  • the area of the fourth gate structure 1031D is less than or equal to the area of the second projection area.
  • the third gate structure 1031C and the fourth gate structure 1031D are parallel to each other; or
  • the third gate structure 1031C and the fourth gate structure 1031D are a gate-frame connected structure.
  • the first gate structure 1032A and the third gate structure 1031C are connected through a contact hole, and the second gate structure 1032B and the fourth gate structure 1031D Connected through contact holes.
  • the channel layer is one of graphene, molybdenum disulfide, or black phosphorus or other two-dimensional materials.
  • a field effect transistor comprising:
  • a first gate structure 4032A and a first bottom gate insulating layer 4022A overlying the first gate structure 4032A are disposed in the first recess of the upper surface of the substrate layer 401.
  • a first channel layer 4061 covering the first bottom gate insulating layer 4022A and having a groove shape
  • a second channel layer 4062 covering the second bottom gate insulating layer 4022B and having a groove shape
  • the bottom surface of the recess formed by the first channel layer 4061 is provided with a first top gate insulating layer 4021C and a third gate structure 4031A overlying the first top gate insulating layer 4021C;
  • the bottom surface of the recess formed by the second channel layer 4062 is provided with a second top gate insulating layer 4021D and a fourth gate structure 4031B covering the second top gate insulating layer 4021D;
  • a source 405 disposed in the recess structure formed by the substrate layer 401, the first outer surface of the first channel layer 4061, and the first outer surface of the second channel layer 4062;
  • a first source 4041 overlying the substrate layer 401 and in contact with the second outer surface of the first channel layer 4061;
  • a first source 4042 overlying the substrate layer 401 and in contact with the second outer surface of the second channel layer 4062.
  • the channel layer is made of one of graphene, molybdenum disulfide, or black phosphorus or other two-dimensional materials.
  • a method of fabricating a field effect transistor comprising:
  • the bottom gate electrode including a first gate structure and a second gate structure
  • the source comprising a first source and a second source
  • a top gate electrode is formed over the top gate insulating layer, the top gate electrode including a third gate structure and a fourth gate structure.
  • the forming the bottom gate electrode on the substrate layer comprises:
  • a first gate structure of the bottom gate electrode and a second gate structure of the bottom gate electrode are formed in the two recess structures, respectively.
  • the method before the forming the bottom gate insulating layer, the method further includes:
  • the surface of the substrate layer forming the bottom gate electrode is processed by a chemical mechanical polishing method.
  • the forming the top gate electrode over the top gate insulating layer comprises:
  • a vertical contact hole is formed between the top gate electrode and the bottom gate electrode such that the top gate electrode is connected to the bottom gate electrode.
  • a method of fabricating a field effect transistor comprising:
  • the sacrificial layer is etched away.
  • the attaching the channel layer comprises:
  • the channel layer is deposited in situ such that the channel layer is folded into the first recess structure and the second recess structure over the first bottom gate insulating layer and the second bottom gate insulating layer.
  • the forming the third gate structure of the top gate electrode and the fourth gate structure of the top gate electrode include:
  • a vertical contact hole is formed between the top gate electrode and the bottom gate electrode such that the top gate electrode is connected to the bottom gate electrode.
  • the field effect transistor provided by the invention comprises two top gate electrodes and two bottom gate electrodes, the top gate electrode and the bottom gate electrode being opposite to each other, so that the field effect transistor increases the number of carriers induced by the control voltage. Further increasing the output current of the FET, increasing the power gain limit frequency at the time of high frequency use, and making the electric field between the top gate electrode and the bottom gate electrode more fully cover the source and the drain The channel layer between them further reduces the parasitic effect at high frequencies, further improving the frequency characteristics of the field effect transistor.
  • FIG. 1 is a schematic vertical sectional view of a field effect transistor according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic view showing a projection area in a vertical section structure of a field effect transistor according to Embodiment 1 of the present invention
  • Figure 3 is a cross-sectional view of a field effect transistor according to Embodiment 1 of the present invention taken along the line AA' in Figure 2;
  • FIG. 4 is a schematic structural view of a vertical cut surface of a field effect transistor according to Embodiment 2 of the present invention.
  • FIG. 5 is a flow chart of a method for manufacturing a field effect transistor according to Embodiment 3 of the present invention.
  • FIG. 6 is a schematic structural view of a field effect transistor to be manufactured when each step is completed in a method for fabricating a field effect transistor according to Embodiment 3 of the present invention
  • FIG. 7 is a flow chart of a method for manufacturing a field effect transistor according to Embodiment 4 of the present invention.
  • FIG. 8 is a schematic structural view of a field effect transistor to be manufactured when each step is completed in a method for fabricating a field effect transistor according to Embodiment 4 of the present invention.
  • FIG. 1 is a schematic diagram showing the vertical section structure of a field effect transistor according to Embodiment 1 of the present invention. As shown in the figure, the field effect transistor includes:
  • a substrate layer 101 the upper surface of the substrate layer 101 is provided with a first gate structure 1032A and a second gate structure 1032B;
  • a bottom gate insulating layer 1022 covering the upper surface of the substrate layer 101, the bottom gate insulating layer 1022 being used to make a gap between the first gate structure 1032A and the second gate structure 1032B as the bottom gate electrode and the channel layer 106 Disconnected state.
  • top gate insulating layer 1021 covering the upper surface of the channel layer 106
  • the lower surface of the top gate insulating layer 1021 is provided with: the first source 1041, the second source 1042, and a drain 105 disposed between the first source 1041 and the second source 1042.
  • the channel layer 106 is in contact with the first source 1041, the second source 1042, and the drain 105 such that when a control voltage is applied through the gate electrode 103, based on the channel layer 106, the source A conductive channel is formed between the pole 104 and the drain 105.
  • a third gate structure 1031C and a fourth gate structure 1031D are disposed in the upper surface recess of the top gate insulating layer 1021, and the top gate insulating layer 1021 is configured to make the third gate structure 1031C and the fourth gate structure 1031D
  • the channel layer 106 is in an open state
  • the third gate structure 1031C is disposed in the first projection region of the first gate structure 1032A on the top gate insulating layer 1021, and the first projection region is located at the first source 1041 and the drain Between poles 105;
  • the fourth gate structure 1031D is disposed in the second projection region of the second gate structure 1032B on the top gate insulating layer 1021, and the second projection region is located in the second source 1042 and the drain Between the poles 105.
  • the structure provided by the embodiment of the present invention includes a third gate structure 1031C as a top gate electrode and a first gate structure 1032A and a second gate structure 1032B of a fourth gate structure and a bottom gate electrode.
  • the drain 105 is disposed between the first source 1041 and the second source 1042, such that the first source 1041 and the drain 105 and the second source 1042 and the drain 105 are respectively
  • a conductive channel is formed to provide a dual conductive channel structure that further increases the output current of the field effect transistor and increases the power gain limit frequency when additionally used at high frequencies.
  • the first gate structure 1032A corresponds to the third gate structure 1031C for applying a control voltage to a conductive channel
  • the second gate structure 1032B corresponds to the fourth gate structure 1031D for applying a control voltage to another conductive channel.
  • the two conductive layers are respectively formed.
  • the gate electrode, the gate insulating layer and the source of the channel may have the same shape and size, and may have different shapes and sizes as needed. The specific shape and size of any of the above structures are not limited in the present invention.
  • the voltages at which the first source 1041 and the second source 1042 and the drain 105 as the source are connected may be interchanged, and thus the first source 1041 and the second source 1042. It can be set as a drain, and the drain 105 can be set as a source. The present invention does not specifically limit whether the source and the drain are interchanged.
  • an electric field between the top gate electrode 1031 and the bottom gate electrode 1032 can sufficiently cover the channel layer 106 between the first source 1041, the second source 1042, and the drain 105.
  • the parasitic effect of the FET at a high frequency such as parasitic resistance, parasitic capacitance, etc., is reduced, thereby improving the frequency characteristics of the FET.
  • the third gate structure 1031C is disposed on The first gate structure 1032A is located in the first projection region 201 of the top gate insulating layer 1021.
  • the first projection region 201 is located between the first source 1041 and the drain 105.
  • the third gate structure 1031C is The first gate structure 1032A is sequentially disposed between the top gate insulating layer 1021, the channel layer 106, and the bottom gate insulating layer 1022.
  • the top gate insulating layer 1021 and the bottom gate insulating layer 1022 are collectively referred to as a gate insulating layer 102, and the top gate electrode 1031 and the bottom gate electrode 1032 are collectively referred to as a gate electrode 103.
  • the fourth gate structure 1031D is disposed in the second projection region 202 of the second gate structure 1032B on the top gate insulating layer 1021, and the second projection region 202 is located at the second source 1042 and the drain 105.
  • the fourth gate structure 1031D and the second gate structure 1032B are sequentially disposed between the top gate insulating layer 1021, the channel layer 106, and the bottom gate insulating layer 1022.
  • the electric field between the top gate electrode and the bottom gate electrode can more fully cover the channel layer 106 between the first source 1041, the second source 1042 and the drain 105, thereby further
  • the two edges 2011 of the first projection area 201 and the edge of the first source 1041 and the edge of the drain 105 respectively.
  • the two edges 2021 of the second projection area 202 coincide with the edge of the second source 1042 and the edge of the drain 105, respectively.
  • the area of the third gate structure 1031C is less than or equal to The area of the first projection area 201
  • the area of the fourth gate structure 1031D is less than or equal to the area of the second projection area 202.
  • 3 is a cross-sectional view taken along line AA' of FIG. 2. As shown in FIG. 3, the area of the first projection area 201 and the first projection area 202 means that any of the projection areas is in a plane parallel to the substrate layer 101. The area occupied.
  • the third gate structure 1031C and the fourth gate structure 1031D are parallel to each other.
  • the third gate structure 1031C and the fourth gate structure 1031D are a gate-frame-shaped communication structure, that is, the top gate electrode includes two portions parallel to each other and is used for connecting the gate structure.
  • the mutually parallel portions may each have a rectangular structure. It should be noted that the shape of any of the above-mentioned gate structures may be set according to actual application conditions, which is not limited by the present invention.
  • the substrate layer 101 has a recess structure in which the bottom gate electrode 1032 is disposed.
  • the substrate layer 101 has two mutually parallel groove structures, and the first gate structure 1032A and the second gate structure 1032B of the bottom gate electrode 1032 are respectively disposed on the two mutually parallel groove structures.
  • the top gate electrode and the bottom gate electrode are connected through a contact hole, that is, the first gate structure 1032A and the third gate structure.
  • the 1031C is connected through a contact hole
  • the second gate structure 1032B is connected to the fourth gate structure 1031D through a contact hole.
  • the specific position of the contact hole can be selected according to the actual situation of the circuit wiring, which is not limited by the present invention.
  • the FET includes:
  • a first gate structure 4032A and a first bottom gate insulating layer 4022A overlying the first gate structure 4032A are disposed in the first recess of the upper surface of the substrate layer 401.
  • the second gate structure 4032B of the second recess of the surface and the second bottom gate insulating layer 4022B are covered to facilitate fabrication.
  • a first channel layer 4061 covering the first bottom gate insulating layer 4022A and having a groove shape
  • a second channel layer 4062 covering the second bottom gate insulating layer 4022B and having a groove shape
  • the bottom surface of the groove formed by the first channel layer 4061 is provided with a first top gate insulating layer 4021C and a third gate structure 4031C covering the first top gate insulating layer 4021C;
  • the bottom surface of the recess formed by the second channel layer 4062 is provided with a second top gate insulating layer 4021D and a fourth gate structure 4031D overlying the second top gate insulating layer 4021D. It is based on the soft mechanical properties of graphene and is easy to manufacture.
  • a source 405 disposed in the recess structure formed by the substrate layer 401, the first outer surface of the first channel layer 4061, and the first outer surface of the second channel layer 4062;
  • a first source 4041 overlying the substrate layer 401 and in contact with the second outer surface of the first channel layer 4061;
  • a first source 4042 overlying the substrate layer 401 and in contact with the second outer surface of the second channel layer 4062.
  • the first channel layer 4061 is in contact with the first source 4041 and the drain 405 for forming a conductive channel between the first source 4041 and the drain 405.
  • the second channel layer 4062 is formed. Contacting the second source 4042 and the drain 405 for forming a conductive channel between the second source 4042 and the drain 405, so that when the control voltage is applied, the top gate electrode and the bottom can be made The electric field between the gate electrodes completely covers the channel layer between the source and the drain, thereby further reducing parasitic effects at high frequencies.
  • first top gate insulating layer 4021C and the second top gate insulating layer 4021D may or may not be connected, and the first bottom gate insulating layer 4022A and the second bottom gate insulating layer 4022B may be connected.
  • the invention may or may not be connected, and the present invention does not specifically limit this.
  • Embodiment 5 is a flow chart of a method for fabricating a field effect transistor according to Embodiment 3 of the present invention.
  • the method is used to manufacture the field effect transistor provided in Embodiment 1, and the channel material is graphene as an example, including the following. step.
  • a substrate layer is provided.
  • the material of the substrate layer may be silicon dioxide (SiO 2 ), silicon carbide (SiC), boron nitride (BN), silicon nitride (Si 3 N 4 ), polyethylene terephthalate. Insulating materials such as diester (PET) and sapphire, the material of the substrate layer is not specifically limited in the present invention.
  • a bottom gate electrode is formed on the substrate layer, and the bottom gate electrode includes a first gate structure and a second gate structure. Specifically, two recess structures are formed on the substrate layer by photolithography and etching and coating processes, and a first gate structure of the bottom gate electrode and a bottom gate electrode are respectively formed in the two recess structures.
  • the second gate structure In practical applications, the material of the bottom gate electrode may be a metal material such as copper, platinum or gold. The material of the bottom gate electrode of the present invention is not limited.
  • the lithography process may be selected as a general lithography process or an electron beam exposure lithography process according to the size characteristics of the FET to be fabricated, which is not limited in the present invention.
  • the etching process includes plasma etching, etc.
  • the coating process includes a sputtering coating process, an evaporation coating process, and the like, and the specific process of forming the bottom gate electrode is not limited.
  • a bottom gate insulating layer is formed on the bottom gate electrode.
  • the surface of the substrate layer forming the bottom gate electrode is treated by a chemical mechanical polishing method before the step, so that the surface is kept flat.
  • the material of the bottom gate insulating layer may be SiO 2 , Al 2 O 3 or the like, which is not limited in the present invention.
  • the specific process for forming the bottom gate insulating layer may be chemical vapor deposition, atomic layer deposition, or the like, which is not limited in the present invention.
  • a graphene layer is attached on the bottom gate insulating layer.
  • the source includes a first source and a second source
  • the drain is disposed on the first source and Between the second sources.
  • the specific formation process includes: defining a source and a drain region by a photolithography process on the graphene layer, and then passing the coating The process forms a source and a drain.
  • the source and drain materials may be metals such as copper, platinum, gold, and the like.
  • a top gate insulating layer is formed on the urethane layer and the source and the drain.
  • the material of the top gate insulating layer may be silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), or the like, which is not limited in the present invention.
  • the specific process for forming the top gate insulating layer may be chemical vapor deposition, atomic layer deposition, or the like, which is not limited in the present invention.
  • a top gate electrode is formed over the top gate insulating layer, and the top gate electrode includes a third gate structure and a fourth gate structure. Specifically, forming the top gate electrode includes forming a vertical contact hole between the top gate electrode and the bottom gate electrode such that the top gate electrode is connected to the bottom gate electrode.
  • FIG. 7 is a flow chart of a method for fabricating a field effect transistor according to Embodiment 4 of the present invention.
  • the method is used to manufacture the field effect transistor provided in Embodiment 2, and the channel material is graphene as an example, including the following. step.
  • a substrate layer is provided. This step is the same as step 501 in Embodiment 3, and details are not described herein again.
  • a thin film structure required for forming a source and a drain is prepared on the substrate layer.
  • the film structure can be formed by a coating process.
  • the coating process includes a sputter coating process, an evaporation coating process, and the like, and the present invention does not limit the specific process for forming the film structure.
  • the material may be a metal material such as copper, platinum or gold.
  • the material of the film structure of the present invention is not limited.
  • a sacrificial layer is formed on the film structure, and the sacrificial layer is soluble in a specific solution.
  • the material of the sacrificial layer may be silicon oxide, polysilicon, silicon nitride, photoresist, etc., which is not specifically limited in the present invention.
  • a first recess structure and a second recess structure are formed on the substrate layer and the thin film structure and the sacrificial layer.
  • the first groove structure and the second groove structure are formed by photolithography and etching processes.
  • the lithography process may be selected as a general lithography process or an electron beam exposure lithography process according to the size characteristics of the FET to be fabricated, which is not limited in the present invention.
  • the etching includes ion beam etching or the like, and the present invention does not limit the specific process for forming the first groove structure and the second groove structure.
  • a first gate structure of the bottom gate electrode and a second gate structure of the bottom gate electrode are respectively formed in the first recess structure and the second recess structure.
  • a first gate structure of the bottom gate electrode and a second gate structure of the bottom gate electrode are formed by a process of electron beam evaporation coating.
  • the first gate structure and the second gate structure may be formed by other processes, which are not limited in the present invention.
  • a first bottom gate insulating layer and a second bottom gate insulating layer are respectively formed in the first recess structure and the second recess structure.
  • the first bottom gate insulating layer and the second bottom gate insulating layer are formed by a process of electron beam evaporation coating.
  • the first bottom gate insulating layer and the second bottom gate insulating layer may be formed by other processes, which is not limited in the present invention.
  • a graphene layer is attached.
  • the graphene layer is deposited in situ such that the graphene layer is folded into the first recess structure and the second recess structure over the first bottom gate insulating layer and the second bottom gate insulating layer.
  • graphene is uniformly and continuously attached to the surface of the structure to form an ohmic contact with the metal in the structure.
  • the first top gate insulating layer and the second top gate insulating layer are formed on the graphene layer as shown in FIG.
  • the first top gate insulating layer and the second top gate insulating layer are formed by a process of electron beam evaporation coating.
  • the first top gate insulating layer and the second top gate insulating layer may be formed by other processes, which is not limited in the present invention.
  • a third gate structure of the top gate electrode and a fourth gate structure of the top gate electrode are respectively formed on the first top gate insulating layer and the second top gate insulating layer.
  • the specific forming process further includes: forming a vertical contact hole between the top gate electrode and the bottom gate electrode, so that the top gate electrode is connected to the bottom gate electrode.
  • the sacrificial layer is etched away as shown in FIG. By etching away the sacrificial layer, the structure above the sacrificial layer is detached, thereby obtaining a field effect transistor that needs to be fabricated.
  • the completion of the hardware may also be performed by a program to instruct related hardware.
  • the program may be stored in a computer readable storage medium.
  • the storage medium mentioned above may be a read only memory, a magnetic disk or an optical disk.

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Abstract

提供一种场效应管及其制造方法。场效应管包括两个顶栅电极（1031C，1031D）和两个底栅电极（1032A，1032B），该顶栅电极（1031C，1031D）和底栅电极（1032A，1032B）两两相对，使得场效应管增加了由控制电压感生的载流子数量，增加了场效应管的输出电流，提高了在高频使用时的功率增益极限频率，并使得顶栅电极（1031C，1031D）和底栅电极（1032A，1032B）之间的电场更加充分地覆盖源极（1041，1042）和漏极（105）之间的沟道层（106），进而减小了在高频下的寄生效应，进一步提高了场效应管的频率特性。

Description

场效应管及其制造方法 技术领域
本发明涉及电子技术领域，特别涉及一种场效应管及其制造方法。
背景技术
随着电子技术的发展，硅集成电路中电子元件的频率特性，例如功率增益极限频率等，逐渐逼近物理规律的极限，进而如何使得电子元件的频率特性进一步提高成为了本技术领域重要的技术问题。
场效应管是一种常见的电子元件，现有技术中一般采用硅基半导体材料来制备场效应管，为了提供更好的频率特性，可以采用石墨烯等二维材料代替硅基半导体材料，从而制备基于石墨烯材料的场效应管。由于石墨烯材料具有二维特性、高迁移率、高饱和速度等优势，进而使得上述基于石墨烯材料的场效应管相比于传统硅基场效应管能够具有更好的频率特性，例如，具有更高的截止频率。
然而，由于上述基于石墨烯材料的场效应管仍采用传统的绝缘栅场效应管结构，进而容易造成输出电流低、对载流子散射效应较大、寄生效应明显等问题，使得该基于石墨烯材料的场效应管未实现理想的频率特性。
发明内容
为了克服本领域内存在的技术问题，本发明实施例提供了一种场效应管及其制造方法。该技术方案如下。
第一方面，提供了一种场效应管，所述场效应管包括：
衬底层101，所述衬底层101的上表面凹槽中设置有第一栅结构1032A和 第二栅结构1032B；
覆盖于所述衬底层101上表面的底栅绝缘层1022；
覆盖于所述底栅绝缘层1022上表面的沟道层106；
覆盖于所述沟道层106上表面的顶栅绝缘层1021，
所述顶栅绝缘层1021的下表面上设置有：所述第一源极1041、第二源极1042以及设置于所述第一源极1041和第二源极1042之间的漏极105，
所述顶栅绝缘层1021的上表面凹槽中设置有第三栅结构1031C和第四栅结构1031D；
所述第三栅结构1031C设置于所述第一栅结构1032A在所述顶栅绝缘层1021上的第一投影区域内，所述第一投影区域位于所述第一源极1041与所述漏极105之间；
所述第四栅结构1031D设置于所述第二栅结构1032B在所述顶栅绝缘层1021上的第二投影区域内，所述第二投影区域位于所述第二源极1042与所述漏极105之间。
在第一方面的一种可能设计中，所述第一投影区域的两个边缘分别与所述第一源极1041的边缘及所述漏极105的边缘相重合，所述第二投影区域的两个边缘分别与所述第二源极1042的边缘及所述漏极105的的边缘相重合。
在第一方面的一种可能设计中，所述第三栅结构1031C的面积小于或等于所述第一投影区域的面积；
所述第四栅结构1031D的面积小于或等于所述第二投影区域的面积。
在第一方面的一种可能设计中，所述第三栅结构1031C和所述第四栅结构1031D相互平行；或，
所述第三栅结构1031C和所述第四栅结构1031D为一个门框形的连通结构。
在第一方面的一种可能设计中，所述第一栅结构1032A与所述第三栅结构1031C通过接触孔相连接，所述第二栅结构1032B与所述第四栅结构1031D 通过接触孔相连接。
在第一方面的一种可能设计中，所述沟道层采用石墨烯、二硫化钼、或黑磷或其他二维材料中的一种。
第二方面，提供了一种场效应管，所述场效应管包括：
衬底层401，所述衬底层401的上表面的第一凹槽中设置有第一栅结构4032A以及覆盖于第一栅结构4032A上的第一底栅绝缘层4022A，所述衬底层401的上表面的第二凹槽中第二栅结构4032B以及覆盖于所述第二底栅绝缘层4022B；
覆盖于所述第一底栅绝缘层4022A上，且呈凹槽形状的第一沟道层4061；
覆盖于所述第二底栅绝缘层4022B上，且呈凹槽形状的第二沟道层4062；
所述第一沟道层4061所形成的凹槽的底表面上设置有第一顶栅绝缘层4021C以及覆盖在所述第一顶栅绝缘层4021C上的第三栅结构4031A；
所述第二沟道层4062所形成的凹槽的底表面上设置有第二顶栅绝缘层4021D以及覆盖在所述第二顶栅绝缘层4021D上的第四栅结构4031B；
设置于由所述衬底层401、所述第一沟道层4061的第一外表面以及所述第二沟道层4062的第一外表面所形成的凹槽结构内的源极405；
覆盖于所述衬底层401上、并与所述所述第一沟道层4061的第二外表面相接触的第一源极4041；
覆盖于所述衬底层401上、并与所述所述第二沟道层4062的第二外表面相接触的第一源极4042。
在第二方面的一种可能设计中，所述沟道层采用石墨烯、二硫化钼、或黑磷或其他二维材料中的一种。
第三方面，提供了一种场效应管的制造方法，所述方法包括：
提供一衬底层；
在所述衬底层上形成底栅电极，所述底栅电极包括第一栅结构和第二栅结构；
在所述底栅电极之上形成底栅绝缘层；
在所述底栅绝缘层之上附着沟道层；
在所述墨烯层之上形成源极及漏极，所述源极包括第一源极和第二源极；
在所述墨烯层及所述源极及漏极之上形成顶栅绝缘层；
在所述顶栅绝缘层之上形成顶栅电极，所述顶栅电极包括第三栅结构和第四栅结构。
在第三方面的一种可能设计中，所述在所述衬底层上形成底栅电极包括：
采用光刻及刻蚀工艺，在所述衬底层上形成两个凹槽结构；
在所述两个凹槽结构内分别形成所述底栅电极的第一栅结构和所述底栅电极的第二栅结构。
在第三方面的一种可能设计中，在所述形成底栅绝缘层之前，所述方法还包括：
采用化学机械抛光方法，对形成底栅电极的衬底层表面进行处理。
在第三方面的一种可能设计中，所述在所述顶栅绝缘层之上形成顶栅电极包括：
在所述顶栅电极与所述底栅电极之间制作垂直接触孔，使得所述顶栅电极与所述底栅电极相连接。
第四方面，提供了一种场效应管的制造方法，所述方法包括：
提供一衬底层；
在所述衬底层上制备形成源极及漏极所需的薄膜结构；
在所述薄膜结构上形成牺牲层，所述牺牲层可溶解于特定的溶液；
在所述衬底层及所述薄膜结构及所述牺牲层上形成第一凹槽结构与第二凹槽结构；
在所述第一凹槽结构及第二凹槽结构内分别形成底栅电极的第一栅结构 和底栅电极的第二栅结构；
在所述第一凹槽结构及第二凹槽结构内分别形成第一底栅绝缘层和第二底栅绝缘层；
附着沟道层；
在所述沟道层上形成第一顶栅绝缘层及第二顶栅绝缘层；
在所述第一顶栅绝缘层及所述第二顶栅绝缘层之上分别形成顶栅电极的第三栅结构和顶栅电极的第四栅结构；
腐蚀掉所述牺牲层。
在第四方面的一种可能设计中，在形成第一底栅绝缘层和第二底栅绝缘层之后，所述附着沟道层包括：
原位沉积所述沟道层，使得所述沟道层折叠贴服在第一底栅绝缘层和第二底栅绝缘层之上的第一凹槽结构及第二凹槽结构内。
在第四方面的一种可能设计中，所述形成顶栅电极的第三栅结构和顶栅电极的第四栅结构包括：
在所述顶栅电极与所述底栅电极之间制作垂直接触孔，使得所述顶栅电极与所述底栅电极相连接。
本发明实施例提供的技术方案的有益效果是：
本发明提供的场效应管包括两个顶栅电极和两个底栅电极，该顶栅电极和底栅电极两两相对，使得该场效应管增加了由控制电压感生的载流子数量，进而增大场效应管的输出电流，提高了在高频使用时的功率增益极限频率，并且使得该顶栅电极和该底栅电极之间的电场更加充分的覆盖该源极和该漏极之间的该沟道层，进而减小了在高频下的寄生效应，进一步提高了场效应管的频率特性。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所 需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例1提供的一种场效应管的垂直切面结构示意图；
图2是本发明实施例1提供的一种场效应管的垂直切面结构中关于投影区域的示意图；
图3是发明实施例1提供的一种场效应管沿图2中AA’方向的剖视图；
图4是本发明实施例2提供的一种场效应管的垂直切面结构示意图；
图5是本发明实施例3提供的一种场效应管制造方法的流程图；
图6是本发明实施例3提供的一种场效应管制造方法中每个步骤完成时，待制造的场效应管结构示意图；
图7是本发明实施例4提供的一种场效应管制造方法的流程图；
图8是本发明实施例4提供的一种场效应管制造方法中每个步骤完成时，待制造的场效应管结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
实施例1
图1是本发明实施例1提供的一种场效应管的垂直切面结构示意图，如图所示，该场效应管包括：
衬底层101，所述衬底层101的上表面凹槽中设置有第一栅结构1032A和第二栅结构1032B；
覆盖于所述衬底层101上表面的底栅绝缘层1022，该底栅绝缘层1022用于使得作为底栅电极的第一栅结构1032A和第二栅结构1032B与该沟道层106之间为断开状态。
覆盖于所述底栅绝缘层1022上表面的沟道层106；
覆盖于所述沟道层106上表面的顶栅绝缘层1021，
所述顶栅绝缘层1021的下表面上设置有：所述第一源极1041、第二源极1042以及设置于所述第一源极1041和第二源极1042之间的漏极105，通过上述结构，沟道层106与该第一源极1041、第二源极1042及该漏极105相接触，使得通过栅电极103施加控制电压时，基于该沟道层106，在该该源极104和该漏极105之间形成导电沟道。所述顶栅绝缘层1021的上表面凹槽中设置有第三栅结构1031C和第四栅结构1031D，该顶栅绝缘层1021用于使得该第三栅结构1031C和第四栅结构1031D与该沟道层106之间为断开状态；
所述第三栅结构1031C设置于所述第一栅结构1032A在所述顶栅绝缘层1021上的第一投影区域内，所述第一投影区域位于所述第一源极1041与所述漏极105之间；
所述第四栅结构1031D设置于所述第二栅结构1032B在所述顶栅绝缘层1021上的第二投影区域内，所述第二投影区域位于所述第二源极1042与所述漏极105之间。
为了在该沟道层106的上下两个方向共同施加控制电压，以增加由该控制电压感生的载流子数量，进而增大场效应管的输出电流，提高在高频使用时的功率增益极限频率，本发明实施例所提供的结构包括作为顶栅电极的第三栅结构1031C和第四栅结构和底栅电极的第一栅结构1032A和第二栅结构1032B。
该漏极105设置于该第一源极1041和第二源极1042之间，进而使得在该第一源极1041与该漏极105之间及该第二源极1042与该漏极105分别形成导电沟道，从而提供了一种双导电沟道结构，进一步提高场效应管的输出电流，提高另外在高频使用时的功率增益极限频率。
该第一栅结构1032A和第三栅结构1031C对应，用于向一导电沟道施加控制电压，该第二栅结构1032B和第四栅结构1031D对应，用于向另一导电沟道施加控制电压。需要说明的是，在实际应用中，分别用于形成该两个导电 沟道的栅电极、栅极绝缘层及源极可以具有相同的形状和尺寸，也可以根据需要具有不同的形状和尺寸，本发明对上述任一结构的具体形状和尺寸不作限定。还需要说明的是，在实际应用中，作为源极的第一源极1041和第二源极1042和漏极105接入的电压可以互换，进而第一源极1041和第二源极1042可以被设置为漏极，而漏极105可以被设置为源极，本发明对源极和漏极是否互换不作具体限定。
为了在施加控制电压时，能够使得顶栅电极1031和底栅电极1032之间的电场充分覆盖该第一源极1041、第二源极1042和该漏极105之间的沟道层106，进而减小场效应管在高频下的寄生效应，如寄生电阻、寄生电容等，进而提升场效应管的频率特性，本发明实施例中，如图2所示，该第三栅结构1031C设置于该第一栅结构1032A在该顶栅绝缘层1021上的第一投影区域201内，该第一投影区域201位于该第一源极1041与该漏极105之间，该第三栅结构1031C与第一栅结构1032A之间依次设置为顶栅绝缘层1021、该沟道层106、该底栅绝缘层1022。顶栅绝缘层1021以及底栅绝缘层1022统称为栅极绝缘层102，顶栅电极1031和底栅电极1032统称为栅电极103。
相应地，该第四栅结构1031D设置于该第二栅结构1032B在该顶栅绝缘层1021上的第二投影区域202内，该第二投影区域202位于该第二源极1042与漏极105之间，该第四栅结构1031D与该第二栅结构1032B及之间依次设置为顶栅绝缘层1021、该沟道层106、该底栅绝缘层1022。
为了在施加控制电压时，能够使得顶栅电极和底栅电极之间的电场更加充分覆盖该第一源极1041、第二源极1042和该漏极105之间的沟道层106，进而进一步减小高频下的寄生效应，在本发明实施例中，如图2所示，该第一投影区域201的两个边缘2011分别与该第一源极1041的边缘及该漏极105的边缘相重合，该第二投影区域202的两个边缘2021分别与该第二源极1042的边缘及该漏极105的边缘相重合。
为了在施加控制电压时，能够使得顶栅电极1031和底栅电极1032之间的 电场更加充分覆盖该源极104和该漏极105之间的沟道层106，进而进一步减小高频下的寄生效应，在本发明实施例中，该第三栅结构1031C的面积小于等于该第一投影区域201面积，该第四栅结构1031D的面积小于等于该第二投影区域202面积。图3是图2中沿AA’方向的剖视图，如图3所示，该第一投影区域201及该第一投影区域202的面积是指该任一投影区域在与衬底层101平行的平面上所占面积。
为了进一步提高场效应管的输出电流，进而进一步提高在高频使用时的功率增益极限频率，在本发明实施例中，该第三栅结构1031C和该第四栅结构1031D相互平行。具体地，如图3所示，所述第三栅结构1031C和所述第四栅结构1031D为一个门框形的连通结构，也即是，顶栅电极包括相互平行的两部分以及用于连接该两部分之间的连通部分。该相互平行的部分可以分别为矩形结构。需要说明的是，上述任一个栅结构的形状可以根据实际应用情况进行设置，本发明对此不做限定。
为了方便制造，该衬底层101具有凹槽结构，该底栅电极1032设置于该凹槽结构之中。具体地，该衬底层101具有两个相互平行的凹槽结构，该底栅电极1032的第一栅结构1032A和第二栅结构1032B分别设置于该两个相互平行的凹槽结构。
为了可以在顶栅电极1031和底栅电极1032施加相同的控制电压，该顶栅电极和底栅电极通过接触孔相连接，也即是，所述第一栅结构1032A与所述第三栅结构1031C通过接触孔相连接，所述第二栅结构1032B与所述第四栅结构1031D通过接触孔相连接。该接触孔设置的具体位置可以根据电路布线的实际情况进行选择，本发明对此不作限定。
实施例2
图4是本发明实施例2提供的一种场效应管的垂直切面结构示意图，如图4所示，该场效应管包括：
衬底层401，所述衬底层401的上表面的第一凹槽中设置有第一栅结构4032A以及覆盖于第一栅结构4032A上的第一底栅绝缘层4022A，所述衬底层401的上表面的第二凹槽中第二栅结构4032B以及覆盖于所述第二底栅绝缘层4022B，以方便制造。
覆盖于所述第一底栅绝缘层4022A上，且呈凹槽形状的第一沟道层4061；
覆盖于所述第二底栅绝缘层4022B上，且呈凹槽形状的第二沟道层4062；
所述第一沟道层4061所形成的凹槽的底表面上设置有第一顶栅绝缘层4021C以及覆盖在所述第一顶栅绝缘层4021C上的第三栅结构4031C；
所述第二沟道层4062所形成的凹槽的底表面上设置有第二顶栅绝缘层4021D以及覆盖在所述第二顶栅绝缘层4021D上的第四栅结构4031D，这种结构，是为了基于石墨烯柔软的机械性能，方便制造。
设置于由所述衬底层401、所述第一沟道层4061的第一外表面以及所述第二沟道层4062的第一外表面所形成的凹槽结构内的源极405；
覆盖于所述衬底层401上、并与所述所述第一沟道层4061的第二外表面相接触的第一源极4041；
覆盖于所述衬底层401上、并与所述所述第二沟道层4062的第二外表面相接触的第一源极4042。
该第一沟道层4061与该第一源极4041及该漏极405相接触，用于形成该第一源极4041及该漏极405之间的导电沟道，该第二沟道层4062与该第二源极4042及该漏极405相接触，用于形成该第二源极4042和该漏极405之间的导电沟道，从而在施加控制电压时，能够使得顶栅电极和底栅电极之间的电场完全覆盖该源极和该漏极之间的沟道层，进而进一步减小高频下的寄生效应。
需要说明的是，在实际应用中，该第一顶栅绝缘层4021C和第二顶栅绝缘层4021D可以连接，也可以不连接，该第一底栅绝缘层4022A和第二底栅绝缘层4022B可以连接，也可以不连接，本发明对此不作具体限定。
实施例3
图5是本发明实施例3提供的一种场效应管制造方法的流程图，该方法用于制造实施例1提供的场效应管，并以沟道材料为石墨烯为例进行说明，包括以下步骤。
501、如图6中a图所示，提供一衬底层。在实际应用中，该衬底层的材料可以是的二氧化硅(SiO2)、碳化硅(SiC)、氮化硼(BN)、氮化硅(Si3N4)、聚对苯二甲酸乙二酯(PET)、蓝宝石等绝缘材料，本发明对衬底层的材料不作具体限定。
502、如图6中b图所示，在该衬底层上形成底栅电极，该底栅电极包括第一栅结构和第二栅结构。具体地，采用光刻及刻蚀及镀膜工艺，在该衬底层上形成两个凹槽结构，在该两个凹槽结构内分别形成该底栅电极的第一栅结构和该底栅电极的第二栅结构。在实际应用中，该底栅电极的材料可以是铜，铂，金等金属材料，本发明对该底栅电极的材料不作限定。在实际应用中，根据待制造场效应管的尺寸特征，该光刻工艺可以选择为普通光刻工艺，或电子束曝光光刻工艺，本发明对此不作限定。在实际应用中，该刻蚀工艺包括等离子体刻蚀等，该镀膜工艺包括溅射镀膜工艺、蒸发镀膜工艺等，本发明对形成该底栅电极的具体工艺不作限定。
503、如图6中c图所示，在该底栅电极之上形成底栅绝缘层。本发明实施例中，在本步骤之前采用化学机械抛光方法，对形成底栅电极的衬底层表面进行处理，使得该表面保持平整。该底栅绝缘层材料可以是SiO2，Al2O3等，本发明对此不作限定。形成该底栅绝缘层的具体工艺可以为化学气相沉积、原子层沉积等，本发明对此不作限定。
504、如图6中d图所示，在该底栅绝缘层之上附着石墨烯层。
505、如图6中e图所示，在该墨烯层之上形成源极及漏极，该源极包括第一源极和第二源极，该漏极设置于该第一源极和该第二源极之间。具体形成过程包括：在该石墨烯层上通过光刻工艺定义源极及漏极区域，然后通过镀膜 工艺形成源极及漏极。该源极及漏极材料可以是铜，铂，金等金属。
506、如图6中f图所示，在该墨烯层及该源极及漏极之上形成顶栅绝缘层。该顶栅绝缘层材料可以是二氧化硅(SiO2)、三氧化二铝(Al2O3)等，本发明对此不作限定。形成该顶栅绝缘层的具体工艺可以为化学气相沉积、原子层沉积等，本发明对此不作限定。
507、如图6中g图所示，在该顶栅绝缘层之上形成顶栅电极，该顶栅电极包括第三栅结构和第四栅结构。具体地，在形成该顶栅电极包括在该顶栅电极与该底栅电极之间制作垂直接触孔，使得该顶栅电极与该底栅电极相连接。
实施例4
图7是本发明实施例4提供的一种场效应管制造方法的流程图，该方法用于制造实施例2提供的场效应管，并以沟道材料为石墨烯为例进行说明，包括以下步骤。
701、如图8中a图所示，提供一衬底层，该步骤与实施例3中步骤501同理，在此不再赘述。
702、如图8中b图所示，在该衬底层上制备形成源极及漏极所需的薄膜结构。该薄膜结构可以通过镀膜工艺形成。该镀膜工艺包括溅射镀膜工艺、蒸发镀膜工艺等，本发明对形成该薄膜结构的具体工艺不作限定。在实际应用中，该的材料可以是铜，铂，金等金属材料，本发明对该薄膜结构的材料不作限定。
703、如图8中c图所示，在该薄膜结构上形成牺牲层，该牺牲层可溶解于特定的溶液。该牺牲层材料可以是氧化硅、多晶硅、氮化硅、光刻胶等，本发明对此不作具体限定。
704、如图8中d图所示，在该衬底层及该薄膜结构及该牺牲层上形成第一凹槽结构与第二凹槽结构。采用光刻及刻蚀工艺形成该第一凹槽结构及第二凹槽结构。在实际应用中，根据待制造场效应管的尺寸特征，该光刻工艺可以选择为普通光刻工艺，或电子束曝光光刻工艺，本发明对此不作限定。该刻蚀 工艺包括离子束刻蚀等，本发明对形成该第一凹槽结构与第二凹槽结构的具体工艺不作限定。
705、如图8中e图所示，在该第一凹槽结构及第二凹槽结构内分别形成底栅电极的第一栅结构和底栅电极的第二栅结构。采用电子束蒸发镀膜的工艺形成该底栅电极的第一栅结构和底栅电极的第二栅结构。在实际应用中，也可以采用其他工艺形成该第一栅结构和该第二栅结构，本发明对此不作限定。
706、如图8中f图所示，在该第一凹槽结构及第二凹槽结构内分别形成第一底栅绝缘层和第二底栅绝缘层。采用电子束蒸发镀膜的工艺形成该第一底栅绝缘层和第二底栅绝缘层。在实际应用中，也可以采用其他工艺形成该第一底栅绝缘层和该第二底栅绝缘层，本发明对此不作限定。
707、如图8中g图所示，附着石墨烯层。原位沉积该石墨烯层，使得该石墨烯层折叠贴服在第一底栅绝缘层和第二底栅绝缘层之上的第一凹槽结构及第二凹槽结构内。在本发明实施例中，石墨烯均匀连续附着在该结构表面，与该结构中的金属形成欧姆接触。
708、如图8中h图所示，在该石墨烯层上形成第一顶栅绝缘层及第二顶栅绝缘层。采用电子束蒸发镀膜的工艺形成该第一顶栅绝缘层及第二顶栅绝缘层。在实际应用中，也可以采用其他工艺形成该第一顶栅绝缘层及该第二顶栅绝缘层，本发明对此不作限定。
709、如图8中i图所示，在该第一顶栅绝缘层及该第二顶栅绝缘层之上分别形成顶栅电极的第三栅结构和顶栅电极的第四栅结构。具体形成过程还包括：在该顶栅电极与该底栅电极之间制作垂直接触孔，使得该顶栅电极与该底栅电极相连接。
710、如图8中j图所示，腐蚀掉该牺牲层。通过腐蚀掉该牺牲层，使得该牺牲层之上的结构脱落，进而获得需要制造的场效应管。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通 过硬件来完成，也可以通过程序来指令相关的硬件完成，该的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上该仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种场效应管，其特征在于，所述场效应管包括：
    衬底层(101)，所述衬底层(101)的上表面凹槽中设置有第一栅结构(1032A)和第二栅结构(1032B)；
    覆盖于所述衬底层(101)上表面的底栅绝缘层(1022)；
    覆盖于所述底栅绝缘层(1022)上表面的沟道层(106)；
    覆盖于所述沟道层(106)上表面的顶栅绝缘层(1021)，
    所述顶栅绝缘层(1021)的下表面上设置有：所述第一源极(1041)、第二源极(1042)以及设置于所述第一源极(1041)和第二源极(1042)之间的漏极(105)，
    所述顶栅绝缘层(1021)的上表面凹槽中设置有第三栅结构(1031C)和第四栅结构(1031D)；
    所述第三栅结构(1031C)设置于所述第一栅结构(1032A)在所述顶栅绝缘层(1021)上的第一投影区域内，所述第一投影区域位于所述第一源极(1041)与所述漏极(105)之间；
    所述第四栅结构(1031D)设置于所述第二栅结构(1032B)在所述顶栅绝缘层(1021)上的第二投影区域内，所述第二投影区域位于所述第二源极(1042)与所述漏极(105)之间。
  2. 根据权利要求1所述的场效应管，其特征在于，所述第一投影区域的两个边缘分别与所述第一源极(1041)的边缘及所述漏极(105)的边缘相重合，所述第二投影区域的两个边缘分别与所述第二源极(1042)的边缘及所述漏极(105)的的边缘相重合。
  3. 根据权利要求1所述的场效应管，其特征在于，所述第三栅结构(1031C)的面积小于或等于所述第一投影区域的面积；
    所述第四栅结构(1031D)的面积小于或等于所述第二投影区域的面积。
  4. 根据权利要求1所述的场效应管，其特征在于，所述第三栅结构(1031C)和所述第四栅结构(1031D)相互平行；或，
    所述第三栅结构(1031C)和所述第四栅结构(1031D)为一个门框形的连通结构。
  5. 根据权利要求1所述的场效应管，其特征在于，所述第一栅结构(1032A)与所述第三栅结构(1031C)通过接触孔相连接，所述第二栅结构(1032B)与所述第四栅结构(1031D)通过接触孔相连接。
  6. 根据权利要求1所述的场效应管，所述沟道层采用石墨烯、二硫化钼、或黑磷或其他二维材料中的一种。
  7. 一种场效应管，其特征在于，所述场效应管包括：
    衬底层(401)，所述衬底层(401)的上表面的第一凹槽中设置有第一栅结构(4032A)以及覆盖于第一栅结构(4032A)上的第一底栅绝缘层(4022A)，所述衬底层(401)的上表面的第二凹槽中第二栅结构(4032B)以及覆盖于所述第二底栅绝缘层(4022B)；
    覆盖于所述第一底栅绝缘层(4022A)上，且呈凹槽形状的第一沟道层(4061)；
    覆盖于所述第二底栅绝缘层(4022B)上，且呈凹槽形状的第二沟道层(4062)；
    所述第一沟道层(4061)所形成的凹槽的底表面上设置有第一顶栅绝缘层(4021C)以及覆盖在所述第一顶栅绝缘层(4021C)上的第三栅结构(4031C)；
    所述第二沟道层(4062)所形成的凹槽的底表面上设置有第二顶栅绝缘层(4021D)以及覆盖在所述第二顶栅绝缘层(4021D)上的第四栅结构(4031D)；
    设置于由所述衬底层(401)、所述第一沟道层(4061)的第一外表面以及所述第二沟道层(4062)的第一外表面所形成的凹槽结构内的源极(405)；
    覆盖于所述衬底层(401)上、并与所述所述第一沟道层(4061)的第二外表面相接触的第一源极(4041)；
    覆盖于所述衬底层(401)上、并与所述所述第二沟道层(4062)的第二外表面相接触的第一源极(4042)。
  8. 根据权利要求7所述的场效应管，所述沟道层采用石墨烯、二硫化钼、或黑磷或其他二维材料中的一种。
  9. 一种场效应管的制造方法，其特征在于，所述方法包括：
    提供一衬底层；
    在所述衬底层上形成底栅电极，所述底栅电极包括第一栅结构和第二栅结构；
    在所述底栅电极之上形成底栅绝缘层；
    在所述底栅绝缘层之上附着沟道层；
    在所述墨烯层之上形成源极及漏极，所述源极包括第一源极和第二源极；
    在所述墨烯层及所述源极及漏极之上形成顶栅绝缘层；
    在所述顶栅绝缘层之上形成顶栅电极，所述顶栅电极包括第三栅结构和第四栅结构。
  10. 根据权利要求9所述的方法，其特征在于，所述在所述衬底层上形成底栅电极包括：
    采用光刻及刻蚀工艺，在所述衬底层上形成两个凹槽结构；
    在所述两个凹槽结构内分别形成所述底栅电极的第一栅结构和所述底栅电极的第二栅结构。
  11. 根据权利要求9所述的方法，其特征在于，在所述形成底栅绝缘层之前，所述方法还包括：
    采用化学机械抛光方法，对形成底栅电极的衬底层表面进行处理。
  12. 一种场效应管的制造方法，其特征在于，所述方法包括：
    提供一衬底层；
    在所述衬底层上制备形成源极及漏极所需的薄膜结构；
    在所述薄膜结构上形成牺牲层，所述牺牲层可溶解于特定的溶液；
    在所述衬底层及所述薄膜结构及所述牺牲层上形成第一凹槽结构与第二凹槽结构；
    在所述第一凹槽结构及第二凹槽结构内分别形成底栅电极的第一栅结构和底栅电极的第二栅结构；
    在所述第一凹槽结构及第二凹槽结构内分别形成第一底栅绝缘层和第二底栅绝缘层；
    附着沟道层；
    在所述沟道层上形成第一顶栅绝缘层及第二顶栅绝缘层；
    在所述第一顶栅绝缘层及所述第二顶栅绝缘层之上分别形成顶栅电极的第三栅结构和顶栅电极的第四栅结构；
    腐蚀掉所述牺牲层。
  13. 根据权利要求12所述的方法，其特征在于，在形成第一底栅绝缘层和第二底栅绝缘层之后，所述附着沟道层包括：
    原位沉积所述沟道层，使得所述沟道层折叠贴服在第一底栅绝缘层和第二底栅绝缘层之上的第一凹槽结构及第二凹槽结构内。
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