CN103782391A - 碳化硅半导体器件及其制造方法 - Google Patents
碳化硅半导体器件及其制造方法 Download PDFInfo
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- CN103782391A CN103782391A CN201280043216.5A CN201280043216A CN103782391A CN 103782391 A CN103782391 A CN 103782391A CN 201280043216 A CN201280043216 A CN 201280043216A CN 103782391 A CN103782391 A CN 103782391A
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- silicon carbide
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 94
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims description 54
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 238000005530 etching Methods 0.000 claims abstract description 34
- 239000007789 gas Substances 0.000 claims description 21
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000000460 chlorine Substances 0.000 claims description 12
- 229910052801 chlorine Inorganic materials 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 229910052736 halogen Inorganic materials 0.000 claims description 9
- 150000002367 halogens Chemical class 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 4
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 4
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 75
- 239000010408 film Substances 0.000 description 59
- 239000011229 interlayer Substances 0.000 description 11
- 239000013078 crystal Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000011049 filling Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 230000001413 cellular effect Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000000007 visual effect Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000003595 mist Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 238000002050 diffraction method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006298 dechlorination reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Abstract
当在平面图中观察时,终端区(TM)围绕元件区(CL)。热蚀刻碳化硅衬底(SB)的第一侧以在终端区(TM)处的碳化硅衬底(SB)中形成侧壁(ST)和底表面(BT)。侧壁(ST)具有{0-33-8}和{0-11-4}中的一种面取向。底表面(BT)具有{000-1}的面取向。在侧壁(ST)和底表面(BT)上,形成绝缘膜(8T)。第一电极(12)形成在元件区(CL)处的碳化硅衬底(SB)的第一侧上。第二电极(14)形成在碳化硅衬底(SB)的第二侧上。
Description
技术领域
本发明涉及一种碳化硅半导体器件以及制造碳化硅半导体器件的方法,更特别地,涉及一种在平面图中观察时具有设置有半导体元件的元件区以及围绕元件区的终端区的碳化硅半导体器件,以及制造这种碳化硅半导体器件的方法。
背景技术
根据日本专利特开No.2010-147222(专利文献1),SiC半导体器件具有设置有MOSFET的单元区以及围绕单元区的外周边区。在外周边区中,形成由凹槽构成的台面(mesa)结构部分。在单元区和外周边区之间的边界部分处,形成p型resurf层(降低表面电场层)以围绕单元区的外周边,从而从台面结构部分的阶梯部分的一个侧壁表面延伸至其底表面。而且,形成多个p型保护环层以围绕p型resurf层的外周边。而且,形成n+型层和电连接至n+型层的相同电势的环电极以围绕p型resurf层和p型保护环层的外周边,由此形成外周边击穿电压结构。而且,分别在衬底的正表面侧和背表面侧提供源电极和漏电极。
引证文献列表
专利文献
PTL1:日本专利特开No.2010-147222
发明内容
技术问题
在外周边区(终端区)中,为了钝化,通常在衬底(碳化硅衬底)上形成绝缘膜。因此,在外周边区中,在衬底(碳化硅衬底)和绝缘膜之间形成界面。因为电流很可能沿该界面流动,因此泄漏电流很可能在源电极和漏电极(第一和第二电极)之间流动。由于本发明人的检验,已经发现当终端区中的碳化硅衬底的晶体学面取向不合适时,在碳化硅衬底和绝缘膜之间的界面中的界面态密度变高,结果是泄漏电流可能在第一和第二电极之间流动。
已经提出本发明以解决上述问题,并且其目的是提供一种可以抑制电极之间的泄漏电流的碳化硅半导体器件,以及制造这种碳化硅半导体器件的方法。
解决问题的手段
本发明中的制造碳化硅半导体器件的方法是制造在平面图中观察时具有设置有半导体元件的元件区以及围绕元件区的终端区的碳化硅半导体器件的方法,并且包括如下步骤。制备由具有六方单晶结构的碳化硅制成并在厚度方向上具有彼此相反的第一侧和第二侧的碳化硅衬底。热蚀刻碳化硅衬底的第一侧以便在终端区处的碳化硅衬底中形成侧壁和底表面,侧壁围绕元件区并具有{0-33-8}或{0-11-4}的面取向,底表面围绕包括元件区和侧壁的区域并具有{000-1}的面取向。绝缘膜形成在侧壁和底表面上。第一电极形成在元件区处的碳化硅衬底的第一侧上。第二电极形成在碳化硅衬底的第二侧上。
根据该制造方法,在第一和第二电极之间的部分处的碳化硅衬底的表面中,借助热蚀刻形成侧壁和底表面。热蚀刻的采用提供了具有{0-33-8}或{0-11-4}面取向的侧壁,并且提供了具有{000-1}面取向的底表面。因此,在绝缘膜与碳化硅衬底的侧壁和底表面中的每一个之间的界面具有低界面态密度。因此,抑制由于界面态的存在而导致的电流的产生,借此可以抑制第一和第二电极之间的泄漏电流。
优选地,热蚀刻的步骤包括在元件区处的碳化硅衬底中形成沟道表面的步骤,沟道表面具有{0-33-8}或{0-11-4}的面取向。因此,可以提高沿沟道表面的载流子迁移率,由此抑制沟道电阻。这致使碳化硅半导体器件的较小导通电阻。更优选地,形成沟道表面的步骤通过形成设置有包括沟道表面的内壁的沟槽来执行。通过采用沟槽结构,可以以高密度在相同区域中设置沟道。以此方式,可以获得更大的电流。
优选地,使用包含卤族元素的工艺气体执行热蚀刻步骤。以此方式,沟槽的侧壁可以自发地形成为对应于所需晶面。而且,通过使用SiO2用作掩膜材料,可以获得针对SiC的高选择比,由此可以确保形成沟槽。更优选地,卤族元素是氯。由于上述相同的原因,因此采用氯气允许更能确保对应于所需晶面的表面的形成。工艺气体可以包含四氟化碳和六氟化硫中至少一种。而且以此方式,沟槽的侧壁可以自发地形成为对应所需晶面。优选地,工艺气体包含氧气。因此,在热蚀刻过程中引入氧,使得形成在SiC表面上的碳薄膜层(SiC中的剩余C原子)可以随SiC被同时移除。
本发明中的碳化硅半导体器件是在平面图中观察时具有设置有半导体元件的元件区以及围绕元件区的终端区的碳化硅半导体器件。这种碳化硅半导体器件包括碳化硅衬底、第一和第二电极以及绝缘膜。碳化硅衬底由具有六方单晶结构的碳化硅制成并具有在厚度方向上彼此相反的第一侧和第二侧。碳化硅衬底的第一侧在终端区中设置有侧壁和底表面,侧壁围绕元件区并具有{0-33-8}或{0-11-4}的面取向,底表面围绕侧壁并具有{000-1}的面取向。绝缘膜设置在侧壁和底表面上。第一电极设置在元件区处的碳化硅衬底的第一侧上。第二电极设置在碳化硅衬底的第二侧上。
根据这种器件,在第一和第二电极之间的部分处的碳化硅衬底的表面中,提供侧壁和底表面。因为使侧壁适于具有{0-33-8}或{0-11-4}的面取向,并且使底表面适于具有{000-1}的面取向,因此在绝缘膜与侧壁和底表面中的每一个之间的界面具有低界面态密度。因此,可以抑制由界面态的存在而导致的电流的产生,由此可以抑制第一和第二电极之间的泄漏电流。
优选地,在元件区中,碳化硅衬底的第一侧设置有具有{0-33-8}或{0-11-4}的面取向的沟道表面。因此,可以提高沿沟道表面的载流子迁移率,由此抑制沟道电阻。这致使碳化硅半导体器件的小导通电阻。更优选地,沟道表面是设置在元件区处的碳化硅衬底的第一侧中的沟槽的内壁的一部分。
本发明的有益效果
根据本发明,如上所述,可以抑制电极之间的泄漏电流。
附图说明
图1(A)示意性示出本发明的一个实施例中的碳化硅半导体器件的表面布局。图1(B)是虚线IB处的局部放大图。图1(C)是对应于局部放大图的局部平面图。
图2是沿图1中的线II-II截取的示意性局部截面图。
图3是示意性示出对应于图2的视场中的、制造本发明的该实施例中的碳化硅半导体器件的方法的第一步骤的局部截面图。
图4是示意性示出对应于图2的视场中的、制造本发明的该实施例中的碳化硅半导体器件的方法的第二步骤的局部截面图。
图5是示意性示出对应于图2的视场中的、制造本发明的该实施例中的碳化硅半导体器件的方法的第三步骤的局部截面图。
图6是示意性示出对应于图2的视场中的、制造本发明的该实施例中的碳化硅半导体器件的方法的第四步骤的局部截面图。
具体实施方式
下文参考附图说明本发明的一个实施例。应当注意在下述附图中,相同或相应的部分由相同的附图标记指定并且不再赘述。对于本说明书中的晶体学指示来说,单独的晶面由()代表,并且组晶面由{}代表。为了指示晶面的负指数,将负号放置在数字之前以取代放置在数字之上的“-”(横杠)。为了说明角度,采用全向角度是360°的系统。
首先,下文说明作为本实施例的碳化硅半导体器件的MOSFET的构造的要点。
如图1(A)所示,当在平面图中观察时,MOSFET100具有设置有晶体管元件(半导体元件)的元件区CL以及围绕元件区CL的终端区TM。如图1(B)中所示,元件区CL和终端区TM之间的边界可以包括曲折构造。在这种曲折构造中,从元件区CL向终端区TM突出的部分优选具有60°的角度DC。而且在这种曲折构造中,从终端区TM向元件区CL突出的部分优选具有60°的角度DT。60°是优选的,因为MOSFET100采用如上所述的具有六重对称性的六方晶体结构。优选地,如图1(C)中所示,沿曲折构造设置侧壁ST。邻近曲折构造设置底表面BT,且侧壁ST插入其间。应当注意将在下文说明侧壁ST和底表面BT的细节。
如图2中所示,MOSFET100是栅极沟槽型。MOSFET100包括碳化硅衬底SB、绝缘膜8T、栅极绝缘膜8C、栅电极9、层间绝缘膜10、源电极12、源极布线电极13、漏电极14以及背侧表面保护电极15。
碳化硅衬底SB由具有六方单晶结构的碳化硅制成并具有在厚度方向上彼此相反的正侧(第一侧)和背侧(第二侧)。在碳化硅衬底SB的正侧处的元件区CL中,提供沟槽6C以具有朝向正侧的渐宽的锥形。在碳化硅衬底SB的正侧处的终端区TM中设置阶地(terrace)6T。阶地6T由碳化硅衬底SB在碳化硅衬底SB的外周边方向上突出的背侧部分构造。
在碳化硅衬底SB的正侧处的元件区CL中,沟槽6C具有内壁,内壁的一部分提供了具有{0-33-8}或{0-11-4}的面取向的沟道表面SC。沟道表面SC是MOSFET100的沟道电流沿其流动的表面,并且由下述p型体层3的表面构成。沟道表面SC具有{0-33-8}或{0-11-4}的面取向。沟道表面SC优选具有(0-33-8),(30-3-8),(-330-8),(03-3-8),(-303-8)以及(3-30-8)的面取向中的至少一种。
在碳化硅衬底SB的正侧处的终端区TM中,阶地6T提供侧壁ST以及围绕侧壁ST的底表面BT。换言之,侧壁ST和底表面BT构成阶地6T。侧壁ST中的每一个都具有{0-33-8}或{0-11-4}的面取向。侧壁ST优选具有(0-33-8),(30-3-8),(-330-8),(03-3-8),(-303-8)以及(3-30-8)的面取向中至少一种。优选地,碳化硅衬底SB设置有具有所有上述六种面取向的侧壁ST。在这种情况下,(0-33-8)面、(30-3-8)面、(-330-8)面、(03-3-8)面、(-303-8)面以及(3-30-8)面可以布置为分别接触六边形的六个侧面以便构成侧壁ST。底表面BT具有{000-1}的面取向,优选地,具有(000-1)的面取向。
在元件区CL中,源电极12中的每一个设置在碳化硅衬底SB的正侧上。漏电极14设置在碳化硅衬底SB的背侧上。绝缘膜8T设置在侧壁ST和底表面BT上。
下文说明MOSFET100的详细构造。
如图2中所示,碳化硅衬底SB包括由碳化硅制成的单晶衬底1,以及外延形成在单晶衬底1的主表面MS上的碳化硅层。
单晶衬底1具有n导电类型,并且由具有六方单晶体结构的碳化硅制成。单晶衬底1的主表面MS具有相对于{000-1}具有5°或更小的偏离角的面取向,更优选地,相对于(000-1)具有5°或更小的偏离角。
碳化硅层具有基本上平行于单晶衬底1的主表面MS的主表面TS。碳化硅层包括:击穿电压保持层2,其是具有n型导电性的外延层;具有p型导电性的p型体层3;具有n型导电性的n型源极接触层4;具有p型导电性的接触区5;具有p型导电性的电场缓和区7;JTE(结终端延伸)区21;保护环区22;以及场中止区23。p型体层3、n型源极接触层4以及接触区5设置在元件区CL中。
JTE区21、保护环区22以及场中止区23形成在碳化硅衬底SB的正侧处的终端区TM中。当在平面图中观察时,设置JTE区21、保护环区22以及场中止区23中的每一个以围绕元件区CL。在提供图1(B)的曲折构造的情况下,JTE区21、保护环区22以及场中止区23中的每一个可以具有对应于上述曲折构造的曲折构造,或可以以直线的形式不严格地沿上述曲折构造延伸。JTE区21具有与p型体层3相同的导电类型并连接至p型体层3。当在平面图中观察时,保护环区22围绕JTE区21并具有不同于击穿电压保持层2的导电类型。当在平面图中观察时,场中止区23围绕保护环区22,具有与击穿电压保持层2相同的导电类型,并具有高于击穿电压保持层2的杂质浓度。
击穿电压保持层2形成在单晶衬底1的主表面MS上。p型体层3中的每一个形成在击穿电压保持层2上。在p型体层3上,形成n型源极接触层4。形成p型接触区5以被n型源极接触层4围绕。
在沟槽6C的内壁上,形成栅极绝缘膜8C。栅极绝缘膜8C在n型源极接触层4中的每一个的顶表面上延伸。在这种栅极绝缘膜8C上,形成栅电极9以填充沟槽6C的内部。栅电极9具有基本上与栅极绝缘膜8C在n型源极接触层4中的每一个的顶表面上的部分的顶表面等高的顶表面。
形成层间绝缘膜10以覆盖栅电极9以及栅极绝缘膜8C在n型源极接触层4中的每一个的顶表面上的部分。通过移除层间绝缘膜10和栅极绝缘膜8C的一部分,形成开口以暴露n型源极接触层4的一部分和p型接触区5。源电极12形成为与p型接触区5以及n型源极接触层4的该一部分接触,以便填充开口内部。源极布线电极13形成为与源电极12中的每一个的顶表面接触,以便在层间绝缘膜10的顶表面上延伸。而且,漏电极14形成在单晶衬底1的、与其上形成击穿电压保持层2的主表面相反的背表面上。这种漏电极14是欧姆电极。漏电极14具有与面对单晶衬底1的表面相反的、并且在其上形成背侧表面保护电极15的表面。
以下简要说明MOSFET100的操作。参考图2,当等于或小于阈值的电压被施加至栅电极9时,即当半导体器件处于截止状态时,p型体层3和n型导电性的击穿电压保持层2反向偏置。因此,其处于非导通状态。另一方面,当栅电极9被馈送有正电压时,反型层形成在p型体层3与栅极绝缘膜8C接触的区域附近的沟道区中。因此,n型源极接触层4和击穿电压保持层2彼此电连接。因此,电流在源电极12和漏电极14之间流动。
下文说明制造MOSFET100的方法。
如图3中所示,制备碳化硅衬底SB,其由具有六方单晶结构的碳化硅制成并在厚度方向上具有彼此相反的正侧和背侧。如下具体说明。
首先,制备由碳化硅形成的单晶衬底1。单晶衬底1具有六方单晶结构。而且,单晶衬底1设置有上述主表面MS。
随后,在主表面MS上,形成具有n型导电性的碳化硅的外延层。外延层作为击穿电压保持层2。借助采用CVD(化学气相沉积)方法的外延生长形成击穿电压保持层2,CVD(化学气相沉积)方法例如使用硅烷(SiH4)和丙烷(C3H8)的混合气体作为材料气体,并且使用氢气(H2)作为载气。在这种情况下,优选例如引入氮(N)或磷(P)作为施主杂质。这种击穿电压保持层2可以适于包含例如不小于5×1015cm-3且不大于5×1016cm-3的浓度的n型杂质。
随后,将离子注入击穿电压保持层2的顶表面层中,由此形成p型体层3和n型源极接触层4。在用于形成p型体层3的离子注入中,使用诸如铝(Al)的受主杂质。而且,将施主杂质的粒子注入由此具有形成在其中的p型体层3的击穿电压保持层2中,由此形成n型源极接触层4。一种示例性、可使用的施主杂质是磷等等。以此方式,形成碳化硅衬底SB。
随后,如图4中所示,设置沟槽16C以从元件区CL中的碳化硅衬底SB的正表面侧依次穿过n型源极接触层4以及p型体层3。沟槽16C的位置对应于将要设置沟槽6C的位置(图2)。而且,通过从终端区TM中的碳化硅衬底SB的正侧移除n型源极接触层4和p型体层3来提供阶地6T。阶地6T的位置对应于将要设置阶地6T的位置(图2)。如图4中所示,沟槽16C和阶地16T中的每一个都具有基本上平行于厚度方向的侧壁。下文说明形成沟槽16C和阶地16T的方法。
首先,掩膜层17形成在n型源极接触层4的顶表面(图3中的主表面TS)上。对于掩膜层17来说,可以使用诸如氧化硅膜的绝缘膜。对于形成掩膜层17的方法来说,例如可以采用以下工艺。首先,借助CVD方法等将氧化硅膜形成在n型源极接触层4的顶表面上。随后,借助光刻方法将具有预定开口图案的抗蚀剂膜(未示出)形成在氧化硅膜上。使用该抗蚀剂膜作为掩膜,通过蚀刻移除氧化硅膜的一部分。此后,移除抗蚀剂膜。因此,如图4中所示,形成具有与将要形成沟槽16C和阶地16T的区域一致的开口图案的掩膜层17。
随后,使用掩膜层17作为掩膜,借助蚀刻移除部分n型源极接触层4、p型体层3以及击穿电压保持层2。一种示例性的、可使用的蚀刻方法是反应离子蚀刻(RIE)或离子研磨。对于RIE来说,可以特别使用感应耦合等离子体(ICP)RIE。具体而言,例如可以采用使用SF6或SF6和O2的混合气体作为反应气体的ICP-RIE。借助这种蚀刻,形成沟槽16C和阶地16T。
随后,如图5中所示,沟槽6C形成在元件区CL中,并且阶地6T形成在终端区中。通过针对碳化硅衬底SB的正侧的热蚀刻形成上述结构。这里,术语“热蚀刻”旨在指示将要被蚀刻的目标在高温下暴露于蚀刻气体的蚀刻。热蚀刻基本上不具有物理蚀刻反应。借助沟槽6C的形成,具有{0-33-8}或{0-11-4}的面取向的沟道表面SC自发地形成在元件区CL处的碳化硅衬底SB中,从而作为沟槽6C的内壁的一部分。借助阶地6T的形成,侧壁ST和底表面BT自发地形成在终端区TM处的碳化硅衬底SB中。侧壁ST中的每一个都围绕元件区CL并具有{0-33-8}或{0-11-4}的面取向。底表面BT围绕包括元件区CL和侧壁ST的区域并具有{000-1}的面取向。
热蚀刻中的工艺气体包含卤族元素。更优选地,卤族元素是氯。替代氯或除氯之外,工艺气体可以包含四氟化碳和六氟化硫中至少一种。优选地,除包含卤族元素的气体之外,工艺气体进一步包含氧气。
下文说明工艺气体是氯气和氧气的混合气体的情况下的蚀刻过程。反应可能在表达为SiC+mO2+nCl2→SiClx+COy的反应方程式中满足0.5≤x≤2.0以及1.0≤y≤2.0的条件下进行,其中m,n,x和y是正数。反应在x=4且y=2的条件下进行最多。应当注意,上述m和n分别代表实际反应的氧气和氯气的量,并且因此不同于作为工艺气体供应的氧气和氯气的量。本发明人已经发现这种热蚀刻中的氧的流量对氯的流量的比值优选不小于0.1且不大于2.0。更优选地,这种比值的下限是0.25。在这种情况下,在碳化硅衬底SB中,对应于{0-33-8}或{0-11-4}面以及{000-1}面的表面可以更稳固地自发形成。
应当注意,工艺气体可以包含除诸如氯气和氧气的反应气体之外的载气。一种示例性、可使用的载气是氮气(N2)、氩气、氦气等等。
优选地,热蚀刻中的热处理温度不小于700℃且不大于1200℃。这种温度的下限更优选为800℃,进一步优选为900℃。而且,这种温度的上限更优选为1100℃,进一步优选为1000℃。在这种情况下,蚀刻速度可以是充分的有效值。当将热处理温度设定为不小于700℃且不大于1000℃时,蚀刻SiC的速度例如约为70μm/hr。当使用氧化硅(SiO2)作为各个掩膜层17的材料时,SiC对SiO2的选择比可以非常大。因此,由SiO2制成的掩膜层17在SiC的蚀刻过程中基本上不被蚀刻。
热蚀刻之后,借助蚀刻等移除掩膜层17。
随后,如图6中所示,形成接触区5、电场缓和区7、JTE区21、保护环区22以及场中止区23。它们可以通过执行使用掩膜的选择性离子注入而形成。
随后,执行活化退火以活化借助上述离子注入而注入的杂质。可以在由碳化硅制成的外延层的表面上不形成特殊的盖层的情况下执行活化退火。特别地,在采用上述{0-33-8}面或{0-11-4}面的情况下,即使当在其表面上未形成诸如盖层的保护膜的情况下执行活化退火处理时,表面特性都不会退化,并且可以保证充分的表面平坦性。
再次参考图2,绝缘膜8T形成在终端区TM处的碳化硅衬底SB上。因此,绝缘膜8T形成在侧壁ST和底表面BT上。而且,栅极绝缘膜8C形成在元件区CL处的碳化硅衬底SB上。可以共同形成绝缘膜8T和栅极绝缘膜8C。绝缘膜8T和栅极绝缘膜8C中的每一个例如都可以通过热氧化碳化硅衬底SB的正侧而形成。
随后,栅电极9形成在栅极绝缘膜8C上,以便填充沟槽6C的内部。对于形成栅电极9的方法来说,例如可以使用以下方法。首先,采用溅射方法等以在栅极绝缘膜8C上形成导体膜。导体膜是延伸至沟槽6C的内部以及p型接触区5上的区域的栅电极。导体膜可以由诸如金属的任何材料制成,只要材料具有导电性即可。此后,使用诸如回蚀方法或CMP(化学机械抛光)的适当方法移除导体膜形成在除沟槽6C内部之外的区域上的部分。因此,保留填充沟槽6C内部的导体膜以构成栅电极9。
随后,形成层间绝缘膜10以覆盖栅电极9的顶表面以及栅极绝缘膜8C暴露在p型接触区5上的顶表面。层间绝缘膜10可以由任何材料制成,只要材料是绝缘性的即可。而且,使用光刻方法在层间绝缘膜10上形成具有图案的抗蚀剂膜(未示出)。抗蚀剂膜设置有形成为与p型接触区5上的区域一致的开口图案。
使用这种抗蚀剂膜作为掩膜,借助蚀刻移除层间绝缘膜10和栅极绝缘膜8C的一部分。因此,形成开口以延伸穿过层间绝缘膜10和栅极绝缘膜8C。开口中的每一个都具有暴露n型源极接触层4的一部分和接触区5的底部。此后,用作源电极12的导体膜形成为填充开口内部并覆盖上述抗蚀剂膜的顶表面。此后,使用化学溶液等移除抗蚀剂膜,由此同时移除(剥离)导体膜形成在抗蚀剂膜上的部分。因此,填充开口内部的导体膜构成源电极12。这种源电极12是与接触区5和n型源极接触层4接触的欧姆电极。
而且,漏电极14形成在单晶衬底1的背表面上(与其上形成击穿电压保持层2的主表面相反的表面)。漏电极14可以由任何材料制成,只要该材料允许与单晶衬底1的欧姆接触即可。
随后,采用溅射方法等形成源极布线电极13和背侧表面保护电极15。源极布线电极13与源电极12的各个顶表面接触,并在层间绝缘膜10的顶表面上延伸。背侧表面保护电极15形成在漏电极14的表面上。
以此方式,制成MOSFET100(图2)。
根据本实施例,在源电极12和漏电极14之间的部分处的碳化硅衬底SB的表面中,借助热蚀刻提供侧壁ST和底表面BT。因此,经由碳化硅衬底SB的表面在源电极12和漏电极14之间流动的泄漏电流流过侧表面ST和底表面BT。热蚀刻的使用为各个侧壁ST提供{0-33-8}或{0-11-4}的面取向,且为底表面BT提供{000-1}的面取向。因此,在绝缘膜8T与侧壁ST和底表面BT中的每一个之间的界面具有低界面态密度。因此,抑制由于界面态的存在而导致的电流的产生,由此可以抑制在电极之间,即在源电极12和漏电极14之间的泄漏电流。
热蚀刻的步骤包括在元件区CL处的碳化硅衬底SB中形成具有{0-33-8}或{0-11-4}的面取向的沟道表面SC的步骤。因此,可以提高沿沟道表面SC的载流子迁移率,由此抑制沟道电阻。以此方式,可以使MOSFET100的导通电阻变小。
而且,形成沟道表面的步骤通过形成设置有包括沟道表面的内壁的沟槽6C来执行。通过采用该沟槽结构,沟道可以以高密度设置在相同区域中。以此方式,可以获得更大电流。而且,因为沟槽6C的最终形状通过热蚀刻形成,因此可以避免在沟槽6C的角落部分NR(图5)中形成子沟槽,子沟槽是局部形成得较深的区域。应当注意,这种子沟槽可能在借助具有物理蚀刻反应的蚀刻方法形成沟槽的最终形状时形成。例如,这种子沟槽可以在借助RIE形成时被观察到。
而且,使用包含卤族元素的工艺气体执行热蚀刻步骤。因此,沟槽6C的侧壁自发地形成为对应于所需晶面,即{0-33-8}面或{01-1-4}面。
而且,通过使用SiO2用于掩膜层17的材料,可以获得针对SiC的高选择比,由此可以稳固地形成沟槽6C。
更优选地,卤族元素是氯。由于上述相同原因,氯气的使用使得更能确保对应于所需晶面的表面的形成。工艺气体可以包含四氟化碳和六氟化硫。而且以此方式,沟槽6C的侧壁自发地形成为对应于所需晶面。
优选地,工艺气体包含氧气。因此,在热蚀刻过程中引入氧,因此可以随SiC同时移除形成在SiC表面上的碳薄膜层(SiC中的剩余C原子)。
应当注意在本实施例中,同时形成终端区TM中的绝缘膜8T以及元件区CL中的栅极绝缘膜8C,但是可以分别形成终端区中的绝缘膜和元件区中的栅极绝缘膜。
而且,在终端区TM中,提供JTE区21,各个保护环区22以及场中止区23,但可以省略它们中的至少一个。
而且,MOSFET100是n沟道型,但是在载流子迁移率无需与n沟道型中的载流子迁移率一样大时,碳化硅半导体器件可以是p沟道型。在这种情况下,可以采用上述实施例中的n型导电性和p型导电性彼此替代的构造。
而且,碳化硅半导体器件可以是除MOSFET之外的MISFET(金属绝缘体半导体场效应晶体管)或可以是除MISFET之外的碳化硅半导体器件。一种除MISFET之外的示例性碳化硅半导体器件是IGBT(绝缘栅双极晶体管)。
本文公开的实施例在各个方面都是说明性而非限制性的。本发明的权利要求的范围由权利要求项限定,而不是由上述实施例限定,且旨在涵盖等效于权利要求项的范围和含义内的任何变型。
附图标记列表
1:单晶衬底;2:击穿电压保持层;3:p型体层;4:n型源极接触层;5:接触区;6C:沟槽;6T:阶地;7:电场缓和区;8C:栅极绝缘膜;8T:绝缘膜;9:栅电极;10:层间绝缘膜;12:源电极;13:源极布线电极;14:漏电极;15:背侧表面保护电极;17:掩膜层;21:JTE区;22:保护环区;23:场中止区;BT:底表面;CL:元件区;SB:碳化硅衬底;SC:沟道表面;ST:侧壁;TM:终端区。
Claims (10)
1.一种制造碳化硅半导体器件(100)的方法,所述碳化硅半导体器件(100)在平面图中观察时具有设置有半导体元件的元件区(CL)以及围绕所述元件区的终端区(TM),并且所述方法包括以下步骤:
制备碳化硅衬底,所述碳化硅衬底由具有六方单晶结构的碳化硅制成并且具有在厚度方向上彼此相反的第一侧和第二侧;
热蚀刻所述碳化硅衬底的所述第一侧以便在所述终端区处的所述碳化硅衬底中形成侧壁(ST)和底表面(BT),所述侧壁(ST)围绕所述元件区并且具有{0-33-8}和{0-11-4}中的一种的面取向,所述底表面(BT)围绕包括所述元件区和所述侧壁的区域并且具有{000-1}的面取向;
在所述侧壁和所述底表面上形成绝缘膜(8T);
在所述元件区处的所述碳化硅衬底的所述第一侧上形成第一电极(12);以及
在所述碳化硅衬底的所述第二侧上形成第二电极(14)。
2.根据权利要求1所述的制造碳化硅半导体器件的方法,其中,所述热蚀刻的步骤包括在所述元件区处的所述碳化硅衬底中形成沟道表面(SC)的步骤,所述沟道表面(SC)具有{0-33-8}和{0-11-4}中的一种的面取向。
3.根据权利要求2所述的制造碳化硅半导体器件的方法,其中,形成所述沟道表面的步骤是通过形成设置有包括所述沟道表面的内壁的沟槽(6C)来执行的。
4.根据权利要求1-3中的任何一项所述的制造碳化硅半导体器件的方法,其中,所述热蚀刻的步骤是使用包含卤族元素的工艺气体来执行的。
5.根据权利要求4所述的制造碳化硅半导体器件的方法,其中,所述卤族元素是氯。
6.根据权利要求4或5所述的制造碳化硅半导体器件的方法,其中,所述工艺气体包含四氟化碳和六氟化硫中的至少一种。
7.根据权利要求4-6中的任何一项所述的制造碳化硅半导体器件的方法,其中,所述工艺气体包含氧气。
8.一种碳化硅半导体器件(100),所述碳化硅半导体器件(100)在平面图中观察时具有设置有半导体元件的元件区(CL)以及围绕所述元件区的终端区(TM),所述碳化硅半导体器件包括:
碳化硅衬底,所述碳化硅衬底由具有六方单晶结构的碳化硅制成并且具有在厚度方向上彼此相反的第一侧和第二侧,所述碳化硅衬底的所述第一侧在所述终端区中设置有侧壁(ST)和底表面(BT),所述侧壁(ST)围绕所述元件区并且具有{0-33-8}和{0-11-4}中的一种的面取向,所述底表面(BT)围绕所述侧壁并且具有{000-1}的面取向;
绝缘膜(8T),所述绝缘膜(8T)设置在所述侧壁和所述底表面上;
第一电极(12),所述第一电极(12)设置在所述元件区处的所述碳化硅衬底的所述第一侧上;以及
第二电极(14),所述第二电极(14)设置在所述碳化硅衬底的所述第二侧上。
9.根据权利要求8所述的碳化硅半导体器件,其中,在所述元件区中,所述碳化硅衬底的所述第一侧设置有沟道表面(SC),所述沟道表面(SC)具有{0-33-8}和{0-11-4}中的一种的面取向。
10.根据权利要求9所述的碳化硅半导体器件,其中,所述沟道表面是设置在所述元件区处的所述碳化硅衬底的所述第一侧中的沟槽(6C)的内壁的一部分。
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