CN103594441B - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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Publication number
CN103594441B
CN103594441B CN201210519648.0A CN201210519648A CN103594441B CN 103594441 B CN103594441 B CN 103594441B CN 201210519648 A CN201210519648 A CN 201210519648A CN 103594441 B CN103594441 B CN 103594441B
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groove
side wall
semiconductor substrate
molding compound
passivation layer
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CN103594441A (zh
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王宗鼎
郑荣伟
李柏毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体封装件，包括位于半导体衬底的钝化层、位于钝化层的凸块以及位于钝化层上方并覆盖凸块的下部的模塑料层。模塑料层覆盖钝化层的侧壁。本发明还提供了半导体封装件的制造方法。

Description

半导体封装件及其制造方法
技术领域
本发明涉及半导体封装件，更具体地，涉及制造半导体封装件的方法。
背景技术
实际上，现代集成电路由以百万计的有源器件(诸如晶体管和电容器)制成。这些器件最初彼此隔离，但随后互连在一起以形成功能电路。典型的互连结构包括诸如金属线(布线)的横向互连件和诸如通孔和接触件的垂直互连件。互连件越来越多地决定现代集成电路的性能和密度的限制。在互连结构的顶部，在相应芯片的表面上形成和暴露接合焊盘。通过接合焊盘进行电连接以将芯片连接至封装衬底或另一个管芯。接合焊盘可以用于引线接合或倒装芯片接合。倒装芯片封装件利用凸块建立芯片的输入/输出(I/O)焊盘和封装件的衬底或引线框之间的电接触件。在结构上，凸块结构常常指的是凸块以及位于凸块和I/O焊盘之间的“凸块底部金属化”层(UBM)。当前晶圆级芯片尺寸封装(WLCSP)由于其低成本和相对简单的工艺而被广泛使用，并且植球或落球(ball drop)工艺用于WLCSP技术中。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体封装件，包括：芯片，包括：半导体衬底；钝化层，位于所述半导体衬底上方；和凸块，位于所述钝化层上方；以及模塑料层，位于所述钝化层上方并覆盖所述凸块的下部；其中，所述模塑料层覆盖所述钝化层的侧壁。
在半导体封装件中，所述半导体衬底包括紧邻所述钝化层的所述侧壁的上侧壁、紧邻所述半导体衬底的背面的下侧壁以及从所述上侧壁延伸至所述下侧壁的表面区域，并且所述上侧壁和所述表面区域在所述半导体衬底中形成凹陷区域。
在半导体封装件中，所述模塑料层覆盖所述半导体衬底的所述上侧壁和所述表面区域。
在半导体封装件中，所述凹陷区域填充有所述模塑料层。
在半导体封装件中，所述半导体衬底的所述下侧壁与所述模塑料层的侧壁基本对齐。
在半导体封装件中，所述半导体衬底的所述上侧壁与所述钝化层的所述侧壁基本对齐。
在半导体封装件中，所述模塑料层覆盖所述半导体衬底的所述下侧壁。
在半导体封装件中，所述凸块的上部突出到所述模塑料层的顶面之外。
根据本发明的另一方面，提供了一种形成半导体封装件的方法，包括：在半导体衬底上方形成钝化层，所述半导体衬底包括第一芯片区、第二芯片区以及位于所述第一芯片区和所述第二芯片区之间的划线区；在所述第一芯片区和所述第二芯片区中的至少一个上的所述钝化层的上方形成凸块；形成穿过所述划线区上的所述钝化层的凹槽；形成模塑料层以覆盖所述钝化层和所述凸块的下部并填充所述凹槽；以及在所述划线区上实施切割工艺以分离所述第一芯片区和所述第二芯片区。
在该方法中，所述凹槽延伸至所述半导体衬底位于所述划线区上的部分。
在该方法中，所述凹槽的形成包括：实施第一开槽工艺以形成穿过所述钝化层并以第一深度延伸至所述划线区上的所述半导体衬底的所述凹槽，其中，所述方法进一步包括：实施第二开槽工艺以形成位于所述凹槽下方的另一个凹槽，所述另一个凹槽以第二深度延伸至所述划线区上的所述半导体衬底。
在该方法中，所述凹槽具有第一宽度，所述另一个凹槽具有第二宽度，并且所述第一宽度大于所述第二宽度。
在该方法中，所述模塑料层的形成包括在所述半导体衬底上施加液态模塑料。
该方法进一步包括：在实施所述切割工艺之前，减薄所述半导体衬底。
根据本发明的又一方面，提供了一种半导体封装件，包括：芯片，包括：衬底；介电层，位于所述衬底上方；接触焊盘，位于所述介电层上方；钝化层，位于所述接触焊盘上方；以及凸块，位于所述钝化层上方；以及模塑料层，位于所述钝化层上方并覆盖所述凸块的下部；其中，所述模塑料层覆盖所述钝化层和所述介电层的侧壁。
在该半导体封装件中，所述衬底包括紧邻所述介电层的所述侧壁的上侧壁、紧邻所述半导体衬底的背面的下侧壁以及从所述上侧壁延伸至所述下侧壁的表面区域，并且所述模塑料层覆盖所述上侧壁和所述表面区域。
在该半导体封装件中，所述上侧壁和所述表面区域在所述半导体衬底中形成凹陷区域，并且所述模塑料层填充所述凹陷区域。
在该半导体封装件中，所述半导体衬底的所述上侧壁与所述介电层的所述侧壁基本对齐。
在该半导体封装件中，所述模塑料层覆盖所述半导体衬底的所述下侧壁。
在该半导体封装件中，所述半导体衬底的侧壁与所述模塑料层的侧壁基本对齐。
附图说明
图1A至图6是示出根据实施例制造半导体封装件的方法的示意图；
图7至图12是示出根据实施例制造半导体封装件的方法的示意图；以及
图13至图15是示出根据实施例制造半导体封装件的方法的示意图。
具体实施方式
下面详细讨论了本发明的实施例的制造和使用。然而，应该理解，本实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出制造和使用实施例的具体方式，并且没有限定本发明的范围。本文中所述的实施例涉及用于半导体器件的凸块。如下文中所讨论，公开了为了将一个衬底附接至另一个衬底而使用凸块的实施例，其中，每个衬底都可以是管芯、晶圆、中介衬底、印刷电路板、封装衬底等，因此允许管芯与管芯、晶圆与管芯、晶圆与晶圆、管芯或晶圆与中介衬底或印刷电路板或封装衬底等的附接。在各个附图和所有说明性实施例中，相同的参考标号用于指定相同的元件。
现在将附图中示出的具体示例性实施例作为参考。只要可能，在附图和描述中使用相同的参考标号就指的是相同或类似部件。在附图中，为了清楚和方便，形状和厚度可以被放大。具体地，描述涉及根据本发明形成的装置的部分或更直接地与该装置协作的元件。应该理解，未具体示出或描述的元件可以采用本领域技术人员公知的各种形式。此外，当层被称为位于另一层上或位于衬底“上”时，该层可以直接位于其他层上或位于衬底上，或者也可以具有中间层。整个本说明书中引用“一个实施例”或“实施例”表示本发明的至少一个实施例包括结合所述实施例所描述的特定部件、结构或特征。因此在本说明书的各个位置处出现的短语“在一个实施例中”或“在实施例中”不一定指同一个实施例。而且，在一个或多个实施例中可以以任何合适的方式组合特定部件、结构或特征。应该理解，以下附图没有按比例绘制；而这些附图仅是为了进行说明。
图1至图6是示出根据实施例制造半导体封装件的方法的示意图。
参考图1A和图1B，提供包括多个具有电路和在其上制造的凸块的芯片(或管芯)10A和10B的半导体晶圆100。图1A是根据实施例的具有芯片10A和10B的半导体晶圆100的俯视图，而图1B是沿在图1A中所示的线A-A截取的截面图。半导体晶圆100包括通过两组相交划线区12相互分离开的芯片阵列。一组划线区12沿第一方向延伸而第二组划线区12沿第二方向延伸。根据实施例，芯片10A和10B具有基本相同的结构。截面图示出了形成在第一芯片区I上的第一芯片10A和形成在第二芯片区II上的第二芯片10B，并且芯片区I和II通过划线区12分离开。下面详细描述形成在芯片区I和II上的芯片10A和10B的结构。
在制造芯片10A和10B期间，在半导体衬底14上实施半导体工艺以形成电路、介电层16、接触焊盘18、第一钝化层20、第二钝化层22、凸块底部金属化(UBM)层24以及凸块26。在至少一个实施例中，还形成在划线区12之上延伸的层16、20以及22。例如，半导体衬底14可以包括绝缘体上半导体(SOI)衬底的体硅层、掺杂的或未掺杂层或有源层。还可以使用诸如多层或梯度衬底的其他衬底。形成在半导体衬底14中的电路(未示出)可以是适合特定应用的任意类型的电路。在一些实施例中，电路包括具有位于电器件上方一个或多个介电层的电器件。金属层可以形成在介电层之间以在电器件之间的传送电信号。电器件也可以形成在一个或多个介电层中。例如，电路可以包括互连的各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件(诸如，晶体管、电容器、电阻器、二极管、光电二极管、熔丝等)以实施一个或多个功能件。功能件可以包括存储结构、处理结构、传感器、放大器、配电装置、输入/输出电路等。本领域普通技术人员应该理解，提供以上实例仅是为了说明的目的以进一步解释一些说明性实施例的应用，并且不是为了以任何方式限定本发明。对于给定的应用，可以适当地使用其他电路。
例如，介电层16可以通过任意合适的方法(诸如旋涂、化学汽相沉积(CVD)和/或等离子增强CVD(PECVD)等)由低介电常数(低k)的介电材料形成，诸如，掺磷硅玻璃(PSG)、掺硼磷硅玻璃(BPSG)、掺氟硅玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的合成物、它们的组合等。在一些实施例中，介电层16可以包括多个介电材料层。金属线和/或通孔(未示出)可以形成在介电层16内部以提供到达形成在半导体衬底14中的电路的电连接件。在一些实施例中，最上层的介电层由诸如氮化硅、氧化硅、未掺杂硅玻璃等的介电材料形成。
接触焊盘18形成在介电层16上以电连接介电层16内部的金属线或通孔。在一些实施例中，接触焊盘18可以由铝、铝铜、铝合金、铜、铜合金等形成。诸如第一钝化层20和第二钝化层22的一个或多个钝化层形成在介电层16上方并且进行图案化以分别暴露接触焊盘18的部分。在一些实施例中，第一钝化层20通过诸如CVD、PVD等的任意合适的方法由介电材料形成，诸如，未掺杂硅玻璃(USG)、氮化硅、氧化硅、氮氧化硅或非多孔材料。在实施例中，形成第一钝化层20以覆盖每个接触焊盘18的外围部分，并通过第一钝化层20中的开口暴露每个接触焊盘18的中心部分。第一钝化层20可以是单层或层压层。第二钝化层22形成在第一钝化层20上方并进行图案化以分别暴露接触焊盘18的部分。在一些实施例中，例如，第二钝化层22可以是聚合物层，将该聚合物层图案化以形成通过其暴露接触焊盘18的开口。在一些实施例中，聚合物层由诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等的聚合物材料形成，但也可以使用其他相对较软的、通常为有机的介电材料。形成方法包括旋涂或其他方法。
UBM层24形成在相应的接触焊盘18的暴露的部分上。在一些实施例中，UBM层24紧邻接触焊盘18延伸至第二钝化层22的表面。UBM层24的形成方法包括光刻胶涂覆、光刻、湿蚀刻或干蚀刻等。在实施例中，UBM层24包括含有钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、铜(Cu)、铜合金、镍(Ni)、锡(Sn)、金(Au)或它们的组合的至少一个金属化层。在一些实施例中，UBM层24包括至少一个含Ti层和至少一个含Cu层。
凸块26形成在相应的UBM层24上方。凸块26可以是由含有焊料、Cu、Ni或Au中的的至少一种的导电材料形成的球形凸块或柱形凸块。在实施例中，凸块26是通过将焊料球附接至UBM层24然后热回流焊料材料形成的焊料凸块。在实施例中，通过使用光刻技术和随后的回流工艺电镀镀焊料层来形成焊料凸块。在实施例中，焊料凸块的直径大于约200μm。在一些实施例中，焊料凸块包括无铅预焊料层、SnAg或焊料材料(包括锡、铅、银、铜、镍、铋或它们的组合的合金)。
参考图2A和图2B，在晶圆100上方实施开槽工艺以在划线区12上形成凹槽28。图2A是根据实施例具有凹槽28的半导体晶圆100的俯视图，而图2B是沿在图2A中所示的线B-B所截取的截面图。开槽工艺移除位于划线区12中的第二钝化层22、第一钝化层20、介电层16以及半导体衬底14的部分。在实施例中，通过用激光束照射划线区12形成凹槽28。根据一个实施例，可以在划线区12上以连续的方式形成晶圆100上的凹槽28，使得凹槽28的平面布局基本类似于相交划线区12的平面布局。例如，第一组凹槽28沿第一方向延伸而第二组凹槽沿第二方向延伸。在一些实施例中，晶圆100上的凹槽28可以以不连续的方式形成在划线区12上并以距离相互间隔开。因此，至少一个凹槽28形成在两个紧接芯片区I和II之间的划线区12上。在实施例中，宽度为W1的凹槽28穿过层22、20和16并到达半导体衬底14的深度D1。深度D1小于半导体衬底14的厚度T1，并且宽度W1小于划线区12的宽度W2。在实施例中，深度D1等于或大于约10μm。
接下来，如图3所示，模塑料层30施加在图2B所示的结构上以覆盖第二钝化层22并填充凹槽28，其中，每个凸块26都部分地掩埋在模塑料层30中。在实施例中，凸块26包括下部26L和上部26U，并且模塑料层30与凸块26的下部26L物理接触，而凸块26的上部26U暴露并突出到模塑料层30的顶面30A上。在一些实施例中，模塑料层30可以与第二钝化层22和/或UBM层24物理接触。在一些实施例中，模塑料层30的厚度(T2)介于凸块26的高度(H)的约1/4至3/4之间。在实施例中，通过施加液态模塑料并实施固化工艺以固化和凝固液态模塑料来形成模塑料层30。在一些实施例中，剥离膜(release film)或软材料可以施加在液态模塑料上。压力施加在液态模塑料上的剥离膜上，使得凸块26的部分被压入剥离膜中。此外，施加在剥离膜上的压力可以向下推动一些液态模塑料。在压力施加在推动凸块和液态模塑料的剥离膜上的同时，可以实施固化以固化和凝固液态模塑料。此后，从模塑料层30上剥掉剥离膜。
然后，如图4所示，上下翻转晶圆100并附接至胶带32，随后在半导体衬底14的背面实施研磨工艺34，以减薄半导体衬底14的厚度。在实施例中，减薄的衬底14”的厚度T3小于厚度T1，但大于凹槽28的深度D1。
如图5所示，在去除胶带32之后，在划线区12上实施切割工艺以从晶圆100中分离单个芯片10。如图5所示，虚线36指示在划线区12上实施的切割工艺，该切割工艺穿过凹槽28内的模塑料层30并穿过凹槽28下方的半导体衬底14。在切割工艺之后，图6示出了示例性独立芯片10。模塑料层30覆盖凸块26的下部26L、第二钝化层22的表面以及层22、20和16的侧壁S22、S20和S16。此外，在独立芯片10中，减薄的衬底14”包括紧邻介电层16的侧壁S16的上侧壁S1、紧邻减薄的衬底14”的背面的下侧壁S2以及从上侧壁S1延伸至下侧壁S2的表面区域S3。上侧壁S1和表面区域S3是通过开槽工艺制造的凹槽28的部分，生成处于减薄的衬底14”的边缘处的凹陷区域14R。通过切割工艺形成下侧壁S2。
在实施例中，上侧壁S1与层16、20和22的侧壁S16、S20和S22的至少一个基本对齐，而下侧壁S2与模塑料层30的侧壁S30基本对齐。在实施例中，上侧壁S1的深度与深度D1基本相同。在实施例中，模塑料层30覆盖减薄的衬底14”的上侧壁S1和表面区域S3。在实施例中，模塑料层30填充减薄的衬底14”的凹陷区域14R。可以在许多不同的情况下使用独立芯片10。例如，独立芯片10可以用于管芯与管芯的接合结构、管芯与晶圆接合结构、管芯级封装件等中。在一些实施例中，将独立芯片10上下翻转并附接至另一个衬底，例如，芯片、中间板、印刷电路板(PCB)或任何其他封装衬底。
根据图6所述的实施例，模塑料层30完全覆盖紧邻芯片边缘的半导体衬底14的上侧壁S1和表面区域S3以提供具有较强的粘合强度的凸块26以消除切割工艺期间的芯片开裂问题。模塑料层30也覆盖凸块26的下部26L，从而可以提供用于附接至另一个衬底的较强的封装结构。而且，在芯片切割工艺之前使用激光开槽工艺可以消除或减少介电层16、钝化层20和22以及芯片10的边缘中的初始开裂点，使得改善了器件的可靠性。
图7至图12是示出根据实施例制造半导体封装件的方法的示意图。除非另有说明，否则这些实施例中的参考标号表示与在图1至图6所示的实施例中的相同元件。
参考图7，在晶圆100上实施第一开槽工艺以在划线区12上形成第一凹槽28a。第一开槽工艺去除在划线区12内的第二钝化层22、第一钝化层20、介电层16以及半导体衬底14的部分。在实施例中，宽度为W1的凹槽28a穿过层22、20和16并到达半导体衬底14的深度D1。深度D1小于半导体衬底14的厚度T1，并且宽度W1小于划线区12的宽度W2。在实施例中，深度D1等于或大于约10μm。
接下来，如图8所示，在晶圆100上实施第二开槽工艺以在划线区12上的第一凹槽28a内部形成第二凹槽28b。第二开槽工艺去除位于第一凹槽28a下方的半导体衬底14的部分。在实施例中，宽度为W3的第二凹槽28b穿过半导体衬底14并到达半导体衬底14的深度D2。在一些实施例中，深度D2满足公式：D1＜D2＜T1，而宽度W3满足公式W3＜W1＜W2。
接下来，如图9所示，模塑料层30施加在图8所示的生成的结构上以覆盖第二钝化层22并填充凹槽28a和28b，其中，各个凸块26都部分地掩埋在模塑料层30中。在实施例中，模塑料层30与凸块26的下部26L物理接触，而凸块26的上部26U被暴露并突出到模塑料层30的顶面30A之外。在一些实施例中，模塑料层30可以与第二钝化层22和/或UBM层24物理接触。
然后，如图10所示，将晶圆100上下翻转并附接至胶带32，随后在半导体衬底14的背面实施研磨工艺34，以减薄半导体衬底14的厚度。减薄的衬底14”的厚度T3小于厚度T1。在实施例中，厚度T3基本等于第二凹槽28b的深度D3，使得在减薄的衬底14”的背面上暴露模塑料层30。在一些实施例中，厚度T3大于第二凹槽28b的深度D3。在去除胶带32之后，在划线区12上实施切割工艺以从晶圆100上分离独立芯片10。如图11所示，虚线36指示在划线区12上实施的切割工艺，该切割工艺穿过凹槽28a和28b内的模塑料层30并穿过位于凹槽28b下方的半导体衬底14。
在切割工艺之后，如图12所示，示出了独立芯片10。模塑料层30覆盖凸块26的下部26L、第二钝化层22的表面以及层22、20和16的侧壁S22、S20和S16。此外，在独立芯片10中，减薄的衬底14”包括紧邻介电层16的侧壁S16的上侧壁S1、紧邻减薄的衬底14”的背面的下侧壁S2，以及从上侧壁S1延伸至下侧壁S2的表面区域S3。上侧壁S1和表面区域S3是通过第一开槽工艺制造的第一凹槽28a的部分，在减薄的衬底14”的边缘处生成凹陷区域14R。下侧壁S2是通过第二开槽工艺制造的第二凹槽28b的部分。在实施例中，模塑料层30覆盖减薄的衬底14”的上侧壁S1、表面区域S3以及下侧壁S2。在实施例中，模塑料层30覆盖并填充减薄的衬底14”的凹陷区域14R。
图13至图15是示出根据实施例制造半导体封装件的方法的示意图。除非另有说明，否则这些实施例中的参考标号表示与在图1至图6所示的实施例中类似的元件。
参考图13，在晶圆100上实施开槽工艺以在划线区12上形成凹槽28c。开槽工艺去除划线区12内的第二钝化层22、第一钝化层20以及介电层16的部分，并且暴露半导体衬底14的表面。在实施例中，宽度为W1的凹槽28c穿过层22、20和16。宽度W1小于划线区12的宽度W2。
接下来，如图14所示，模塑料层30施加在生成的结构上以覆盖第二钝化层22并填充凹槽28c，其中，每个凸块26部分地掩埋在模塑料层30中。在实施例中，模塑料层30与凸块26的下部26L物理接触，而凸块26的上部26U被暴露并突出到模塑料层30的顶面30A之外。在一些实施例中，模塑料层30可以与第二钝化层22和/或UBM层24物理接触。
在减薄工艺和切割工艺之后，如图15所示，示出了独立芯片10。模塑料层30覆盖凸块26的下部26L、第二钝化层22的表面以及层22、20和16的侧壁S22、S20和S16。此外，在独立芯片10中，减薄的衬底14”的侧壁S2与模塑料层30的侧壁S30基本上对齐。
根据实施例，半导体封装件包括位于半导体衬底上方的钝化层、位于钝化层上方的凸块以及位于钝化层上方并覆盖凸块下部的模塑料层。模塑料层覆盖钝化层的侧壁。
根据一些实施例，形成半导体封装件的方法包括：在半导体衬底上方形成钝化层，其中，该半导体衬底包括第一芯片区、第二芯片区以及位于第一芯片区和第二芯片区之间的划线区。然后，在第一芯片区和第二芯片区的至少一个上的钝化层上方形成凸块。接下来，形成的凹槽穿过划线区上的钝化层。然后，形成模塑料层以覆盖钝化层和凸块的下部并填充凹槽。在划线区上实施切割工艺之后，第一芯片区与第二芯片区分离。
根据一些实施例，半导体封装件包括位于衬底上方介电层、位于介电层上方接触焊盘、位于接触焊盘上方的钝化层、位于钝化层上方的凸块以及位于钝化层上方并覆盖凸块下部的模塑料层。模塑料层覆盖钝化层和介电层的侧壁。
虽然已经参考其示例性实施例具体地示出和描述了本发明，本领域技术人员应该理解，可以存在本发明的许多实施例的变型例。尽管已经详细描述了实施例及其特征，但应该理解，在不背离本实施例的主旨和范围的情况下，可以在本文中进行各种改变、替换和更改。
以上方法实施例示出了示例性步骤，但不一定要求按所示顺序实施这些示例性步骤。根据本发明的实施例的主旨和范围，可以适当地增加、替换步骤、改变步骤的顺序和/或去除步骤。结合不同权利要求和/或不同实施例的实施例在本发明的范围内，并本领域技术人员在审阅本发明以后，容易理解这些实施例。

Claims (18)

1.一种半导体封装件，包括：
芯片，包括：
具有第一厚度的半导体衬底，所述半导体衬底包括凹槽，其中，所述凹槽包括：
具有第一宽度和第一深度的第一凹槽；和
具有第二宽度和第二深度的第二凹槽，其中，所述第二深度大于所述第一深度，且所述第二深度小于第一厚度；
钝化层，位于所述半导体衬底上方；和
凸块，位于所述钝化层上方；以及
模塑料层，位于所述钝化层上方并覆盖所述凸块的下部；
其中，所述模塑料层覆盖所述钝化层的侧壁，所述第二凹槽填充有模塑料层，并且所述第一凹槽填充有模塑料层。
2.根据权利要求1所述的半导体封装件，其中，所述半导体衬底包括紧邻所述钝化层的所述侧壁的上侧壁、紧邻所述半导体衬底的背面的下侧壁以及从所述上侧壁延伸至所述下侧壁的表面区域，并且所述上侧壁和所述表面区域在所述半导体衬底中形成凹陷区域。
3.根据权利要求2所述的半导体封装件，其中，所述模塑料层覆盖所述半导体衬底的所述上侧壁和所述表面区域。
4.根据权利要求2所述的半导体封装件，其中，所述凹陷区域填充有所述模塑料层。
5.根据权利要求2所述的半导体封装件，其中，所述半导体衬底的所述下侧壁与所述模塑料层的侧壁对齐。
6.根据权利要求2所述的半导体封装件，其中，所述半导体衬底的所述上侧壁与所述钝化层的所述侧壁对齐。
7.根据权利要求2所述的半导体封装件，其中，所述模塑料层覆盖所述半导体衬底的所述下侧壁。
8.根据权利要求1所述的半导体封装件，其中，所述凸块的上部突出到所述模塑料层的顶面之外。
9.一种形成半导体封装件的方法，包括：
在具有第一厚度的半导体衬底上方形成钝化层，所述半导体衬底包括第一芯片区、第二芯片区以及位于所述第一芯片区和所述第二芯片区之间的划线区；
在所述第一芯片区和所述第二芯片区中的至少一个上的所述钝化层的上方形成凸块；
形成穿过所述划线区上的所述钝化层的凹槽，其中，所述凹槽延伸至所述半导体衬底位于所述划线区上的部分，所述凹槽的形成包括：
实施第一开槽工艺以形成穿过所述钝化层并以第一深度延伸至所述划线区上的所述半导体衬底的所述凹槽，其中，所述方法进一步包括：
实施第二开槽工艺以形成位于所述凹槽下方的另一个凹槽，所述另一个凹槽以第二深度延伸至所述划线区上的所述半导体衬底，其中，所述第二深度大于所述第一深度，且第二深度小于第一厚度；
形成模塑料层以覆盖所述钝化层和所述凸块的下部并填充所述凹槽；以及
在所述划线区上实施切割工艺以分离所述第一芯片区和所述第二芯片区。
10.根据权利要求9所述的方法，其中，所述凹槽具有第一宽度，所述另一个凹槽具有第二宽度，并且所述第一宽度大于所述第二宽度。
11.根据权利要求9所述的方法，其中，所述模塑料层的形成包括在所述半导体衬底上施加液态模塑料。
12.根据权利要求9所述的方法，进一步包括：在实施所述切割工艺之前，减薄所述半导体衬底。
13.一种半导体封装件，包括：
芯片，包括：
具有第一厚度的衬底，所述衬底包括凹槽，其中，所述凹槽包括：
具有第一宽度和第一深度的第一凹槽；和
具有第二宽度和第二深度的第二凹槽，其中，所述第二深度大于所述第一深度，且所述第二深度小于第一厚度；
介电层，位于所述衬底上方；
接触焊盘，位于所述介电层上方；
钝化层，位于所述接触焊盘上方；以及
凸块，位于所述钝化层上方；以及
模塑料层，位于所述钝化层上方并覆盖所述凸块的下部；
其中，所述模塑料层覆盖所述钝化层和所述介电层的侧壁，所述第二凹槽填充有模塑料层，并且所述第一凹槽填充有模塑料层。
14.根据权利要求13所述的半导体封装件，其中，所述衬底包括紧邻所述介电层的所述侧壁的上侧壁、紧邻所述半导体衬底的背面的下侧壁以及从所述上侧壁延伸至所述下侧壁的表面区域，并且所述模塑料层覆盖所述上侧壁和所述表面区域。
15.根据权利要求14所述的半导体封装件，其中，所述上侧壁和所述表面区域在所述半导体衬底中形成凹陷区域，并且所述模塑料层填充所述凹陷区域。
16.根据权利要求14所述的半导体封装件，其中，所述半导体衬底的所述上侧壁与所述介电层的所述侧壁对齐。
17.根据权利要求14所述的半导体封装件，其中，所述模塑料层覆盖所述半导体衬底的所述下侧壁。
18.根据权利要求13所述的半导体封装件，其中，所述半导体衬底的侧壁与所述模塑料层的侧壁对齐。
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