US20150340338A1 - Conductor design for integrated magnetic devices - Google Patents

Conductor design for integrated magnetic devices Download PDF

Info

Publication number
US20150340338A1
US20150340338A1 US14/286,600 US201414286600A US2015340338A1 US 20150340338 A1 US20150340338 A1 US 20150340338A1 US 201414286600 A US201414286600 A US 201414286600A US 2015340338 A1 US2015340338 A1 US 2015340338A1
Authority
US
United States
Prior art keywords
layer
polymer
openings
magnetic
vias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/286,600
Inventor
Dok Won Lee
William D. French
Ann Gabrys
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US14/286,600 priority Critical patent/US20150340338A1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FRENCH, WILLIAM D., GABRYS, ANN, LEE, DOK WON
Publication of US20150340338A1 publication Critical patent/US20150340338A1/en
Priority to US16/264,733 priority patent/US11393787B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0013Printed inductances with stacked layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0033Printed inductances with the coil helically wound around a magnetic core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/2804Printed windings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227Inductive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F2017/0066Printed inductances with a magnetic layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F2017/0086Printed inductances on semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/2804Printed windings
    • H01F2027/2809Printed windings on stacked layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622Manufacturing methods by patterning a pre-deposited material using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/0519Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/296Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32235Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335Material
    • H01L2224/33505Layer connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/46Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Definitions

  • This invention relates to the field of integrated Inductors. More particularly, this invention relates to inductors and their quality factor at high frequencies.
  • Inductors and transformers may be used in many different types of circuits. For example, they may be used for radio frequency (RF) circuits and high-frequency power distribution or conversion systems, such as a DC-DC voltage (or power) converter. Inductors experience resistance increases in magnetic devices due to effects in both the magnetic core and the conductor. The resistance increase due to the core is assumed to be caused by the magnetic losses in the magnetic core and many try to solve the problem by reducing the magnetic losses. This can mitigate the overall resistance increase by suppressing the magnetic losses, but the resistance increase due to the conductor still exists, limiting the full optimization of device performance. For example, a desired operating frequency may require an inductance quality factor that is unobtainable based on the constrained physical size of the inductor. Further, in particular cases, based due to the skin effect, an on-chip inductor may not have a sufficiently high operating frequency for specific RF or high-frequency voltage conversion applications.
  • Resistance of integrated magnetic devices can increase at frequency of operation, which in turn causes the decrease in quality factor.
  • an integrated magnetic device comprising: a conventionally formed silicon wafer, having a substrate, an active region comprising transistors, diodes, capacitors and resistors coupled by a conductive interconnect layer, to form an active circuit, wherein the active region touches the top surface of the silicon wafer substrate and includes a first plurality of bond contacts; wherein the conductive interconnect layer is comprised of multiple layers of conductive material with insulating layers therebetween, the multiple layers of conductive material are coupled together by a first plurality of vias piercing their associated insulating layer, wherein the top of the conductive interconnect layer is an insulating layer, having openings to expose a first plurality of bond contacts; also wherein the insulating layer on top of the conductive interconnect layer is covered by a Silicon Nitride layer, having openings to expose the first plurality of bond contacts; a first layer of polymer, having a first plurality of openings extending from the top surface of the first polymer layer
  • a method of forming an integrated magnetic device comprises: providing a conventionally formed integrated circuit wafer, wherein bond contacts of each of the integrated circuits are exposed through openings in an insulating layer at the top of a conductive interconnect layer; depositing a layer of silicon nitride over the integrated circuit wafer, the layer of silicon nitride touching the insulating layer at the top of the conductive interconnect layer, exposing the bond contacts exposed through the openings in the insulating layer at the top of the conductive interconnect layer by using a pattern and etch process to expose the bond contacts through openings in the silicon nitride layer; depositing a first layer of polymer, having a first plurality of openings extending from the top surface of the first polymer layer down to the plurality of bond contacts, wherein the first plurality of openings are filled with a high conductance material forming a second plurality of vias coupled to the first plurality of bond contacts
  • FIG. 1 is an illustration of an inductor including a coil without slots formed according to embodiments of this invention.
  • FIG. 2 is an illustration of an inductor including a coil with slots formed according to embodiments of this invention.
  • FIG. 3 illustrates inductance vs frequency for inductors with and without slots in their coils according to embodiments of this invention.
  • FIG. 4 illustrates series resistance vs frequency for inductors with and without slots in their coils according to embodiments of this invention.
  • FIG. 5 illustrates inductance quality factor vs frequency for inductors with and without slots in their coils according to embodiments of this invention.
  • FIGS. 6-8 illustrate the mask process sequence of an inductor without slots in the coils according to embodiments of this invention.
  • FIGS. 9-11 illustrate the mask process sequence of an inductor with slots in the coils according to embodiments of this invention.
  • FIG. 12 is an illustration of section AA FIG. 8 . according to embodiments of this invention.
  • FIG. 13 is an illustration of section BB FIG. 8 . according to embodiments of this invention.
  • FIG. 14 is an illustration of section CC FIG. 11 . according to embodiments of this invention.
  • an embodiment is an inductor that may include a laminated material magnetic core structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency.
  • the inductor of an embodiment may include a plurality of metal lines substantially or completely surrounding a magnetic material.
  • the inductor of an embodiment may also include a laminated magnetic layer or layers that may further include higher resistance or insulator layers.
  • the increased resistance of the laminated magnetic layers may reduce eddy currents within the inductor and subsequently improve the performance of the inductor at higher frequencies.
  • the plurality of metal lines substantially or completely surrounding a magnetic material may experience resistance increases at higher frequencies.
  • Resistance increases caused by skin effect at high frequencies can be reduced by introducing the slotting in the conductor winding.
  • the skin effect acts to force the current in the wire to flow close to its surface and away from the center.
  • the slots create more surface area within the metal where the skin effect occurs, and less internal metal areas with lower current, which will therefore result in a higher current density through the wire as a whole, thus a lower effective resistance.
  • a higher quality factor can be achieved at frequencies of interest.
  • slotting can be applied to a part of the conductor selectively for example at the two ends of the inductor only. Slotting can be considered as one of design variables in the inductor design.
  • slotting can be done in the mask design, so there is no impact on the process flow or cost. Slotting can be applied to the entire conductor or to portions of the conductor.
  • FIGS. 12 and 13 are cross sectional views of sections A-A and B-B of FIG. 3 , respectively and 14 is a cross sectional view of C-C of FIG. 11 .
  • FIG. 12 has a silicon wafer substrate 101 .
  • An active region 102 comprising transistors, diodes, capacitors and resistors coupled by a conductive interconnect layer 103 to form an active circuit, wherein the active region 102 touches the top surface of the silicon wafer substrate and includes a first plurality of bond contacts 104 .
  • the conductive interconnect layer 103 can be comprised of multiple layers of conductive material with insulating layer therebetween. The multiple layers of conductive material can be coupled together by a first plurality of vias piercing their associated insulating layer, wherein the top of the conductive interconnect layer 103 is an insulating layer, having openings to expose a first plurality of bond contacts 104 . Additionally the insulating layer on top of the conductive interconnect layer can be covered by a Silicon Nitride layer 106 , having openings to expose the first plurality of bond contacts 104 .
  • a first layer of polymer 105 can be deposited on top of the Silicon Nitride layer and also include a first plurality of openings extending from the top of the first layer of polymer down to the first plurality of bond contacts 104 .
  • the first layer of polymer 105 can act as a stress relief layer between the inductor and the silicon wafer. It can be between 5 ⁇ m-15 ⁇ m in thickness. This can also act to reduce coupling between the copper windings and the silicon wafer substrate 101 .
  • the first layer of polymer can be chosen from the group of polymers SU8 or PI-2622.
  • a first layer high conductance material 107 FIGS. 6 and 9 can be deposited on the top surface of the first layer of polymer 105 , filling the openings in the first polymer layer forming a second plurality of vias, thereby coupling the first layer of high conductance material 107 to the first plurality of bond contacts 104 .
  • the first layer of high conductance material 107 can be configured to form bottom coil members and a coupling means, wherein the bottom coil members can include either slots or no slots and also include a second plurality of bond contacts 108 at the ends of the bottom coil members 107 , also wherein the coupling means connects to the first plurality of vias, coupling to the first plurality of bond contacts 104 .
  • the first layer of high conductance material 107 can be comprised of copper with a thickness of 20 ⁇ m.
  • a second layer of polymer 109 touching the first layer of polymer 105 and the first layer high conductance material 107 wherein the top surface of the second layer of polymer is planar.
  • the second layer of polymer 109 can include openings extending from the top surface of the second layer of polymer 109 down to the second plurality of contacts 108 .
  • the openings in the second layer of polymer can be filled with a third plurality of vias 110 .
  • the third plurality of vias 110 can be copper.
  • the second layer of polymer 109 can be chosen from the group of polymers SU8 3000 or PI-2622
  • FIGS. 7 and 14 can be deposited and defined on the top surface of second layer of polymer 109 , wherein the single layer of magnetic core material or the multiple layers of alternating magnetic material and insulating material 111 , as defined, do not touch the third plurality of vias 110 exposed on the top surface of the second layer of polymer 109 .
  • the single layer magnetic core is sputtered in the presence of a magnetic field, which defines the easy axis and can have total thickness of between 3-15 ⁇ m.
  • the magnetic layer can be selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN and then magnetic layers can be subjected to an anneal (300-500° C.) in the presence of a magnetic field (0.1-1 T) after sputtering.
  • each magnetic film layer can have thickness ranges from 0.1 ⁇ m to 3 ⁇ m with a 10 nm AlN dielectric in between.
  • the magnetic film layers can be selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN.
  • the laminated magnetic core total thickness can be between 5-15 ⁇ m
  • a third layer of polymer 112 can be deposited next, touching the second layer of polymer 109 and the top of the magnetic core 111 .
  • the third layer of polymer can include openings extending from the top surface of the third lay of polymer 112 down to the top surfaces of the third plurality of vias 110 .
  • a second layer high conductance material 114 FIGS. 8 and 11 can be deposited on the top surface of the third layer of polymer 112 , wherein the second layer of high conductance material 114 fills the openings in the third polymer layer 112 forming a fourth plurality of vias, thereby coupling the second layer of high conductance material 114 to the first plurality of bond contacts 104 .
  • the second layer of high conductance material 114 can also be configured with either slots or no slots and include a third plurality of bond contacts 115 .
  • the second layer of high conductance material 114 can be comprised of copper with a thickness of 20 ⁇ m.
  • a fourth layer of polymer 116 can be deposited next, touching the third layer of polymer 112 and the top of the second layer high conductance material 114 .
  • the fourth layer of polymer can include openings extending from the top surface of the fourth lay of polymer 112 down to the top surfaces second layer high conductance material 114 .
  • the openings in the fourth layer of polymer can be filled with solder balls 116 , wherein the solder balls provide connection to outside circuitry.
  • the wafer level integrated inductor is fabricated by providing a conventionally formed integrated circuit wafer 101 , 102 and 103 wherein the bond contacts 104 of each of the integrated circuits are exposed through openings in the insulating layer at the top of the conductive interconnect layer 103 .
  • a layer of silicon nitride is deposited over the wafer, touching the insulating layer at the top of the conductive interconnect layer 103 and the bond pads 104 exposed through the openings in the insulating layer at the top of the conductive interconnect layer 103 .
  • the bond contacts 104 are exposed through openings in the silicon nitride layer.
  • a first layer of polymer 105 is spun onto the wafer and baked to cure the polymer layer.
  • a patterned hard mask is deposited on the wafer touching the top surface of the first polymer 105 . Openings are etched into the first polymer layer 105 extending from the top surface of the first polymer layer 105 down to the plurality of bond contacts 104 . The hard mask is then removed.
  • a mold mask is deposited and patterned onto the surface and the first layer of high conductance material 107 is then electroplated on the surface of the first polymer layer 105 , filling the openings in the first polymer layer forming a second plurality of vias, thereby coupling the first layer of high conductance material to the first plurality of bond contacts 104 .
  • the first layer of high conductance material then forms the bottom coil members and a coupling means, wherein the bottom coil members can include either slots or no slots and also include a second plurality of bond contacts 108 at the ends of the bottom coil members 107 , also wherein the coupling means connects to the first plurality of vias, coupling to the first plurality of bond contacts 104 .
  • the mold mask is stripped off the surface after the electroplating step.
  • the first layer of high conductance material can be composed of 20 ⁇ m of copper and can be configured with or without slots.
  • a second layer of polymer 109 can be deposited next, touching the first layer of polymer 105 and the first layer high conductance material 107 wherein the top surface of the second layer of polymer 109 is planar.
  • the second layer of polymer 109 can include openings extending from the top surface of the second layer of polymer down through 109 to the second plurality of contacts 108 .
  • the openings in the second layer of polymer can include a third plurality of vias 110 , thereby coupling the third plurality of vias 110 to the first plurality of bond contacts 104 .
  • the third plurality of vias 110 can be copper electroplated on the surface of the second polymer layer 109 through a mold mask, filling the openings in the second polymer layer.
  • the second layer of polymer 109 can be chosen from the group of polymers SU8 3000 or PI-2622. If PI-2622 is used, a CMP process can be used to planarize the surface. If SU8 3000 is used instead of PI-2622 for the second Polymer layer 109 , CMP is not required because SU8 3000 is largely self-planarizing to the required tolerance.
  • a layer of titanium can be sputtered on the top surface of the second layer of polymer 109 touching the second layer of polymer 109 and the tops of the third plurality of vias 110 .
  • a single layer of magnetic core material or a laminated magnetic core 111 comprised of multiple layers of alternating magnetic material and insulating material FIGS. 7 and 10 can be deposited using a Veeco Nexus PVDi Tool in a magnetic field on the top surface of second layer of polymer 109 , wherein the single layer of magnetic core material or multiple layers of alternating magnetic material and insulating material 111 are defined to not touch the third plurality of vias 110 exposed on the top surface of the second layer of polymer 109 .
  • each magnetic film layer can be sputtered, with thickness ranges from 0.1 ⁇ m to 3 ⁇ m with a 10 nm AlN dielectric therebetween.
  • Sputtering can be in the presence of a magnetic field to determine the easy axis of the magnetic material.
  • the orientation in the multiple layers of alternating magnetic material and insulating material 111 due to the imposed B-field during the sputtering process is in the direction of the easy axis.
  • the easy axis is perpendicular to the hard axis.
  • the hard axis is the axis along which the magnetic field, generated by the final inductor in normal operation, will flow through the core.
  • the magnetic layers can be selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN.
  • the magnetic layers can be subjected to an anneal (300-500 C) in the presence of a magnetic field (0.1-1 T) after sputtering. This acts to further define the easy/hard axes.
  • the laminated magnetic core 111 total thickness can be between 3-15 ⁇ m
  • Standard photo resist process can be used to define the etch pattern for the magnetic core 111 .
  • the single layer of magnetic material or the multiple layers of alternating magnetic material and insulating material and the Ti adhesion layer can then be etched.
  • the photoresist is then stripped using standard techniques.
  • a mold mask is then deposited and patterned on to the polymer layer 112 , and a second layer of high conductance material 114 is then electroplated on the surface of the third polymer layer 112 , filling the openings in the third polymer layer 112 , forming a fourth plurality of vias, thereby coupling the third layer of high conductance material 114 to the first plurality of bond contacts 104 .
  • the second layer of high conductance material can be composed of 20 ⁇ m of copper and can be configured with or without slots.
  • a fourth layer of polymer 116 can be deposited next, touching the third layer of polymer 112 and the second layer of high conductance material 114 .
  • the fourth layer of polymer 116 can include openings extending from the top surface of the fourth layer of polymer 116 down through the fourth layer of polymer 116 to the second layer of high conductance material 114 .
  • the magnetic layers can be subjected to a second anneal (300-500 C) in the presence of a magnetic field (0.1-1 T). This acts to further define the easy/hard axes.
  • solder bumps are formed in the openings formed in the fourth layer of polymer 116 touching the second layer of high conductance material 114 .

Abstract

An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.

Description

    FIELD OF THE INVENTION
  • This invention relates to the field of integrated Inductors. More particularly, this invention relates to inductors and their quality factor at high frequencies.
  • BACKGROUND OF THE INVENTION
  • Inductors and transformers may be used in many different types of circuits. For example, they may be used for radio frequency (RF) circuits and high-frequency power distribution or conversion systems, such as a DC-DC voltage (or power) converter. Inductors experience resistance increases in magnetic devices due to effects in both the magnetic core and the conductor. The resistance increase due to the core is assumed to be caused by the magnetic losses in the magnetic core and many try to solve the problem by reducing the magnetic losses. This can mitigate the overall resistance increase by suppressing the magnetic losses, but the resistance increase due to the conductor still exists, limiting the full optimization of device performance. For example, a desired operating frequency may require an inductance quality factor that is unobtainable based on the constrained physical size of the inductor. Further, in particular cases, based due to the skin effect, an on-chip inductor may not have a sufficiently high operating frequency for specific RF or high-frequency voltage conversion applications.
  • Resistance of integrated magnetic devices (e.g. inductors, transformers) can increase at frequency of operation, which in turn causes the decrease in quality factor.
  • What is needed is a technique wherein an on chip inductor can be manufactured using a conductor design that minimizes skin effect of the conductor, thereby minimizing the increase in resistance at required switching frequencies.
  • SUMMARY OF THE INVENTION
  • The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
  • In accordance with an embodiment of the present application an integrated magnetic device, wherein the integrated magnetic device comprises: a conventionally formed silicon wafer, having a substrate, an active region comprising transistors, diodes, capacitors and resistors coupled by a conductive interconnect layer, to form an active circuit, wherein the active region touches the top surface of the silicon wafer substrate and includes a first plurality of bond contacts; wherein the conductive interconnect layer is comprised of multiple layers of conductive material with insulating layers therebetween, the multiple layers of conductive material are coupled together by a first plurality of vias piercing their associated insulating layer, wherein the top of the conductive interconnect layer is an insulating layer, having openings to expose a first plurality of bond contacts; also wherein the insulating layer on top of the conductive interconnect layer is covered by a Silicon Nitride layer, having openings to expose the first plurality of bond contacts; a first layer of polymer, having a first plurality of openings extending from the top surface of the first polymer layer down to the plurality of bond contacts, wherein the first plurality of openings are filled with a high conductance material forming a second plurality of vias coupled to the first plurality of bond contacts; a first layer of high conductance material filling the first plurality of openings and overlaying and touching the surface of the first polymer layer, wherein the first layer of high conductance material is defined and configured to include a plurality of rectangular bottom coil members and a coupling means to connect to the second plurality of vias and coupling to the first plurality of bond contacts; the plurality of rectangular bottom coil members, each composed of the first layer of high conductance material, overlaying and touching the first layer of polymer, where each bottom coil member includes, a second plurality of bond contacts at the ends of each of the bottom coil members, one of each of a plurality of bottom slots therein, wherein each of the bottom slots pierces its respective bottom coil member; a second layer of polymer, touching the first layer of polymer and the first layer high conductance material wherein the top surface of the second layer of polymer is planar, the second layer of polymer includes a second plurality of openings extending from the top surface of the second layer of polymer down to the second plurality of contacts, wherein the openings in the second layer of polymer are filled with a third plurality of vias; a layer of titanium touching the second layer of polymer and the tops of the third plurality of vias; a magnetic core selected from a single layer of magnetic core material or a laminated magnetic core material deposited and defined on the top surface of second layer of polymer, wherein the magnetic core, as defined, does not touch the third plurality of vias exposed on the top surface of the second layer of polymer; a third layer of polymer touching the second layer of polymer and the top of the magnetic core material, wherein the third layer of polymer includes a third plurality of openings extending from the top surface of the third layer of polymer down to the top surfaces of the third plurality of vias, wherein the openings in the third layer of polymer are filled with a fourth plurality of vias; a second layer of high conductance material filling the third plurality of openings and overlaying and touching the surface of the third polymer layer, wherein the second layer of high conductance material is defined and configured to include a plurality of rectangular top coil members and coupling to the third plurality of vias; the plurality of rectangular top coil members, composed of the second layer of high conductance material, overlaying and touching the third layer of polymer, where each top coil member includes, a third plurality of bond contacts at the ends of each of the top coil members, wherein each one of the third plurality of bond contacts touching and coupling to one each of the fourth plurality of vias, and of a plurality of top slots therein, wherein each of the top slots pierces its respective top coil member; and a fourth layer of polymer touching the third layer of polymer and the top of the second layer of high conductance material, wherein the fourth layer of polymer includes a fourth plurality of openings extending from the top surface of the fourth lay of polymer down to the top surface of the second layer high conductance material, the openings in the fourth layer of polymer are filled with solder balls, wherein the solder balls provide connection to outside circuitry.
  • In accordance with another embodiment of the present application a method of forming an integrated magnetic device, wherein the method of forming an integrated magnetic device, comprises: providing a conventionally formed integrated circuit wafer, wherein bond contacts of each of the integrated circuits are exposed through openings in an insulating layer at the top of a conductive interconnect layer; depositing a layer of silicon nitride over the integrated circuit wafer, the layer of silicon nitride touching the insulating layer at the top of the conductive interconnect layer, exposing the bond contacts exposed through the openings in the insulating layer at the top of the conductive interconnect layer by using a pattern and etch process to expose the bond contacts through openings in the silicon nitride layer; depositing a first layer of polymer, having a first plurality of openings extending from the top surface of the first polymer layer down to the plurality of bond contacts, wherein the first plurality of openings are filled with a high conductance material forming a second plurality of vias coupled to the first plurality of bond contacts; depositing and patterning a mold mask through which is electroplated a first layer of high conductance material on the surface of the first polymer layer, which also fills the openings in the first polymer layer, after which the mold mask is removed, thereby coupling the first layer of high conductance material to the first plurality of bond contacts, to form a coupling means to the first plurality of bond contacts and a plurality of bottom coil members which are configured to include either slots or no slots and also include a second plurality of bond contacts at the ends of the bottom coil members; depositing a second layer of polymer, touching the first layer of polymer and the first layer high conductance material wherein the top surface of the second layer of polymer is planar, the second layer of polymer including a second plurality of openings extending from the top surface of the second layer of polymer down through the second layer of polymer to the second plurality of bond contacts; filling the second plurality of openings in the second layer of polymer with a third plurality of vias, thereby coupling the second plurality of vias to the first plurality of bond contacts, wherein a mold mask is deposited and patterned and the third plurality of vias are copper electroplated on the surface of the second polymer layer, also filling the openings in the second polymer layer, after which the mold mask is removed; sputtering a layer of titanium on the top surface of the second layer of polymer touching the second layer of polymer and the tops of the second plurality of vias; depositing a magnetic core selected from a single layer of magnetic core material or a laminated magnetic core material on the top surface of second layer of polymer; patterning and etching using a standard photo resist process the laminated magnetic core, wherein the multiple layers of alternating magnetic material and insulating material and the titanium layer are then etched; stripping the photoresist using standard techniques; subjecting the magnetic layers to a first anneal step to reinforce the magnetic alignment imposed during deposition; depositing a third layer of polymer, touching the second layer of polymer, the third plurality of vias and the top of the magnetic core, the third layer of polymer including a third plurality of openings extending from the top surface of the third layer of polymer down through the third layer of polymer to the third plurality of vias, wherein the third plurality of openings in the third layer of polymer constitute a fourth plurality of vias; depositing and patterning a mold mask, electroplating a second layer of high conductance material on the surface of the third polymer layer, filling the third plurality of openings in the third polymer layer thereby coupling the second layer of high conductance material to the first plurality of bond contacts, wherein the second layer of high conductance material is defined and configured to include a plurality of rectangular top coil members thereby coupling to the third plurality of vias and the second layer of high conductance material is selectively configured to include slots or the absence of slots, after which the mold mask is removed; depositing a fourth layer of polymer, touching the third layer of polymer and the second layer of high conductance material, the fourth layer of polymer including openings extending from the top surface of the fourth layer of polymer down through the fourth layer of polymer to the second layer of high conductance material; subjecting the magnetic layers to a second anneal (300-500° C.) in the presence of a magnetic field (0.1-1 T), wherein the second anneal further defines the easy/hard axes; and forming solder bumps in the openings formed in the fourth layer of polymer touching the third layer of high conductance material.
  • DESCRIPTION OF THE VIEWS OF THE DRAWING
  • FIG. 1 is an illustration of an inductor including a coil without slots formed according to embodiments of this invention.
  • FIG. 2 is an illustration of an inductor including a coil with slots formed according to embodiments of this invention.
  • FIG. 3 illustrates inductance vs frequency for inductors with and without slots in their coils according to embodiments of this invention.
  • FIG. 4 illustrates series resistance vs frequency for inductors with and without slots in their coils according to embodiments of this invention.
  • FIG. 5 illustrates inductance quality factor vs frequency for inductors with and without slots in their coils according to embodiments of this invention.
  • FIGS. 6-8 illustrate the mask process sequence of an inductor without slots in the coils according to embodiments of this invention.
  • FIGS. 9-11 illustrate the mask process sequence of an inductor with slots in the coils according to embodiments of this invention.
  • FIG. 12 is an illustration of section AA FIG. 8. according to embodiments of this invention.
  • FIG. 13 is an illustration of section BB FIG. 8. according to embodiments of this invention.
  • FIG. 14 is an illustration of section CC FIG. 11. according to embodiments of this invention.
  • In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.
  • DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
  • Embodiments of a conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof will be described. Reference will now be made in detail to a description of these embodiments as illustrated in the drawings. While the embodiments will be described in connection with these drawings, there is no intent to limit them to drawings disclosed herein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents within the spirit and scope of the described embodiments as defined by the accompanying claims. Simply stated, an embodiment is an inductor that may include a laminated material magnetic core structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. The inductor of an embodiment may include a plurality of metal lines substantially or completely surrounding a magnetic material. The inductor of an embodiment may also include a laminated magnetic layer or layers that may further include higher resistance or insulator layers. The increased resistance of the laminated magnetic layers may reduce eddy currents within the inductor and subsequently improve the performance of the inductor at higher frequencies.
  • In operation, the plurality of metal lines substantially or completely surrounding a magnetic material may experience resistance increases at higher frequencies. Resistance increases caused by skin effect at high frequencies can be reduced by introducing the slotting in the conductor winding. The skin effect acts to force the current in the wire to flow close to its surface and away from the center. The slots create more surface area within the metal where the skin effect occurs, and less internal metal areas with lower current, which will therefore result in a higher current density through the wire as a whole, thus a lower effective resistance. As a result, a higher quality factor can be achieved at frequencies of interest.
  • This was verified with simulations where devices PWP2 FIG. 1 and PWP2 with slotting FIG. 2 are compared. Plots of inductance vs frequency show higher inductance with slotting FIG. 3, resistance vs frequency show lower resistance with slotting FIG. 4 and quality factor vs frequency show higher quality factor with slotting FIG. 5.
  • Introduction of conductor slotting can increase the DC resistance, which is not desirable. Hence to minimize the impact on DC resistance, slotting can be applied to a part of the conductor selectively for example at the two ends of the inductor only. Slotting can be considered as one of design variables in the inductor design.
  • Introduction of slotting can be done in the mask design, so there is no impact on the process flow or cost. Slotting can be applied to the entire conductor or to portions of the conductor.
  • FIGS. 12 and 13 are cross sectional views of sections A-A and B-B of FIG. 3, respectively and 14 is a cross sectional view of C-C of FIG. 11.
  • In an embodiment of the present invention 100, FIG. 12 has a silicon wafer substrate 101. An active region 102 comprising transistors, diodes, capacitors and resistors coupled by a conductive interconnect layer 103 to form an active circuit, wherein the active region 102 touches the top surface of the silicon wafer substrate and includes a first plurality of bond contacts 104. The conductive interconnect layer 103 can be comprised of multiple layers of conductive material with insulating layer therebetween. The multiple layers of conductive material can be coupled together by a first plurality of vias piercing their associated insulating layer, wherein the top of the conductive interconnect layer 103 is an insulating layer, having openings to expose a first plurality of bond contacts 104. Additionally the insulating layer on top of the conductive interconnect layer can be covered by a Silicon Nitride layer 106, having openings to expose the first plurality of bond contacts 104.
  • A first layer of polymer 105 can be deposited on top of the Silicon Nitride layer and also include a first plurality of openings extending from the top of the first layer of polymer down to the first plurality of bond contacts 104. The first layer of polymer 105 can act as a stress relief layer between the inductor and the silicon wafer. It can be between 5 μm-15 μm in thickness. This can also act to reduce coupling between the copper windings and the silicon wafer substrate 101. The first layer of polymer can be chosen from the group of polymers SU8 or PI-2622.
  • A first layer high conductance material 107 FIGS. 6 and 9 can be deposited on the top surface of the first layer of polymer 105, filling the openings in the first polymer layer forming a second plurality of vias, thereby coupling the first layer of high conductance material 107 to the first plurality of bond contacts 104. The first layer of high conductance material 107 can be configured to form bottom coil members and a coupling means, wherein the bottom coil members can include either slots or no slots and also include a second plurality of bond contacts 108 at the ends of the bottom coil members 107, also wherein the coupling means connects to the first plurality of vias, coupling to the first plurality of bond contacts 104. The first layer of high conductance material 107 can be comprised of copper with a thickness of 20 μm.
  • A second layer of polymer 109, touching the first layer of polymer 105 and the first layer high conductance material 107 wherein the top surface of the second layer of polymer is planar. The second layer of polymer 109 can include openings extending from the top surface of the second layer of polymer 109 down to the second plurality of contacts 108. The openings in the second layer of polymer can be filled with a third plurality of vias 110. The third plurality of vias 110 can be copper. The second layer of polymer 109 can be chosen from the group of polymers SU8 3000 or PI-2622
  • A single layer of magnetic material or multiple layers of alternating magnetic material and insulating material 111 FIGS. 7 and 14 can be deposited and defined on the top surface of second layer of polymer 109, wherein the single layer of magnetic core material or the multiple layers of alternating magnetic material and insulating material 111, as defined, do not touch the third plurality of vias 110 exposed on the top surface of the second layer of polymer 109.
  • The single layer magnetic core is sputtered in the presence of a magnetic field, which defines the easy axis and can have total thickness of between 3-15 μm. The magnetic layer can be selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN and then magnetic layers can be subjected to an anneal (300-500° C.) in the presence of a magnetic field (0.1-1 T) after sputtering.
  • In the case of the case of alternating magnetic material and insulating material, each magnetic film layer can have thickness ranges from 0.1 μm to 3 μm with a 10 nm AlN dielectric in between. The magnetic film layers can be selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN. The laminated magnetic core total thickness can be between 5-15 μm
  • A third layer of polymer 112 can be deposited next, touching the second layer of polymer 109 and the top of the magnetic core 111. The third layer of polymer can include openings extending from the top surface of the third lay of polymer 112 down to the top surfaces of the third plurality of vias 110.
  • A second layer high conductance material 114 FIGS. 8 and 11 can be deposited on the top surface of the third layer of polymer 112, wherein the second layer of high conductance material 114 fills the openings in the third polymer layer 112 forming a fourth plurality of vias, thereby coupling the second layer of high conductance material 114 to the first plurality of bond contacts 104. The second layer of high conductance material 114 can also be configured with either slots or no slots and include a third plurality of bond contacts 115. The second layer of high conductance material 114 can be comprised of copper with a thickness of 20 μm.
  • A fourth layer of polymer 116 can be deposited next, touching the third layer of polymer 112 and the top of the second layer high conductance material 114. The fourth layer of polymer can include openings extending from the top surface of the fourth lay of polymer 112 down to the top surfaces second layer high conductance material 114. The openings in the fourth layer of polymer can be filled with solder balls 116, wherein the solder balls provide connection to outside circuitry.
  • In accordance with another embodiment of this invention, the wafer level integrated inductor is fabricated by providing a conventionally formed integrated circuit wafer 101, 102 and 103 wherein the bond contacts 104 of each of the integrated circuits are exposed through openings in the insulating layer at the top of the conductive interconnect layer 103.
  • A layer of silicon nitride is deposited over the wafer, touching the insulating layer at the top of the conductive interconnect layer 103 and the bond pads 104 exposed through the openings in the insulating layer at the top of the conductive interconnect layer 103. Using a pattern and etch process, the bond contacts 104 are exposed through openings in the silicon nitride layer.
  • A first layer of polymer 105 is spun onto the wafer and baked to cure the polymer layer. A patterned hard mask is deposited on the wafer touching the top surface of the first polymer 105. Openings are etched into the first polymer layer 105 extending from the top surface of the first polymer layer 105 down to the plurality of bond contacts 104. The hard mask is then removed.
  • A mold mask is deposited and patterned onto the surface and the first layer of high conductance material 107 is then electroplated on the surface of the first polymer layer 105, filling the openings in the first polymer layer forming a second plurality of vias, thereby coupling the first layer of high conductance material to the first plurality of bond contacts 104. The first layer of high conductance material then forms the bottom coil members and a coupling means, wherein the bottom coil members can include either slots or no slots and also include a second plurality of bond contacts 108 at the ends of the bottom coil members 107, also wherein the coupling means connects to the first plurality of vias, coupling to the first plurality of bond contacts 104. The mold mask is stripped off the surface after the electroplating step. The first layer of high conductance material can be composed of 20 μm of copper and can be configured with or without slots.
  • A second layer of polymer 109 can be deposited next, touching the first layer of polymer 105 and the first layer high conductance material 107 wherein the top surface of the second layer of polymer 109 is planar. The second layer of polymer 109 can include openings extending from the top surface of the second layer of polymer down through 109 to the second plurality of contacts 108. The openings in the second layer of polymer can include a third plurality of vias 110, thereby coupling the third plurality of vias 110 to the first plurality of bond contacts 104. The third plurality of vias 110 can be copper electroplated on the surface of the second polymer layer 109 through a mold mask, filling the openings in the second polymer layer. The second layer of polymer 109 can be chosen from the group of polymers SU8 3000 or PI-2622. If PI-2622 is used, a CMP process can be used to planarize the surface. If SU8 3000 is used instead of PI-2622 for the second Polymer layer 109, CMP is not required because SU8 3000 is largely self-planarizing to the required tolerance.
  • A layer of titanium can be sputtered on the top surface of the second layer of polymer 109 touching the second layer of polymer 109 and the tops of the third plurality of vias 110.
  • A single layer of magnetic core material or a laminated magnetic core 111 comprised of multiple layers of alternating magnetic material and insulating material FIGS. 7 and 10 can be deposited using a Veeco Nexus PVDi Tool in a magnetic field on the top surface of second layer of polymer 109, wherein the single layer of magnetic core material or multiple layers of alternating magnetic material and insulating material 111 are defined to not touch the third plurality of vias 110 exposed on the top surface of the second layer of polymer 109.
  • The single layer magnetic core is sputtered and can have total thickness of between 3-15 μm. The magnetic layer can be selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN and then magnetic layers can be subjected to an anneal (300-500 C) in the presence of a magnetic field (0.1-1 T) after sputtering.
  • In the case of the laminated core, each magnetic film layer can be sputtered, with thickness ranges from 0.1 μm to 3 μm with a 10 nm AlN dielectric therebetween. Sputtering can be in the presence of a magnetic field to determine the easy axis of the magnetic material. The orientation in the multiple layers of alternating magnetic material and insulating material 111 due to the imposed B-field during the sputtering process is in the direction of the easy axis. The easy axis is perpendicular to the hard axis. The hard axis is the axis along which the magnetic field, generated by the final inductor in normal operation, will flow through the core. The magnetic layers can be selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN. The magnetic layers can be subjected to an anneal (300-500 C) in the presence of a magnetic field (0.1-1 T) after sputtering. This acts to further define the easy/hard axes. The laminated magnetic core 111 total thickness can be between 3-15 μm
  • Standard photo resist process can be used to define the etch pattern for the magnetic core 111. The single layer of magnetic material or the multiple layers of alternating magnetic material and insulating material and the Ti adhesion layer can then be etched. The photoresist is then stripped using standard techniques.
  • A third layer of polymer 112 can be deposited next, touching the second layer of polymer 109 and the first plurality of vias 110 and the top of the magnetic core 111. The third layer of polymer can include openings extending from the top surface of the third layer of polymer 112 down through the third layer of polymer 112 to the third plurality of vias 110.
  • A mold mask is then deposited and patterned on to the polymer layer 112, and a second layer of high conductance material 114 is then electroplated on the surface of the third polymer layer 112, filling the openings in the third polymer layer 112, forming a fourth plurality of vias, thereby coupling the third layer of high conductance material 114 to the first plurality of bond contacts 104. The second layer of high conductance material can be composed of 20 μm of copper and can be configured with or without slots.
  • A fourth layer of polymer 116 can be deposited next, touching the third layer of polymer 112 and the second layer of high conductance material 114. The fourth layer of polymer 116 can include openings extending from the top surface of the fourth layer of polymer 116 down through the fourth layer of polymer 116 to the second layer of high conductance material 114.
  • The magnetic layers can be subjected to a second anneal (300-500 C) in the presence of a magnetic field (0.1-1 T). This acts to further define the easy/hard axes.
  • Finally solder bumps are formed in the openings formed in the fourth layer of polymer 116 touching the second layer of high conductance material 114.
  • While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.

Claims (13)

What is claimed is:
1. An integrated magnetic device, comprising:
a conventionally formed silicon wafer, having a substrate, an active region comprising transistors, diodes, capacitors and resistors coupled by a conductive interconnect layer, to form an active circuit, wherein the active region touches the top surface of the silicon wafer substrate and includes a first plurality of bond contacts;
wherein the conductive interconnect layer is comprised of multiple layers of conductive material with insulating layers therebetween, the multiple layers of conductive material coupled together by a first plurality of vias piercing their associated insulating layer, wherein the top of the conductive interconnect layer is an insulating layer, having openings to expose a first plurality of bond contacts;
also wherein the insulating layer on top of the conductive interconnect layer is covered by a Silicon Nitride layer, having openings to expose the first plurality of bond contacts;
a first layer of polymer, having a first plurality of openings extending from the top surface of the first polymer layer down to the plurality of bond contacts, wherein the first plurality of openings are filled with a high conductance material forming a second plurality of vias coupled to the first plurality of bond contacts;
a first layer of high conductance material filling the first plurality of openings and the overlaying and touching the surface of the first polymer layer, wherein the first layer of high conductance material is defined and configured to include a plurality of rectangular bottom coil members and a coupling means to connect to the second plurality of vias and coupling to the first plurality of bond contacts;
the plurality of rectangular bottom coil members, composed of the first layer of high conductance material, overlaying and touching the first layer of polymer, each bottom coil member including, a second plurality of bond contacts at the ends of each of the bottom coil members, one of each of a plurality of bottom slots therein, wherein each of the bottom slots pierces its respective bottom coil member;
a second layer of polymer, touching the first layer of polymer and the first layer high conductance material wherein the top surface of the second layer of polymer is planar, the second layer of polymer including a second plurality of openings extending from the top surface of the second layer of polymer down to the second plurality of contacts, wherein the openings in the second layer of polymer are filled with a third plurality of vias;
a layer of titanium touching the second layer of polymer and the tops of the third plurality of vias;
a magnetic core selected from a single layer of magnetic core material or a laminated magnetic core material deposited and defined on the top surface of second layer of polymer, wherein the magnetic core, as defined, does not touch the third plurality of vias exposed on the top surface of the second layer of polymer;
a third layer of polymer touching the second layer of polymer and the top of the magnetic core material, wherein the third layer of polymer includes a third plurality of openings extending from the top surface of the third layer of polymer down to the top surfaces of the third plurality of vias, wherein the openings in the third layer of polymer are filled with a fourth plurality of vias;
a second layer of high conductance material filling the third plurality of openings and overlaying and touching the surface of the third polymer layer, wherein the second layer of high conductance material is defined and configured to include a plurality of rectangular top coil members and coupling to the third plurality of vias;
the plurality of rectangular top coil members, composed of the second layer of high conductance material, overlaying and touching the third layer of polymer, each top coil member including, a third plurality of bond contacts at the ends of each of the top coil members, wherein each one of the third plurality of bond contacts touching and coupling to one each of the fourth plurality of vias, and of a plurality of top slots therein, wherein each of the top slots pierces its respective top coil member; and
a fourth layer of polymer touching the third layer of polymer and the top of the second layer high conductance material, wherein the fourth layer of polymer includes a fourth plurality of openings extending from the top surface of the fourth lay of polymer down to the top surfaces second layer high conductance material, the openings in the fourth layer of polymer are filled with solder balls, wherein the solder balls provide connection to outside circuitry.
2. The integrated magnetic device of claim 1, wherein each of the bottom slots is rectangular and longitudinally aligned and spaced apart from the outside edges of its respective bottom coil member.
3. The integrated magnetic device of claim 1, wherein the single layer magnetic core is sputtered and has a total thickness of 3-15 μm.
4. The integrated magnetic device of claim 1, wherein the laminated magnetic core material is comprised of multiple layers of alternating magnetic material and insulating material, wherein each magnetic film layer thickness ranges from 0.1 μm to 3 μm with a 10 nm AlN dielectric in between.
5. The integrated magnetic device of claim 1, wherein each of top slots is rectangular and longitudinally aligned and spaced apart from the outside edges of its respective top coil member.
6. A method of forming an integrated magnetic device, comprising:
providing a conventionally formed integrated circuit wafer, wherein bond contacts of each of the integrated circuits are exposed through openings in an insulating layer at the top of a conductive interconnect layer;
depositing a layer of silicon nitride over the integrated circuit wafer, the layer of silicon nitride touching the insulating layer at the top of the conductive interconnect layer, exposing the bond contacts exposed through the openings in the insulating layer at the top of the conductive interconnect layer by using a pattern and etch process to expose the bond contacts through openings in the silicon nitride layer;
depositing a first layer of polymer, having a first plurality of openings extending from the top surface of the first polymer layer down to the plurality of bond contacts, wherein the first plurality of openings are filled with a high conductance material forming a second plurality of vias coupled to the first plurality of bond contacts;
depositing and patterning a photoresist mold and electroplating a first layer of high conductance material on the surface of the first polymer layer, filling the openings in the first polymer layer, and removing the photoresist mold, thereby coupling the first layer of high conductance material to the first plurality of bond contacts, the first layer of high conductance material is then patterned and etched to form a coupling means to the first plurality of bond contacts and a plurality of bottom coil members which are configured to include either slots or no slots and also include a second plurality of bond contacts at the ends of the bottom coil members;
depositing a second layer of polymer, touching the first layer of polymer and the first layer high conductance material wherein the top surface of the second layer of polymer is planar, the second layer of polymer including a second plurality of openings extending from the top surface of the second layer of polymer down through the second layer of polymer to the second plurality of bond contacts;
filling the second plurality of openings in the second layer of polymer with a third plurality of vias, thereby coupling the second plurality of vias to the first plurality of bond contacts, wherein the third plurality of vias are copper electroplated on the surface of the second polymer layer using a mold mask to define their pattern, filling the openings in the second polymer layer;
sputtering a layer of titanium on the top surface of the second layer of polymer touching the second layer of polymer and the tops of the second plurality of vias;
depositing a magnetic core selected from a single layer of magnetic core material or a laminated magnetic core material on the top surface of second layer of polymer;
patterning and etching using a standard photo resist process the laminated magnetic core, wherein the Multiple layers of alternating magnetic material and insulating material and the Ti adhesion layer are then etched;
stripping the photoresist using standard techniques;
subjecting the magnetic materials to a first anneal to reinforce the magnetic alignment imposed during deposition;
depositing a third layer of polymer, touching the second layer of polymer, the third plurality of vias and the top of the magnetic core, the third layer of polymer including a third plurality of openings extending from the top surface of the third layer of polymer down through the third layer of polymer to the third plurality of vias, wherein the third plurality of openings in the third layer of polymer are filled with a fourth plurality of vias;
electroplating a second layer of high conductance material through a photoresist mold mask, on the surface of the third polymer layer, filling the third plurality of openings in the third polymer layer thereby coupling the second layer of high conductance material to the first plurality of bond contacts, wherein the second layer of high conductance material is defined and configured to include a plurality of rectangular top coil members therein coupling to the third plurality of vias, the second layer of high conductance material is selectively configured to include slots or the absence of slots;
depositing a fourth layer of polymer, touching the third layer of polymer and the second layer of high conductance material, the fourth layer of polymer including openings extending from the top surface of the fourth layer of polymer down through the fourth layer of polymer to the second layer of high conductance material;
subjecting the magnetic layers to a second anneal (300-500° C.) in the presence of a magnetic field (0.1-1 T), wherein the second anneal further defines the easy/hard axes; and
forming solder bumps in the openings formed in the fourth layer of polymer touching the third layer of high conductance material.
7. The method of forming an integrated magnetic device of claim 6, wherein each of the bottom slots is rectangular, longitudinally aligned and spaced apart from the outside edges of its respective bottom coil member.
8. The method of forming an integrated magnetic device of claim 6, wherein the second layer of polymer is chosen from the group of polymers SU8 3000 or PI-2622, wherein if PI-2622 is used, a CMP process must be used to planarize the surface and if SU8 3000 is used instead of PI-2622 for the second Polymer layer, CMP is not required because SU8 3000 is largely self-planarizing to the required tolerance.
9. The method of forming an integrated magnetic device of claim 6, wherein the single layer magnetic core is sputtered and the total thickness is between 3-15 μm, the magnetic layer is selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN and the magnetic layers are subjected to an anneal (300-500 C) in the presence of a magnetic field after sputtering.
10. The method of forming an integrated magnetic device of claim 6, wherein the laminated magnetic core is comprised of multiple layers of alternating magnetic film material and insulating material be deposited using a Veeco Nexus PVDi Tool in a magnetic field on the top surface of second layer of polymer, multiple layers of alternating magnetic material and insulating material are defined to not touch the second plurality of vias exposed on the top surface of the second layer of polymer;
11. The method of forming an integrated magnetic device of claim 10, wherein each magnetic film layer is sputtered, with thickness ranges from 0.1 μm to 3 μm with a 10 nm AlN dielectric therebetween, sputtering is accomplished in the presence of a magnetic field to determine the easy axis of the magnetic material, wherein the orientation in the multiple layers of alternating magnetic material and insulating material 111 due to the imposed B-field during the sputtering process is in the direction of the easy axis and the easy axis is perpendicular to the hard axis, wherein the hard axis is the axis along which the magnetic field, created by the final inductor in normal operation, will flow through the core.
12. The method of forming an integrated magnetic device of claim 6, wherein the laminated magnetic core total thickness is between 5-15 μm and the magnetic layers are selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN and the magnetic layers are subjected to an anneal (300-500 C) in the presence of a magnetic field after sputtering.
13. The method of forming an integrated magnetic device of claim 6, wherein the first and second layers of high conductance material are composed of 20 μm of copper.
US14/286,600 2014-05-23 2014-05-23 Conductor design for integrated magnetic devices Abandoned US20150340338A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/286,600 US20150340338A1 (en) 2014-05-23 2014-05-23 Conductor design for integrated magnetic devices
US16/264,733 US11393787B2 (en) 2014-05-23 2019-02-01 Conductor design for integrated magnetic devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/286,600 US20150340338A1 (en) 2014-05-23 2014-05-23 Conductor design for integrated magnetic devices

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/264,733 Division US11393787B2 (en) 2014-05-23 2019-02-01 Conductor design for integrated magnetic devices

Publications (1)

Publication Number Publication Date
US20150340338A1 true US20150340338A1 (en) 2015-11-26

Family

ID=54556614

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/286,600 Abandoned US20150340338A1 (en) 2014-05-23 2014-05-23 Conductor design for integrated magnetic devices
US16/264,733 Active 2034-07-26 US11393787B2 (en) 2014-05-23 2019-02-01 Conductor design for integrated magnetic devices

Family Applications After (1)

Application Number Title Priority Date Filing Date
US16/264,733 Active 2034-07-26 US11393787B2 (en) 2014-05-23 2019-02-01 Conductor design for integrated magnetic devices

Country Status (1)

Country Link
US (2) US20150340338A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160255714A1 (en) * 2015-02-26 2016-09-01 Denso Corporation Power converter
US20170141021A1 (en) * 2015-11-14 2017-05-18 Intel Corporation Magnetic alignment for flip chip microelectronic devices
US20170346000A1 (en) * 2016-05-26 2017-11-30 Texas Instruments Incorporated Magnetic core
US10164001B1 (en) 2017-09-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having integrated inductor therein
WO2020083027A1 (en) * 2018-10-26 2020-04-30 Huawei Technologies Co., Ltd. Embedded thin-film magnetic inductor design for integrated voltage regulator (ivr) applications
US20220013275A1 (en) * 2018-10-30 2022-01-13 Beihang University Mems solenoid inductor and manufacturing method thereof
US11380472B2 (en) * 2018-09-25 2022-07-05 Intel Corporation High-permeability magnetic-dielectric film-based inductors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140068932A1 (en) * 2012-09-11 2014-03-13 Ferric Semiconductor, Inc. Magnetic Core Inductor Integrated with Multilevel Wiring Network
US20150035718A1 (en) * 2012-08-09 2015-02-05 Murata Manufacturing Co., Ltd. Antenna device and wireless communication apparatus

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6195232B1 (en) * 1995-08-24 2001-02-27 Torohead, Inc. Low-noise toroidal thin film head with solenoidal coil
US7719084B2 (en) 2006-06-30 2010-05-18 Intel Corporation Laminated magnetic material for inductors in integrated circuits
JP2008041115A (en) * 2006-08-01 2008-02-21 Alps Electric Co Ltd Vertical magnetic recording head
US7948346B2 (en) * 2008-06-30 2011-05-24 Alpha & Omega Semiconductor, Ltd Planar grooved power inductor structure and method
US8686722B2 (en) * 2011-08-26 2014-04-01 National Semiconductor Corporation Semiconductor fluxgate magnetometer
US8686522B2 (en) * 2011-10-13 2014-04-01 International Business Machines Corporation Semiconductor trench inductors and transformers
CN103636066B (en) * 2012-05-09 2017-02-08 株式会社村田制作所 Coil antenna element and antenna module
US9275924B2 (en) * 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150035718A1 (en) * 2012-08-09 2015-02-05 Murata Manufacturing Co., Ltd. Antenna device and wireless communication apparatus
US20140068932A1 (en) * 2012-09-11 2014-03-13 Ferric Semiconductor, Inc. Magnetic Core Inductor Integrated with Multilevel Wiring Network

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780684B2 (en) * 2015-02-26 2017-10-03 Denso Corporation Power converter
US20160255714A1 (en) * 2015-02-26 2016-09-01 Denso Corporation Power converter
US20170141021A1 (en) * 2015-11-14 2017-05-18 Intel Corporation Magnetic alignment for flip chip microelectronic devices
US9711443B2 (en) * 2015-11-14 2017-07-18 Intel Corporation Magnetic alignment for flip chip microelectronic devices
US10002824B2 (en) * 2015-11-14 2018-06-19 Intel Corporation Magnetic alignment for flip chip microelectronic devices
US10199573B2 (en) * 2016-05-26 2019-02-05 Texas Instruments Incorporated Magnetic core
US20170346000A1 (en) * 2016-05-26 2017-11-30 Texas Instruments Incorporated Magnetic core
CN109524388A (en) * 2017-09-18 2019-03-26 台湾积体电路制造股份有限公司 Semiconductor structure with integrated inductor
US10164001B1 (en) 2017-09-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having integrated inductor therein
TWI666757B (en) * 2017-09-18 2019-07-21 台灣積體電路製造股份有限公司 Semiconductor structure having integrated inductor therein
US10541297B2 (en) 2017-09-18 2020-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having integrated inductor therein
CN109524388B (en) * 2017-09-18 2020-07-31 台湾积体电路制造股份有限公司 Semiconductor structure with integrated inductor
US11011600B2 (en) 2017-09-18 2021-05-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having integrated inductor therein
US11380472B2 (en) * 2018-09-25 2022-07-05 Intel Corporation High-permeability magnetic-dielectric film-based inductors
WO2020083027A1 (en) * 2018-10-26 2020-04-30 Huawei Technologies Co., Ltd. Embedded thin-film magnetic inductor design for integrated voltage regulator (ivr) applications
US11373966B2 (en) 2018-10-26 2022-06-28 Huawei Technologies Co., Ltd. Embedded thin-film magnetic inductor design for integrated voltage regulator (IVR) applications
US20220013275A1 (en) * 2018-10-30 2022-01-13 Beihang University Mems solenoid inductor and manufacturing method thereof

Also Published As

Publication number Publication date
US20190164934A1 (en) 2019-05-30
US11393787B2 (en) 2022-07-19

Similar Documents

Publication Publication Date Title
US11393787B2 (en) Conductor design for integrated magnetic devices
EP3146538B1 (en) Method of manufacturing a micro-fabricated wafer level integrated inductor for high frequency switch mode power supplies
US10028385B2 (en) Method of manufacturing a processor
US20130106552A1 (en) Inductor with multiple polymeric layers
US7652348B1 (en) Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits
JP4584533B2 (en) Thin film multilayer high Q transformer formed in a semiconductor substrate
WO1997045873A1 (en) Conductors for integrated circuits
US8314676B1 (en) Method of making a controlled seam laminated magnetic core for high frequency on-chip power inductors
US20040070893A1 (en) Microtransformer for system-on-chip power supply
US8754500B2 (en) Plated lamination structures for integrated magnetic devices
TWI489613B (en) Methods of forming magnetic vias to maximize inductance in integrated circuits and structures formed thereby
CN114946023A (en) Integrated inductor with stacked metal lines
US8531002B2 (en) Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits
US20080120828A1 (en) High Density Planarized Inductor And Method Of Making The Same
US10470309B2 (en) Inductor and capacitor integrated on a substrate
JP2006041357A (en) Semiconductor device and its manufacturing method
US20110272780A1 (en) Method and structure for improving the qualilty factor of rf inductors
JP2010080551A (en) Semiconductor device
CN110233147B (en) Stacked inductor and manufacturing method thereof
US20230129684A1 (en) Integrated inductor with inductor wire formed in an integrated circuit layer stack
US20230128990A1 (en) Integrated inductor including multi-component via layer inductor element
KR100709782B1 (en) High frequency semiconductor passive device and manufacturing method thereof
KR102528067B1 (en) Power device and method of manufacturing the same
JP2001352040A (en) Semiconductor integrated circuit device and its manufacturing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, DOK WON;FRENCH, WILLIAM D.;GABRYS, ANN;REEL/FRAME:032959/0202

Effective date: 20140507

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION