CN103531478A - 多栅极fet及其形成方法 - Google Patents

多栅极fet及其形成方法 Download PDF

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CN103531478A
CN103531478A CN201310109488.7A CN201310109488A CN103531478A CN 103531478 A CN103531478 A CN 103531478A CN 201310109488 A CN201310109488 A CN 201310109488A CN 103531478 A CN103531478 A CN 103531478A
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semiconductor fin
semiconductor
sidewall
gate
impurity
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CN103531478B (zh
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卢文泰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了多栅极FET及其形成方法。一种方法包括氧化半导体鳍以在该半导体鳍的相对侧壁上形成氧化物层。该半导体鳍位于隔离区的顶面上方。在氧化之后，实施倾斜注入以将杂质注入半导体鳍。在倾斜注入之后去除氧化物层。

Description

多栅极FET及其形成方法
技术领域
本发明涉及半导体制造，具体而言，涉及多栅极FET及其形成方法。
背景技术
随着集成电路不断按比例缩小以及对集成电路速度的要求不断提高，晶体管需要具有更高的驱动电流和不断减小的尺寸。因此开发了鳍式场效应晶体管(FinFET)，也被称为多栅极FET。典型的FinFET包括位于衬底上方的半导体鳍，该鳍用于形成FinFET的沟道区。沟道区包括半导体鳍的侧壁部分而有时也包括顶面部分。当沟道区包括侧壁部分但不包括顶面部分时，相应的FinFET被称为双栅极FinFET。当沟道区包括侧壁部分和顶面部分时，相应的FinFET被称为三栅极FinFET。
FinFET中的一些从绝缘体上硅衬底开始形成。相应的FinFET具有减少的漏电流。然而，制造成本高。一些其它FinFET从块状硅衬底开始形成。因此，形成的鳍通过在浅沟槽隔离(STI)区中形成的硅带(silicon strip)连接到块状衬底。因此，漏电流可能流经半导体带。
按照惯例，可以通过注入实施重掺杂，从而可以将掺杂物注入位于STI区之间的硅带。在硅带中重掺杂有助于抑制漏电流。然而，这种方法导致相应的掺杂物被引入到位于硅带上方的硅鳍中，这是不利的。因此，降低了相应的FinFET的阈值电压Vth。
发明内容
为了解决上述技术问题，一方面，本发明提供了一种方法，包括：氧化半导体鳍以在所述半导体鳍的相对侧壁上形成氧化物层，其中所述半导体鳍位于隔离区的顶面上方；在所述氧化之后，实施倾斜注入以将杂质注入所述半导体鳍；以及在所述倾斜注入的步骤之后，去除所述氧化物层。
所述的方法还包括：在所述半导体鳍的相对侧壁上形成栅极电介质；在所述栅极电介质上方形成栅电极；以及邻近所述栅极电介质和所述栅电极形成源极/漏极区。
所述的方法还包括：在所述半导体鳍的相对侧壁上形成栅极电介质；在所述栅极电介质上方形成栅电极；以及邻近所述栅极电介质和所述栅电极形成源极/漏极区，其中，所述杂质的导电类型与所述源极/漏极区的导电类型相反。
在所述的方法中，采用介于约20度和约45度之间的倾斜角度实施所述倾斜注入。
在所述的方法中，在所述倾斜注入期间，所述杂质的一部分穿透所述半导体鳍。
在所述的方法中，在所述倾斜注入期间，所述杂质的一部分穿透所述半导体鳍，其中，在所述倾斜注入期间，所述杂质的所述一部分穿透位于所述半导体鳍的相对侧壁上的所述氧化物层的一部分。
在所述的方法中，所述隔离区包括：具有倾斜顶面的第一部分，所述倾斜顶面更靠近所述半导体鳍的部分高于所述倾斜顶面更远离所述半导体鳍的部分，并且与所述第一部分齐平的掺杂半导体区具有所述杂质的第一杂质浓度，所述杂质的第一杂质浓度高于所述杂质在所述半导体鳍的中部中的第二杂质浓度；以及比所述第一部分更远离所述半导体鳍的第二部分，所述第二部分的顶面连接到所述第一部分的倾斜顶面并且低于所述第一部分的倾斜顶面。
另一方面，本发明提供了一种方法，包括：氧化半导体鳍以在所述半导体鳍的相对侧壁上形成氧化物层，其中所述半导体鳍位于浅沟槽隔离(STI)区的顶面上方，半导体带位于所述半导体鳍的下方并连接到所述半导体鳍，并且所述半导体带与所述STI区齐平；在所述氧化之后，实施倾斜注入以将杂质注入所述半导体鳍，所述杂质具有第一导电类型；在所述倾斜注入的步骤之后，去除所述氧化物层；形成包括位于所述半导体鳍的侧壁上的一部分的栅极电介质；在所述栅极电介质上方形成栅电极；以及邻近所述栅极电介质和所述栅电极形成源极/漏极区，其中所述源极/漏极区具有与所述第一导电类型相反的第二导电类型。
在所述的方法中，采用介于约20度和约45度之间的倾斜角度实施所述倾斜注入。
在所述的方法中，在所述倾斜注入期间，所述杂质的一部分穿透所述半导体鳍。
在所述的方法中，使用介于约4keV和约30keV之间的能量实施所述倾斜注入。
在所述的方法中，在所述注入之后，所述半导体带的顶部具有所述杂质的第一浓度，所述半导体鳍的中部具有所述杂质的第二浓度，并且所述第二浓度低于所述第一浓度。
在所述的方法中，在所述倾斜注入期间，所述杂质的一部分穿透所述半导体鳍，并且穿透位于所述半导体鳍的相对侧壁上的所述氧化物层的一部分。
在所述的方法中，在所述氧化之后，所述半导体鳍的剩余厚度介于所述半导体鳍在所述氧化之前的厚度的约55％和约75％之间。
又一方面，本发明提供了一种器件，包括：半导体衬底；半导体带，位于所述半导体衬底上方并且连接到所述半导体衬底，所述半导体带包括：基本上是平的且处在第一平面中的第一侧壁，和与所述第一侧壁相对的第二侧壁，所述第二侧壁基本上是平的并且处在第二平面中；浅沟槽隔离(STI)区，位于所述半导体带的相对侧上；以及半导体鳍，位于所述半导体带上方并且连接到所述半导体带，所述半导体鳍包括：基本上是平的第三侧壁，其中所述第三侧壁处在与所述第一平面基本平行但不重叠的第三平面中；和基本上是平的并且与所述第三侧壁相对的第四侧壁，其中所述第四侧壁处在与所述第二平面基本平行但不重叠的第四平面中，并且所述第三侧壁和所述第四侧壁位于所述第一平面和所述第二平面之间的区域中。
在所述的器件中，所述第一侧壁和所述第三侧壁通过连接部分连接，并且所述连接部分与所述STI区的顶端基本齐平。
所述的器件还包括：栅极电介质，位于所述半导体鳍的第三侧壁和第四侧壁上；栅电极，位于所述栅极电介质的上方；以及源极/漏极区，邻近所述栅极电介质和所述栅电极。
所述的器件还包括：栅极电介质，位于所述半导体鳍的第三侧壁和第四侧壁上；栅电极，位于所述栅极电介质的上方；以及源极/漏极区，邻近所述栅极电介质和所述栅电极，其中，所述半导体带的顶部的杂质的第一杂质浓度高于所述杂质在所述半导体鳍的中部中的第二杂质浓度，并且所述杂质的导电类型与所述源极/漏极区的导电类型相反。
所述的器件还包括：栅极电介质，位于所述半导体鳍的第三侧壁和第四侧壁上；栅电极，位于所述栅极电介质的上方；以及源极/漏极区，邻近所述栅极电介质和所述栅电极，其中，所述STI区包括：具有第一倾斜顶面的第一部分，所述倾斜顶面更靠近所述半导体鳍的部分高于所述倾斜顶面更远离所述半导体鳍的部分，并且与所述第一部分齐平的所述半导体带的顶部具有所述杂质的第一杂质浓度，所述杂质的第一杂质浓度高于所述杂质在所述半导体鳍的中部中的第二杂质浓度；以及比所述第一部分更远离所述半导体鳍的第二部分，所述第二部分的顶面连接到所述第一部分的倾斜顶面并且低于所述第一部分的倾斜顶面。
在所述的器件中，所述半导体鳍具有圆顶角。
附图说明
为了更充分地理解实施例及其优点，现在将参考结合附图所进行的以下描述，其中：
图1至图6B是根据一些示例性实施例制造鳍式场效应晶体管(FinFET)的中间阶段的截面图。
具体实施方式
以下详细论述本发明实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅是示例性的，而不用于限制本发明的范围。
提供了一种形成鳍式场效应晶体管(FinFET)的方法。示出了根据实施例制造FinFET的中间阶段。论述了实施例的变化。在全文的各个视图和示例性实施例中，相同的参考编号用于表示相同的元件。
图1至图6B示出根据一些实施例形成FinFET的截面图。参照图1，形成结构。示出的结构包括晶圆10的一部分，其进一步包括衬底20。衬底20可以是硅衬底、锗衬底或者由III-V族化合物半导体材料形成的衬底。衬底20可以掺杂有p型杂质或n型杂质。可以在衬底20的主体部分上方形成隔离区，诸如浅沟槽隔离(STI)区22。在STI区22中形成半导体带24，并且该半导体带24位于相对的STI区22之间。半导体带24的底部可以是衬底20的一部分，并连接到衬底20的主体部分。图1中结构的形成可以包括在衬底20中形成沟槽(被STI区22占据)，在沟槽中填充介电材料，然后实施化学机械抛光(CMP)以去除多余的介电材料。介电材料的剩余部分是STI区22。STI区22可以包含氧化物，诸如氧化硅。
接下来，参照图2，使STI区22凹陷。在整个说明书中，半导体带24位于STI区22剩余部分的上方的部分被称为半导体鳍124。STI区22的剩余部分具有顶面22A。在一些实施例中，顶面22A包括基本平坦的部分22A1和连接到基本平坦的部分22A1并位于基本平坦的部分22A1上方的倾斜部分22A2。平坦部分22A1可以是靠近相邻的鳍124中部的部分。倾斜部分22A2可以是靠近鳍124的部分。而且，STI区22可以被看作是包括具有基本平坦的顶面22A1的部分22’，以及位于部分22’的上方并具有倾斜顶面22A2的凸出部分22”。凸出部分22”的顶端23可以邻接相应的鳍124。在鳍124的顶面和鳍124的底部(具有尖端23的底部水平面)之间的中间水平面测量鳍124的中间厚度T1。在整个说明书中，中间厚度T1被称为相应鳍124的厚度。
在一些实施例中，半导体带24的侧壁24A基本上是直的，并且可以是基本垂直的或者略微倾斜的。半导体鳍124的侧壁124A基本上也是直的，并且可以是基本上垂直的或者略微倾斜的。而且，侧壁124A及其下方的连接侧壁24A中的每一个均可以在同一平面25中。换句话说，在图2的截面图中，当从一个侧壁24A向上绘制延伸平面(其与平面25重叠)时，延伸平面与位于上方的相应侧壁124A基本重叠。
参照图3，实施氧化以氧化鳍124的表层。因此形成氧化物层26，其可以是氧化硅层，取决于鳍124的材料。氧化物层26包括位于鳍124的相对侧壁上的部分，以及位于鳍124上方的顶部。在一些实施例中，通过原位蒸汽生成(ISSG)步骤实施氧化。在可选的实施例中，通过在含氧环境(诸如烤箱)中对晶圆10进行退火来实施氧化。由于氧化，减小了鳍124的厚度。例如，鳍124的中间厚度T2可能减小到小于鳍124在氧化前测量的中间厚度T1(图2中示出)的约75％，小于厚度T1的约55％，或介于厚度T1的约55％和约75％之间。中间厚度T2还可以介于厚度T1的约25％和约45％之间。在一些实施例中，氧化物层26的厚度T3介于约
Figure BDA00002990285600061
和约
Figure BDA00002990285600062
之间。然而，应该理解，整个说明书中列举的尺寸仅是实例，并且可以更改为不同的值。
由于氧化，鳍124的角部(示出的左上角和右上角)被圆化。这使得改进了所形成的FinFET42(图6A和图6B)的性能，因为尖锐的角部可能导致漏电流增加，并且由于在角部具有高电场密度，尖锐的角部不利于FinFET42的可靠性。此外，通过STI区22保护半导体带24的底部，并且对半导体带24的底部的氧化是最小的(如果有的话)。还可以氧化半导体带24邻近STI部分22”的顶部。然而，氧化物层26的由半导体带24的顶部产生的部分的厚度(例如，T4和T5)小于厚度T3。上部所形成的厚度还与相应的位置有关。例如，氧化物层26的厚度T4小于厚度T5，并且位置越高，由半导体带24产生的氧化物层26就越厚。
由于氧化，鳍124被减薄。由于鳍124的减薄，侧壁124A的平面125与侧壁24A的相应平面25不再相互重叠。而是，在相对的侧壁24A的平面25中限定区域，而鳍124位于该区域内。侧壁124A的一部分(该部分位于平面125中)可以是基本上平的并且平行于侧壁24A的一部分。在侧壁24A和124A都是基本垂直的实施例中，相对的侧壁124A之间的距离小于相对的侧壁24A之间的距离。
图4示出倾斜注入以形成掺杂区28，该掺杂区位于半导体带24的顶部中。如果形成的FinFET42(图6A和图6B)是n型FinFET，这意味着如果FinFET42的源极和漏极区44(图6B)是n型，那么掺杂的杂质是p型，反之亦然。注入的倾斜角度α可以介于约20度和约45度之间。然而，应该理解，整个说明书中列举的倾斜角度仅是实例，并且可以更改为不同的值。倾斜注入可以包括以相对方向倾斜的两种倾斜注入，如箭头30和32所示，或者仅包括一种倾斜注入。当注入的杂质是p型时，可以包括硼、铟或它们的组合。相反，当注入的杂质是n型时，可以包括磷、砷、锑或它们的组合。
对注入的能量进行控制，从而使大量(例如，30％或更多)的注入杂质穿透鳍124，并且到达与杂质注入侧相反的部分氧化物层26。例如，如果掺杂物从右侧注入，那么该注入向左倾斜，如箭头30示意性示出的，掺杂物的大部分可以穿透鳍124，并且到达位于相应鳍124左侧上的部分氧化物层26。一些掺杂物也可以穿透鳍124以及位于鳍124两侧上的部分氧化物层26。注入杂质中未停留在鳍124中的部分对鳍124的杂质浓度没有贡献。因此，通过氧化鳍124以使鳍124变薄并且调整注入的能量，减小了鳍124中的杂质浓度，该杂质浓度是由注入产生的。随着鳍124中杂质浓度的减小，形成的FinFET的阈值电压Vth增大。在注入硼的一些示例性实施例中，使用介于约4keV和约10keV之间的能量实施倾斜注入。在注入磷的可选示例性实施例中，可以使用介于约10keV和约30keV之间的能量实施倾斜注入。
另一方面，在区域28中，由于STI区22的部分22”，注入杂质停留在区域28中，因此区域28中的杂质浓度高。另外，还对注入的能量进行控制从而使注入杂质可以停留在区域28中。区域28中的高杂质浓度有助于降低在形成的FinFET的源极区和漏极区之间流动的漏电流，该漏电流流经区域28。作为注入和控制能量的结果，区域28中的注入杂质浓度高于半导体鳍124中部中的注入杂质浓度。
参照图5，去除氧化物层26，例如使用稀HF溶液。从而暴露鳍124。接下来，如图6A所示，形成栅极介电层36和栅电极38。根据一些实施例，栅极电介质36包括氧化硅、氮化硅或它们的多层。在可选的实施例中，栅极电介质36包括高k介电材料，因此在整个说明书中可选地被称为高k栅极电介质36。高k栅极电介质36可以具有大于约7.0的k值，并且可以包括金属氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb以及它们的组合的硅酸盐。栅极电介质36的形成方法可以包括分子束沉积(MBD)、原子层沉积(ALD)、物理汽相沉积(PVD)等。
在栅极电介质36上方形成栅电极38。栅电极38可以包括含金属的材料诸如多晶硅、TiN、TaN、TaC、Co、Ru、Al、它们的组合以及它们的多层。栅极电介质36和栅电极38的形成可以包括覆盖式沉积栅极介电层以及在栅极介电层上方沉积栅电极层，然后图案化栅极介电层和栅电极层。然后形成FinFET的剩余部件，包括源极和漏极区44(图6B)以及源极和漏极硅化物(未示出)，形成的FinFET是指FinFET42。在此不再论述这些部件的形成工艺。
图6B示出图6A中所示结构的截面图，其中截面图是由图6A中的平面剖切线6B-6B获得的。如图6B所示，区域28位于源极和漏极区44之间。由于STI区22的部分22”(图6A)的存在，区域28设置在栅电极38对电流控制较少的地方。因此，随着区域28具有高掺杂浓度，流经区域28的漏电流46减小。
图6A和图6B示出使用先栅极方法形成的栅极电介质36和栅电极38，其中在形成源极/漏极区44(图6B)之前形成栅极电介质36和栅电极38。在可选的实施例中，可以使用后栅极方法形成栅极电介质36和栅电极38，其中在形成相应的源极/漏极区44之后形成FinFET42的栅极电介质和栅电极。相应的工艺包括形成伪栅极(未示出)，形成源极/漏极区44，在源极/漏极区44上方形成层间电介质(ILD，未示出)，去除伪栅极以在ILD中形成凹槽，以及在凹槽中形成栅极介电层和栅电极层。然后实施CMP以去除栅极介电层和栅电极层位于ILD上方的部分。
在实施例中，由于注入杂质中的一些穿透鳍124，并因此对鳍124中的杂质浓度没有贡献，减小了不期望的鳍124中掺杂浓度的增加，这种不期望的增加是由区域28中的掺杂引起的。而且，采用在氧化工艺中变薄的鳍124，改进了所形成的FinFET42的器件性能。
根据实施例，一种方法包括氧化半导体鳍以在半导体鳍的相对侧壁上形成氧化物层。半导体鳍位于隔离区的顶面上方。在氧化之后，实施倾斜注入以将杂质注入半导体鳍。在倾斜注入之后去除氧化物层。
根据其他实施例，一种方法包括氧化半导体鳍以在半导体鳍的相对侧壁上形成氧化物层，其中半导体鳍位于STI区的顶面上方。半导体带位于半导体鳍的下方并连接到半导体鳍，并且半导体带与STI区齐平。在氧化之后，实施倾斜注入以将杂质注入半导体鳍，其中杂质具有第一导电类型。在倾斜注入步骤之后，去除氧化物层。该方法还包括形成包括位于半导体鳍侧壁上的一部分的栅极电介质，在栅极电介质上方形成栅电极，以及邻近栅极电介质和栅电极形成源极/漏极区。源极/漏极区具有与第一导电类型相反的第二导电类型。
根据又一些实施例，一种器件包括半导体衬底，以及位于半导体衬底的上方并且连接到半导体衬底的半导体带。半导体带具有基本上平的且处在第一平面中的第一侧壁，以及与第一侧壁相对的第二侧壁，其中第二侧壁基本上是直的且处在第二平面中。STI区设置在半导体带的相对侧上。半导体鳍设置在半导体带的上方并且连接到该半导体带，其中半导体鳍包括基本上是直的第三侧壁，其中第三侧壁处在与第一平面基本平行但不重叠的第三平面中。半导体鳍还包括基本上是直的且与第三侧壁相对的第四侧壁。第四侧壁处在与第二平面基本平行但不重叠的第四平面中。第三侧壁和第四侧壁位于第一平面和第二平面之间的区域中。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的构思和范围的情况下，在其中进行各种改变、替换和更改。而且，本申请的范围并不限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种方法，包括：
氧化半导体鳍以在所述半导体鳍的相对侧壁上形成氧化物层，其中所述半导体鳍位于隔离区的顶面上方；
在所述氧化之后，实施倾斜注入以将杂质注入所述半导体鳍；以及
在所述倾斜注入的步骤之后，去除所述氧化物层。
2.根据权利要求1所述的方法，还包括：
在所述半导体鳍的相对侧壁上形成栅极电介质；
在所述栅极电介质上方形成栅电极；以及
邻近所述栅极电介质和所述栅电极形成源极/漏极区。
3.根据权利要求2所述的方法，其中，所述杂质的导电类型与所述源极/漏极区的导电类型相反。
4.根据权利要求1所述的方法，其中，采用介于约20度和约45度之间的倾斜角度实施所述倾斜注入。
5.根据权利要求1所述的方法，其中，在所述倾斜注入期间，所述杂质的一部分穿透所述半导体鳍。
6.根据权利要求5所述的方法，其中，在所述倾斜注入期间，所述杂质的所述一部分穿透位于所述半导体鳍的相对侧壁上的所述氧化物层的一部分。
7.根据权利要求1所述的方法，其中，所述隔离区包括：
具有倾斜顶面的第一部分，所述倾斜顶面更靠近所述半导体鳍的部分高于所述倾斜顶面更远离所述半导体鳍的部分，并且与所述第一部分齐平的掺杂半导体区具有所述杂质的第一杂质浓度，所述杂质的第一杂质浓度高于所述杂质在所述半导体鳍的中部中的第二杂质浓度；以及
比所述第一部分更远离所述半导体鳍的第二部分，所述第二部分的顶面连接到所述第一部分的倾斜顶面并且低于所述第一部分的倾斜顶面。
8.一种方法，包括：
氧化半导体鳍以在所述半导体鳍的相对侧壁上形成氧化物层，其中所述半导体鳍位于浅沟槽隔离(STI)区的顶面上方，半导体带位于所述半导体鳍的下方并连接到所述半导体鳍，并且所述半导体带与所述STI区齐平；
在所述氧化之后，实施倾斜注入以将杂质注入所述半导体鳍，所述杂质具有第一导电类型；
在所述倾斜注入的步骤之后，去除所述氧化物层；
形成包括位于所述半导体鳍的侧壁上的一部分的栅极电介质；
在所述栅极电介质上方形成栅电极；以及
邻近所述栅极电介质和所述栅电极形成源极/漏极区，其中所述源极/漏极区具有与所述第一导电类型相反的第二导电类型。
9.一种器件，包括：
半导体衬底；
半导体带，位于所述半导体衬底上方并且连接到所述半导体衬底，所述半导体带包括：
基本上是平的且处在第一平面中的第一侧壁；和
与所述第一侧壁相对的第二侧壁，所述第二侧壁基本上是平的并且处在第二平面中；
浅沟槽隔离(STI)区，位于所述半导体带的相对侧上；以及
半导体鳍，位于所述半导体带上方并且连接到所述半导体带，所述半导体鳍包括：
基本上是平的第三侧壁，其中所述第三侧壁处在与所述第一平面基本平行但不重叠的第三平面中；和
基本上是平的并且与所述第三侧壁相对的第四侧壁，其中所述第四侧壁处在与所述第二平面基本平行但不重叠的第四平面中，并且所述第三侧壁和所述第四侧壁位于所述第一平面和所述第二平面之间的区域中。
10.根据权利要求9所述的器件，还包括：
栅极电介质，位于所述半导体鳍的第三侧壁和第四侧壁上；
栅电极，位于所述栅极电介质的上方；以及
源极/漏极区，邻近所述栅极电介质和所述栅电极。
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