CN114864577A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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CN114864577A
CN114864577A CN202210397518.8A CN202210397518A CN114864577A CN 114864577 A CN114864577 A CN 114864577A CN 202210397518 A CN202210397518 A CN 202210397518A CN 114864577 A CN114864577 A CN 114864577A
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top surface
fin
fin structures
semiconductor structure
gate
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谢奇颖
陈志容
陈建宏
李志岳
邱诚朴
卢世敏
林永崧
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United Microelectronics Corp
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Abstract

本发明公开一种半导体结构及其制作方法，该半导体结构包含一底材，其上具有多个鳍状结构；一绝缘氧化结构，设于该底材中，该绝缘氧化结构介于两个相邻的所述鳍状结构之间，其中该绝缘氧化结构具有一下凹的弧形顶面；一栅极，设于该多个鳍状结构上；一栅极介电层，设于该栅极与该多个鳍状结构之间；以及一漏极/源极掺杂区，设于各该多个鳍状结构中。

Description

半导体结构及其制作方法
本申请是中国发明专利申请(申请号：201810579878.3，申请日：2018年06月07日，发明名称：半导体结构及其制作方法)的分案申请。
技术领域
本发明涉及一种半导体结构及其制造方法，更具体来说，是一种鳍式场效晶体管(FinFET)元件结构。
背景技术
半导体存储器装置的更高集成度有助于满足消费者对卓越性能和低廉价格的需求。然而，随着芯片或管芯中电路元件的密度增加，相邻元件之间的距离变得越来越小，半导体制作工艺也遭遇到越来越多的挑战。
在制造纳米级鳍式场效晶体管元件的过程中，高分子聚合物的残留已成为一个严重的问题。在鳍片结构上图案化虚设多晶硅栅极之后，高分子聚合物残留物可能残存在芯片上并引起可靠性问题。高分子聚合物残留物倾向于积聚在向上突出的鳍片的侧壁与周围的浅沟槽隔离(STI)区域的顶部表面之间的不平顺的拐角处。这些高分子聚合物残余物难以被去除，并且可能在随后的置换金属栅极(RMG)制作工艺中导致在源极/漏极区域形成硅孔洞。
发明内容
本发明的主要目的在于提供一种改良的鳍式场效晶体管(FinFET)元件结构及其制造方法，以解决上述现有技术的不足与缺点。
根据一实施例，本发明半导体结构，包含一底材，其上具有多个鳍状结构；一绝缘氧化结构，设于该底材中，该绝缘氧化结构介于两个相邻的所述鳍状结构之间，其中该绝缘氧化结构具有一下凹的弧形顶面；一栅极，设于该多个鳍状结构上；一栅极介电层，设于该栅极与该多个鳍状结构之间；以及一漏极/源极掺杂区，设于各该多个鳍状结构中。
根据另一实施例，本发明半导体结构，包含一底材，其上具有一鳍状结构；一第一绝缘氧化结构，具有一第一弧形顶面，设于该鳍状结构的一侧；一第二绝缘氧化结构，具有一第二弧形顶面，相对于该第一绝缘氧化结构设于该鳍状结构的另一侧，其中该第一绝缘氧化结构与该第二绝缘氧化结构具有不同的深度；一栅极，设于该鳍状结构上；一栅极介电层，设于该栅极与该鳍状结构之间；以及一漏极/源极掺杂区，设于该鳍状结构中。
本发明另公开一种制作半导体元件的方法。首先提供一底材，其上具有一鳍状结构；再于该鳍状结构的一侧形成一第一绝缘氧化结构，具有一第一弧形顶面。接着，相对于该第一绝缘氧化结构的该鳍状结构的另一侧形成一第二绝缘氧化结构，具有一第二弧形顶面，其中该第一绝缘氧化结构与该第二绝缘氧化结构具有不同的深度。再于该鳍状结构上形成一栅极。再于该鳍状结构中形成一漏极/源极掺杂区。
本发明通过在绝缘氧化结构或浅沟绝缘区域形成下凹的弧形顶面，避免在与相邻的鳍片或鳍状结构的侧壁相连处产生不平顺的拐角，以解决聚合物残留物积聚问题并防止在源极/漏极区域造成硅空洞。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图8例示本发明实施例一种制作半导体元件的方法的示意图，其中，
图1～图5为剖面示意图；
图4为鳍状结构的放大示意图；
图6例示在鳍状结构和绝缘氧化结构上形成虚设栅极后的立体侧视图；
图7例示在虚设栅极两侧的鳍状结构中形成漏极/源极掺杂区后的立体侧视图；
图8例示完成置换金属栅极工艺后的立体侧视图。
主要元件符号说明
10 底材
101～105 鳍状结构
101a～105a 顶面
104SL 第一侧壁
104SR 第二侧壁
110 衬垫层
110a 顶面
112 硬掩模层
112a 顶面
200 绝缘氧化结构
201 第一绝缘氧化结构
201ac 第一弧形顶面
201ap 顶面
201t 最高上缘
201b 最低点
201tl 切线
202 第二绝缘氧化结构
202ac 第二弧形顶面
202ap 顶面
202t 最高上缘
202b 最低点
202tl 切线
260 栅极氧化层
280 虚设栅极
290 间隙壁
302、304 漏极/源极掺杂区
360 高介电常数栅极介电层
380 金属栅极
h1～h4 深度
P1、P2 间距
TROX 落差
θ1、θ2 夹角
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容还构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，还可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图8，其例示本发明实施例一种制作半导体元件的方法。如图1所示，首先提供一底材10，例如，硅基底、硅锗等半导体基底，其上具有鳍状结构101～105，其中鳍状结构101～104为密集平行排列在一起的连续的四条鳍状结构，而鳍状结构105则为孤立(或半孤立)的鳍状结构。例如，连续的四条鳍状结构101～104之间的间距(pitch)P1可以介于90纳米至200纳米，而孤立的鳍状结构105与最近的鳍状结构104的间距P2可以介于400纳米至1000纳米，但不限于此。此种连续的、密集平行的四条鳍状结构101～104和孤立的鳍状结构105可应用在静态随机存取存储器(SRAM)电路中，但不限于此。
由于鳍状结构101～105的制作方法为现有技术，包括光刻及蚀刻制作工艺，因此不再赘述。根据本发明实施例，此时在鳍状结构101～105上设有一衬垫层110及一硬掩模层112，例如，衬垫层110可以是二氧化硅层，而硬掩模层112可以是氮化硅层，但不限于此。
在完成鳍状结构101～105的定义后，接着在鳍状结构101～105之间形成绝缘氧化结构200，例如，在鳍状结构104的一侧(例如，图中鳍状结构104的左侧)，鳍状结构101～104之间，形成一第一绝缘氧化结构201，在相对于第一绝缘氧化结构201的鳍状结构104的另一侧(例如，图中鳍状结构104的右侧)，鳍状结构104～105之间，形成一第二绝缘氧化结构202。由于绝缘氧化结构200的制作方法为现有的浅沟绝缘或浅沟隔离技术，包括绝缘层沉积及化学机械研磨制作工艺，因此不再赘述。此时，经过研磨后，第一绝缘氧化结构201的顶面201ap、第二绝缘氧化结构202的顶面202ap与硬掩模层112的顶面112a约略齐平。
如图2所示，接着选择性的去除硬掩模层112，显露出衬垫层110的顶面110a。例如，硬掩模层112可以利用湿蚀刻方式来去除。此时，第一绝缘氧化结构201与衬垫层110的顶面110a会有一个落差TROX。根据本发明实施例，前述落差TROX需小于140埃，例如，介于20～140埃。根据本发明实施例，前述落差TROX可以通过硬掩模层112的厚度及化学机械研磨来控制。
如图3所示，接着进行一蚀刻制作工艺，例如，SiConiTM蚀刻，选择性的蚀刻显露出来的与衬垫层110和绝缘氧化结构200。已知，SiConiTM蚀刻是一种远端等离子体辅助的干式蚀刻制作工艺，包含让基板或晶片暴露于氢气、三氟化氮(NF3)与氨气(NH3)等离子体副产物下。例如，先使NF3和NH3激发转变成氟化氨(NH4F)和二氟化氨(NH4F.HF)，再让NH4F和NH4F.HF与氧化硅反应进行刻蚀，生成固态的六氟硅氨((NH4)2SiF6)刻蚀副产物，这种硅酸盐将阻止刻蚀反应的进一步进行。接着，进行退火以升华固态刻蚀副产物的步骤，刻蚀副产物((NH4)2SiF6)在高温下分解为气态的四氟化硅(SiF4)、氨气(NH3)和氟化氢(HF)。
经过前述蚀刻制作工艺后，鳍状结构101～105的顶面101a～105a和部分的侧壁被显露出来，其中顶面101a～105a约略齐平，而绝缘氧化结构200低于顶面101a～105a，并且形成弧形顶面。以下，术语“弧形顶面”指的是从剖面来看具有一定曲率的曲形顶面，换言之，所形成的弧形顶面不会包含有平面。
例如，第一绝缘氧化结构201的第一弧形顶面201ac和第二绝缘氧化结构202的第二弧形顶面202ac均低于顶面101a～105a。第一绝缘氧化结构201的第一弧形顶面201ac和第二绝缘氧化结构202的第二弧形顶面202ac从剖面看均为下凹的弧形顶面，更明确的说，第一绝缘氧化结构201的第一弧形顶面201ac和第二绝缘氧化结构202的第二弧形顶面202ac均为下凹的二氧化硅弧形顶面。其中，术语“下凹的”指的是垂直于底材10的主表面并向下深入底材10的主表面。
前述第一绝缘氧化结构201的第一弧形顶面201ac具有一最高上缘201t，其邻接鳍状结构104的一第一侧壁104SL，其中最高上缘201t具有一深度h1。以下，术语“深度”指的均是从鳍状结构101～105的顶面101a～105a往下计算的垂直距离，除非另有特别说明。第二绝缘氧化结构202的第二弧形顶面202ac具有一最高上缘202t，其邻接鳍状结构104的一第二侧壁104SR，最高上缘202t具有一深度h2，其中深度h2大于深度h1。根据本发明实施例，例如，深度h1介于400～500埃，深度h2介于450～550埃。
根据本发明实施例，下凹的第一弧形顶面201ac具有一最低点201b，约略位于相邻的鳍状结构103和104之间的下凹的弧形顶面201ac正中央处，此最低点201b具有一深度h3，介于500～700埃。下凹的第一弧形顶面202ac具有一最低点202b，约略位于相邻的鳍状结构104和105之间的下凹的弧形顶面202ac正中央处，此最低点202b具有一深度h4，介于500～600埃。根据本发明实施例，深度h3大于深度h4。
如图4所示，最高上缘201t与第一侧壁104SL接触点的切线201tl与第一侧壁104SL的夹角θ1约略介于130～140度，而最高上缘202t与第二侧壁104SR接触点的切线202tl与第二侧壁104SR的夹角θ2约略介于125～135度。
如图5及图6所示，接着于鳍状结构101～105和绝缘氧化结构200上形成虚设栅极280，例如，多晶硅栅极。在虚设栅极280与鳍状结构101～105以及在虚设栅极280与绝缘氧化结构200之间，可以形成有一栅极氧化层260。虚设栅极280可以是由单层的多晶硅所构成，也可以是由多层材料所构成，例如，多晶硅和氮化硅盖层，但不限于此。
如图7所示，接着在虚设栅极280的两侧形成间隙壁290，例如，氮化硅间隙壁，再于虚设栅极280两侧的鳍状结构101～105中形成漏极/源极掺杂区302、304，其中漏极/源极掺杂区302、304包含一外延应力层，例如，硅磷(SiP)外延层或硅锗(SiGe)外延层，但不限于此。上述漏极/源极掺杂区302、304的形成步骤乃周知工艺，故其细节不另赘述。举例来说，可以先在虚设栅极280两侧的鳍状结构101～105中蚀刻出凹沟，再进行外延步骤，并且进行离子布植，将N型或者P型掺质注入漏极/源极掺杂区302、304。
如图8所示，完成漏极/源极掺杂区302、304，最后进行置换金属栅极(replacementmetal gate，RMG)工艺，将虚设栅极280和栅极氧化层260分别置换成金属栅极380和高介电常数栅极介电层360。上述置换金属栅极工艺是周知工艺，故其细节不另赘述。举例来说，可以先进行层间介电层的沉积(图未示)，再进行化学机械研磨(CMP)工艺，研磨掉部分的层间介电层和部分的虚设栅极280，接着以蚀刻方式将剩下的虚设栅极280和栅极氧化层260去除，形成栅极沟槽，再于栅极沟槽内填入高介电常数栅极介电层360和金属栅极380，然后可以再进行一次化学机械研磨。
本发明通过在绝缘氧化结构200形成下凹的弧形顶面201ac、202ac，避免在与相邻的鳍状结构101～105的侧壁相连处产生不平顺的拐角，解决了聚合物残留物积聚问题并防止在源极/漏极区域造成硅空洞。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (9)

1.一种半导体结构，包含：
底材，其上具有多个鳍状结构；
绝缘氧化结构，设于该底材中，该绝缘氧化结构介于两个相邻的所述鳍状结构之间，其中该绝缘氧化结构具有下凹的弧形顶面；
栅极，设于该多个鳍状结构上；
栅极介电层，设于该栅极与该多个鳍状结构之间；以及
漏极/源极掺杂区，设于各该多个鳍状结构中。
2.如权利要求1所述的半导体结构，其中该多个鳍状结构包含四个连续的且彼此平行排列的直线型鳍状结构。
3.如权利要求1所述的半导体结构，其中该下凹的弧形顶面是一个下凹的二氧化硅弧形顶面。
4.如权利要求1所述的半导体结构，其中该下凹的弧形顶面具有最高上缘，其邻接各该多个鳍状结构的侧壁。
5.如权利要求4所述的半导体结构，其中该最上缘具有第一深度，介于400～500埃。
6.如权利要求1所述的半导体结构，其中该下凹的弧形顶面具有最低底面，位于所述两个相邻的鳍状结构之间的该下凹的弧形顶面正中央处。
7.如权利要求6所述的半导体结构，其中该最低底面具有第二深度，介于500～700埃。
8.如权利要求1所述的半导体结构，其中该栅极是金属栅极。
9.如权利要求1所述的半导体结构，其中该漏极/源极掺杂区包含外延应力层。
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