WO2016168994A1 - 隧穿晶体管及隧穿晶体管的制备方法 - Google Patents

隧穿晶体管及隧穿晶体管的制备方法 Download PDF

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Publication number
WO2016168994A1
WO2016168994A1 PCT/CN2015/077139 CN2015077139W WO2016168994A1 WO 2016168994 A1 WO2016168994 A1 WO 2016168994A1 CN 2015077139 W CN2015077139 W CN 2015077139W WO 2016168994 A1 WO2016168994 A1 WO 2016168994A1
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region
source region
layer
tunneling transistor
gate
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PCT/CN2015/077139
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English (en)
French (fr)
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吴昊
张臣雄
杨喜超
赵静
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华为技术有限公司
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Priority to PCT/CN2015/077139 priority Critical patent/WO2016168994A1/zh
Priority to CN201580077845.3A priority patent/CN107431089B/zh
Publication of WO2016168994A1 publication Critical patent/WO2016168994A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a method for fabricating a tunneling transistor and a tunneling transistor.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS transistors shrinks, their power consumption continues to increase. This is partly due to the increase in leakage current due to short channel effects and to the fact that the supply voltage of CMOS devices is difficult to reduce.
  • the supply voltage of the CMOS device is difficult to reduce mainly because the subthreshold swing SS is limited, and can not be lower than 60mV/decade at room temperature, that is, if the supply voltage is reduced by 60mV while maintaining the overdrive voltage, the source and drain leakage will be Increase by an order of magnitude.
  • the tunnel field effect transistor is considered to be a better device to replace the CMOS device to reduce the supply voltage because it can break through the SS limit.
  • the tunneling direction of carriers during operation of a conventional TFET is not in the same direction as the gate electric field, that is, a point tunneling mechanism. Due to the small tunneling area of the tunneling mechanism, the gated electric field of the tunneling junction is not strong, resulting in low carrier tunneling probability, which makes the TFET have the disadvantage of small tunneling current.
  • Embodiments of the present invention provide a method for fabricating a tunneling transistor.
  • the line tunneling mechanism is used to increase the tunneling probability of the tunneling transistor, thereby increasing the tunneling current of the tunneling transistor.
  • a first aspect of the embodiments of the present invention provides a tunneling transistor, including:
  • a substrate a first source region, a drain region, a second source region, a channel, a halo layer, a gate dielectric layer, and a gate region, wherein the first source region and the drain region are formed in the substrate Above the substrate, the second source region is formed between the first source region and the drain region such that a channel is formed between the second source region and the drain region.
  • the halo layer is formed in the second source region Above the partial surface, the gate dielectric layer and the gate region are sequentially formed over the halo layer.
  • the tunneling transistor further includes:
  • the tunneling transistor further includes:
  • the tunneling transistor is N A tunneling transistor
  • the source region is heavily doped with P-type ions
  • the drain region and the halo layer are heavily doped with N-type ions.
  • the tunneling transistor is P A type tunneling transistor
  • the source region is heavily doped with N-type ions
  • the drain region and the halo layer are heavily doped with P-type ions.
  • the P-type ion comprises boron ion, difluoro At least one of a boron ion or an indium ion, the N-type ion comprising at least one of a phosphorus ion, an arsenic ion, or a cerium ion.
  • a second aspect of the embodiments of the present invention provides a method for fabricating a tunneling transistor, including:
  • a gate dielectric layer and a gate region are sequentially formed over the halo layer.
  • the tunneling transistor In conjunction with the second aspect, in a first possible implementation of the second aspect, the tunneling transistor The preparation method also includes:
  • a first via hole and a second via hole are formed over the silicide layer.
  • a first possible implementation of the second aspect in a second possible implementation of the second aspect, the forming a first source region and a drain region over a surface of the substrate, including :
  • the forming a second source between the first source region and the drain region Areas including:
  • the sidewall is used as an implantation barrier layer, and the first region is subjected to oblique ion implantation to form the second source region.
  • a part of the surface of the second source region forms a halo layer, including:
  • Dip ion implantation is performed on the second source region to form the halo layer.
  • the second source region Performing oblique ion implantation to form the halo layer includes:
  • Ge ion implantation is performed on the second source region, and oblique ion implantation of the same type as that of the drain region implant is performed to form the halo layer.
  • the inclination angle ranges from 30° to 45°.
  • the Forming a gate dielectric layer and a gate including:
  • a gate dielectric layer material and a gate material are sequentially deposited on a surface of the halo layer away from the second source region to form the gate dielectric layer and the gate region.
  • the tunneling transistor is an N-type tunneling transistor
  • the source region is heavily doped with P-type ions
  • the drain region and the halo layer are heavily doped with N-type ions.
  • the tunneling transistor is a P-type tunneling transistor
  • the source region is heavily doped with N-type ions
  • the drain region and the halo layer are heavily doped with P-type ions.
  • the P-type ion comprises boron ion, boron difluoride ion or indium At least one of ions, the N-type ion comprising at least one of a phosphorus ion, an arsenic ion, or a cerium ion.
  • the tunneling transistor provided by the present invention since the gate regions are stacked on the gate dielectric layer and the second source region, when the gate region is loaded with an electrical signal, the gate region is loaded with an electrical signal.
  • the direction of the electric field is vertical. It can be seen that the electric field direction of the electrical signal loaded in the gate region is consistent with the tunneling direction of the electron, that is, the line tunneling mechanism.
  • line tunneling occurs at the second source region, thereby improving tunneling efficiency, thereby increasing the on-state current of the tunneling transistor.
  • the tunneling transistor provided by the present invention is an N-type tunneling transistor, since a large dose of Ge is implanted in the second source region to form a silicon germanium material after annealing, in the tunneling transistor, the The source-side material of the tunneling transistor has a forbidden band width to further increase the on-state current of the entire device; if the tunneling transistor provided by the present invention is a P-type tunneling transistor, the high-dose implanted Ge in the halo layer is annealed After forming a silicon germanium material, in the tunneling transistor, the forbidden band width of the halo layer material of the tunneling transistor is reduced, and the on-state current of the entire device is further improved.
  • FIG. 1 is a cross-sectional view of a tunneling transistor according to an embodiment of the present invention.
  • FIG. 2 is a flow chart of preparing a tunneling transistor according to a preferred embodiment of the present invention.
  • FIG. 3 to FIG. 10 are schematic diagrams showing a specific process of a method for fabricating a tunneling transistor of FIG. 2;
  • FIG. 11 is a flow chart of preparing a tunneling transistor compatible with a planar CMOS process according to the present invention.
  • FIG. 12 to FIG. 22 are schematic diagrams showing a flow chart of a method for fabricating a tunneling transistor and a specific integration scheme of a CMOS device.
  • Embodiments of the present invention provide a method for fabricating a tunneling transistor.
  • the line tunneling mechanism is used to increase the tunneling probability of the tunneling transistor, thereby increasing the tunneling current of the tunneling transistor.
  • a tunneling transistor including a substrate 10, a first source region 50, a drain region 60, a second source region 80, a channel 90, and a halo layer.
  • the substrate 10 has a shallow trench isolation process (shallow trench)
  • the doped substrate of the isolation, STI structure may be a silicon on insulator (SOI) substrate.
  • the substrate 10 may also be a binary or ternary of silicon (Si), germanium (Ge) or germanium silicon, gallium arsenide, etc., group IV, or group III-V, or group IV-IV. Any of a compound or a crucible on an insulating substrate.
  • the tunneling transistor when the tunneling transistor is an N-type tunneling transistor, the substrate 10 is doped with an N-type ion doping, or an N-type well is fabricated, when the tunneling transistor is a P
  • the substrate 10 when tunneling a transistor, the substrate 10 is doped with a P-type ion doping, or a P-type well is fabricated, wherein the P-type ion includes at least at least boron (B) ions or indium (In) ions.
  • B boron
  • the N-type ion includes at least one of a phosphorus (P) ion, an arsenic (As) ion, or a strontium (Sb) ion.
  • the first source region 50 and the drain region 60 may be formed by forming a dummy gate region on a surface of the substrate 10. Forming sidewalls at both ends of the dummy gate region, and providing an implantation barrier layer on one surface of the substrate 10, and performing ion implantation to form a first source by using the sidewall spacer and the implantation barrier layer as a mask In the polar region 50, another implant barrier layer is disposed on the other side surface of the doped substrate 10, and the drain region 60 is formed by ion implantation using the sidewall spacer and the implant barrier layer as a mask.
  • a rapid annealing process RTA
  • Laser Annealing a laser annealing process
  • the ion and repair implants of the polar region 50 and the drain region 60 cause lattice damage of the substrate 10, and then another annealing is performed to complete the halo layer 100 after the halo layer 100 is implanted later.
  • the ion and repair implants cause lattice damage of the substrate 10.
  • the first source region 50 region and the drain region 60 may complete the halo layer 100 implant later. Annealing is then performed to activate all of the impurity ions and repair implants at one time to cause lattice damage to the substrate 10.
  • the tunneling transistor when the tunneling transistor is an N-type tunneling transistor, the drain region 60 is heavily doped with N-type ions, and the first source region 50 is heavily doped with P-type ions;
  • the tunneling transistor is a P-type tunneling transistor, the drain region 60 is heavily doped with a P-type ion, and the first source region 50 is heavily doped with an N-type ion;
  • the P-type ion includes At least one of boron ions or indium ions;
  • the N-type ions include at least one of phosphorus ions or arsenic ions and strontium ions.
  • the second source region 80 and the halo layer 100 may be formed by removing the dummy gate region and performing large tilt ion implantation to form the second source region 80 and the halo layer 100.
  • the injection direction is the direction of the first source region 50
  • the tilt angle of the large tilt ion implantation ranges from 30° to 45°
  • the large tilt angle implanting ions is specifically divided into three steps: 1) and the first The source region 50 is doped with a larger energy type of Super-Steep Retrograde Source (SSRS) to form the second source region 80; 2) a large dose of C, Ge Injecting, the channel 90 is amorphized, thereby reducing the subsequent implant junction depth, increasing the tunneling electric field between the halo layer 100 and the second source region 80, thereby increasing the tunneling current; 3)
  • the drain region 60 is doped with an ultra low energy pocket of the same type to form the halo layer 100.
  • a rapid annealing process RTA
  • a laser annealing process Laser Annealing
  • the tunneling transistor when the tunneling transistor is an N-type tunneling transistor, the second source region 80 is heavily doped with P-type ions, and the halo layer 100 is heavily doped with N-type ions;
  • the tunneling transistor is a P-type tunneling transistor, the second source region 80 is heavily doped with N-type ions, and the halo layer 100 is heavily doped with P-type ions;
  • the P-type ions include At least one of a boron ion or an indium ion;
  • the N-type ion includes at least one of a phosphorus ion, an arsenic ion, or a cerium ion.
  • the gate dielectric layer 20 and the gate region 30 sequentially deposit a gate dielectric layer and a metal gate region over the halo layer 100, and etch the gate dielectric layer and the metal gate region to obtain the present The gate dielectric layer 20 and the gate region 30 in the embodiment.
  • the gate dielectric layer 20 may be a combination of thermally oxidized silicon dioxide and ALD formed HfO 2 . In other embodiments, the gate dielectric layer 20 can also be a combination of one or more materials of high K dielectric, silicon oxide, HfSiON, or other oxide materials.
  • the metal gate material may be TiN. In other embodiments, the metal gate material may be other metal materials such as Ti, Ta, Al, and W. The gate dielectric layer and the metal gate after deposition are CMP planarized to form a gate dielectric layer 20 and a gate region 30 sequentially on the halo layer 90.
  • the gate region 30 is stacked on the gate dielectric layer 20 and the second source region 80, when the gate region 30 is loaded with an electrical signal, the gate region 30 is loaded.
  • the electric field direction of the electrical signal is vertical. It can be seen that the electric field direction of the electrical signal loaded by the gate region 30 coincides with the tunneling direction of the electron, that is, the line tunneling mechanism.
  • the tunneling transistor is tunneled, Line tunneling occurs at the second source region 80, thereby improving tunneling efficiency, thereby increasing the on-state current of the tunneling transistor.
  • a large dose of Ge is annealed to form a silicon germanium material, and the energy of the Ge implantation is adjusted.
  • the silicon germanium material is located in the second source region 80 below the halo layer 100. Reducing a band gap of the source material of the tunneling transistor to further increase an on-state current of the entire device.
  • the silicon germanium material is located at the halo layer 100, reducing the The forbidden band width of the halo layer material of the tunneling transistor is further increased to further increase the on-state current of the entire device.
  • the tunneling transistor further includes a silicide layer 70 formed on the first source region and the drain region, and a first via formed on the silicide layer And a second via 120, wherein the silicide layer 70, the first via 110, and the second via 120 are formed by forming the first source region 50 and After the drain region 60 is removed, the remaining implant barrier layer is removed, and a metallization process of the surface of the substrate 10 of the first source region 50 and the drain region 60 is performed to enable the first source a portion of the surface of the polar region 50 and the drain region 60 forms a silicide layer 70; after the gate dielectric layer 20 and the gate region 30 are formed, the oxide filling layer is formed (the formation process is: Before the forming the second source region, performing oxide or low-k material filling on the substrate 10 and the dummy gate region) forming a first via hole on the first source region by an etching process 110. Form a second via hole 120 on the drain region.
  • the first via hole 110 and the second via hole 120 may also be formed by forming the first source region 50 region and the drain region 60 after Forming the gate dielectric layer 20 and the gate region 30 without performing a metallization process on the surface of the substrate 10 of the first source region 50 and the drain region 60, but completing the After the gate dielectric layer 20 and the gate region 30, the first via hole 110 is formed on the first source region by an etching process on the oxide filling layer, and the drain region is formed on the drain region Forming a second via hole 120 in which a metallization process is performed on the surface of the substrate 10 of the first source region 50 and the drain region 60 to Forming a silicide layer 70 in the two via locations, and on portions of the first source region 50 and the drain region 60, and then the first via 110 and the second via The through holes of 120 are filled with material.
  • FIG. 2 is a flow chart of preparing a tunneling transistor according to a preferred embodiment of the present invention. Can In an understanding, some of the steps included in this embodiment may also be omitted, and other steps may also be added. It can be understood that in other embodiments, the following multiple steps may be combined into one step, or one step may be split into multiple steps, and the order between the steps may be adjusted as needed.
  • the preparation process of the tunneling transistor includes the following steps.
  • a substrate 10 is provided.
  • the substrate 10 is a doped substrate having a shallow trench isolation (STI) structure, as shown in FIG.
  • the substrate 10 may be a silicon on insulator (SOI) substrate.
  • the substrate 10 may also be a binary or ternary of silicon (Si), germanium (Ge) or germanium silicon, gallium arsenide, etc., group IV, or group III-V, or group IV-IV. Any of a compound or a crucible on an insulating substrate.
  • the tunneling transistor when the tunneling transistor is an N-type tunneling transistor, the substrate 10 is doped with an N-type ion doping, or an N-type well is fabricated, when the tunneling transistor is a P
  • the substrate 10 when tunneling a transistor, the substrate 10 is doped with a P-type ion doping, or a P-type well is fabricated, wherein the P-type ion includes at least at least boron (B) ions or indium (In) ions.
  • B boron
  • the N-type ion includes at least one of a phosphorus (P) ion, an arsenic (As) ion, or a strontium (Sb) ion.
  • Step S102 forming a dummy gate oxide layer 20a and a dummy gate region 30a on a surface of the substrate 10.
  • forming a dummy gate oxide layer 20a and a dummy gate region 30a on one surface of the substrate 10 may be formed by sequentially depositing a thermal oxide layer on one surface of the substrate 10. Or a dummy gate oxide layer, and a dummy gate layer, an etch hard mask is disposed in a middle portion of a surface of the dummy gate layer, and the hard mask is etched to obtain the dummy gate in the embodiment of the present invention.
  • the oxide layer 20a and the dummy gate region 30a may be formed by sequentially depositing a thermal oxide layer on one surface of the substrate 10.
  • an etch hard mask is disposed in a middle portion of a surface of the dummy gate layer, and the hard mask is etched to obtain the dummy gate in the embodiment of the present invention.
  • the oxide layer 20a and the dummy gate region 30a may be formed by sequentially depositing a thermal oxide layer on one surface of the substrate 10.
  • an etch hard mask is disposed in a middle portion of a
  • a dummy gate oxide layer 20a is formed on one surface of the substrate 10 by a thermal oxidation technique.
  • the dummy gate oxide layer 20a may be silicon dioxide.
  • the dummy gate oxide layer 20a may also be a high-k dielectric, silicon oxide, HfSiON, or other oxide material or the like.
  • a dummy gate layer 30a is formed on the surface of the dummy gate oxide layer 20a away from the substrate 10 by using a low pressure chemical vapor deposition (LPCVD) technique.
  • the dummy gate material may be polysilicon (poly).
  • the dummy gate material may also be titanium nitride or the like.
  • a hard mask a is disposed in a middle portion of a surface of the dummy gate layer 30a (the hard mask may be a photoresist or a hard mask combination of an oxide-nitride-oxide (ONO)),
  • the dummy gate layer of the hard mask provided in the middle of the surface and the dummy gate oxide layer are etched to form the dummy gate oxide layer 20a and the dummy gate on a surface of the doped substrate 10.
  • Area 30a Since the hard mask a has a function of protecting the surface of the dummy gate layer 30a covered by the surface and the surface of the dummy gate layer 30a from being etched, the arrangement of the hard mask a is provided.
  • the surface of the dummy gate layer 30a is etched, the surface of the dummy gate layer 30a covered by the hard mask layer and the area below the surface of the dummy gate layer 30a are not etched, and the hard mask is not covered.
  • the surface of the dummy gate layer 30a of the film a and the region below the surface of the dummy gate layer 30a are gradually etched away due to no protection, thereby forming a sidewall short on the surface of the substrate 10.
  • the gate oxide layer 20a and a dummy gate region 30a are gradually etched away due to no protection, thereby forming a sidewall short on the surface of the substrate 10.
  • step S103 sidewall spacers 40 are formed at both ends of the dummy gate region 30a.
  • the sidewall material is isotopically deposited on the substrate 10, the dummy gate region 30a, the sidewall of the dummy gate oxide layer 20a, and the top of the dummy gate region 30a to form a sidewall material.
  • the sidewall material 40 is in the embodiment, the sidewall material is silicon nitride.
  • the material of the sidewall spacer may also be silicon oxide, low-k dielectric or other insulation. A combination of one or more of the materials.
  • the spacer layer 40 is anisotropic dry etched (RIE), leaving some residue on the side of the dummy gate region 30a as the spacer 40 in the present embodiment.
  • the sidewall spacer 40 has a protection gate region, a source/drain region, a distance between the source-drain doped region and the gate region, and a function of reducing the gate region and the source-drain contact hole capacitance.
  • Step S104 forming a first source region 50 and a drain region 60 on a surface of the substrate 10.
  • forming the first source region 50 and the drain region 60 on one surface of the substrate 10 may be formed by: providing an implantation barrier layer on one surface of the substrate 10, The first source region 50 is formed by ion implantation using the sidewall spacer 40 and the implantation barrier layer as a mask. Another implantation barrier layer is disposed on the other side surface of the doped substrate 10, and the drain region 60 is formed by ion implantation using the sidewall spacer 40 and the implantation barrier layer as a mask.
  • an implantation barrier layer b is disposed on the right side surface of the doped substrate 10, and the sidewalls 40 and the implantation barrier layer b are used as a mask, and the surface is disposed on the surface. Injecting barrier layer b and The substrate 10 of the side wall 40 is ion implanted to form the first source region 50.
  • an implantation barrier layer c is disposed on the right side surface of the doped substrate 10 , and the sidewall 40 and the implantation barrier layer c are used as a mask, and the hard surface is disposed on the surface. The mask c and the substrate 10 of the spacer 40 are ion-implanted to form the drain region 60.
  • a rapid annealing process RTA
  • Laser Annealing a laser annealing process
  • the ion and repair implants of the polar region 50 and the drain region 60 cause lattice damage of the substrate 10, and then another annealing is performed to complete the halo layer 100 after the halo layer 100 is implanted later.
  • the ion and repair implants cause lattice damage to the substrate 10.
  • the first source region 50 region and the drain region 60 may also be annealed after the completion of the halo layer 100 is implanted, and all impurity ions are activated at one time and the implant is repaired. The lattice damage of the substrate 10 is described.
  • the remaining implant barrier layer c is removed, and the first source region 50 and the drain region 60 are performed.
  • a metallization process such that a silicide layer 70 (shown in FIG. 8) is formed on portions of the first source region 50 and the drain region 60 to facilitate subsequent generation of source and drain contacts.
  • a hole can be connected to the first source region 50 domain and the drain region 60.
  • the tunneling transistor when the tunneling transistor is an N-type tunneling transistor, the drain region 60 is heavily doped with N-type ions, and the first source region 50 is heavily doped with P-type ions;
  • the tunneling transistor is a P-type tunneling transistor, the drain region 60 is heavily doped with a P-type ion, and the first source region 50 is heavily doped with an N-type ion;
  • the P-type ion includes At least one of boron ions or indium ions;
  • the N-type ions include at least one of phosphorus ions or arsenic ions and strontium ions.
  • Step S105 forming a second source region 80 between the first source region 50 and the drain region 60 and forming a halo layer 100 on a portion of the surface of the second source region, such that the A channel 90 is formed between the second source region 80 and the drain region 60.
  • a second source region 80 is formed between the first source region 50 and the drain region 60, and a halo layer 100 is formed on a portion of the surface of the second source region.
  • Forming the channel 90 between the second source region 80 and the drain region 60 may be formed by removing the dummy gate oxide layer 20a and the dummy gate region 30a, and forming a large tilt ion implantation formation.
  • Second source region Field 80, a large oblique angle ion implantation on a portion of the surface of the second source region 80 forms the halo layer 100 such that a channel 90 is formed between the second source region 80 and the drain region 60 .
  • an oxide or low-k material is filled around the substrate 10, the dummy gate oxide layer 20a, and the dummy gate region 30a to chemically oxidize the oxide or low-k material.
  • a mechanical polishing (CMP) or low temperature thermal oxidation + spin on glass (LTO + SOG) planarization process exposes the dummy gate region 30a.
  • the dummy gate region 30a and the dummy gate oxide layer 20a are wet etched, and then the sidewall spacer 40 is used as an implantation barrier layer to perform large tilt ion implantation to form the second source region 80 and the The halo layer 100, wherein the injection direction is the direction of the first source region 50, and the tilt angle of the large tilt ion implantation ranges from 30° to 45°, and the implanting ions at the large tilt angle is specifically divided into three steps: 1) a super-steep retrograde source (SSRS) of a larger energy doping type of the first source region 50 is implanted to form the second source region 80; 2) The dose of C and Ge implants causes the channel 90 to be amorphized, thereby reducing the subsequent implant junction depth, increasing the tunneling electric field between the halo layer 100 and the second source region 80, thereby increasing tunneling. Current; 3) ultra low energy pocket implant of the same type as the drain region 60 doping to form the halo layer 100.
  • SSRS super-stee
  • a rapid annealing process RTA
  • a laser annealing process Laser Annealing
  • the tunneling transistor when the tunneling transistor is an N-type tunneling transistor, the second source region 80 is heavily doped with P-type ions, and the halo layer 100 is heavily doped with N-type ions;
  • the tunneling transistor is a P-type tunneling transistor, the second source region 80 is heavily doped with N-type ions, and the halo layer 100 is heavily doped with P-type ions;
  • the P-type ions include At least one of boron ions or indium ions;
  • the N-type ions include at least one of phosphorus ions or arsenic ions and strontium ions.
  • the purpose of the large dip angle implantation is to form an implantation shadow region as shown in the drawing, so that the channel 90 can be self-aligned and not affected by the injection, so that The fixed injection shadow region width (as shown in FIG. 8), at the same time, ensures that the second source region 80 and the halo layer 100 can be self-aligned with the gate region 30.
  • the implantation shadow region can be adjusted in the channel by adjusting the planarization height and the large tilt ion implantation angle in step S105. The magnitude of the projection distance in 90, thereby adjusting the size of the undoped region in the channel 90.
  • step S106 the gate dielectric layer 20 and the gate region 30 are sequentially formed on the halo layer 100.
  • sequentially forming the gate dielectric layer 20 and the gate region 30 on the halo layer 100 may be formed by sequentially depositing a gate dielectric layer and a metal on the halo layer 100.
  • the gate dielectric layer and the gate region 30 in the present embodiment are obtained by etching the gate dielectric layer and the metal gate region in a gate region.
  • a gate dielectric layer or an atomic layer deposition (ALD) high-k gate dielectric layer 20 is formed on one surface of the halo layer 100 by thermal oxidation technology.
  • the gate dielectric layer 20 may be a combination of thermally oxidized silicon dioxide and ALD formed HfO 2 .
  • the gate dielectric layer 20 can also be a combination of one or more materials of high K dielectric, silicon oxide, HfSiON, or other oxide materials.
  • a layer of the gate dielectric layer 20 away from the halo layer 20 is formed by an atomic layer deposition (ALD) technique, a low pressure chemical vapor deposition (LPCVD) technique, a physical vapor deposition (PVD) technique, or the like.
  • a metal gate is deposited on the surface to form a gate region.
  • the metal gate material may be TiN.
  • the metal gate material may also be other metal materials such as Ti, Ta, Al, and W. Wait.
  • the gate dielectric layer and the metal gate after deposition are CMP planarized to form a gate dielectric layer 20 and a gate region 30 sequentially on the halo layer 90.
  • the gate region 30 is stacked on the gate dielectric layer 20 and the second source region 80, when the gate region 30 is loaded with an electrical signal, the gate region 30 is loaded.
  • the electric field direction of the electrical signal is vertical. It can be seen that the electric field direction of the electrical signal loaded by the gate region 30 coincides with the tunneling direction of the electron, that is, the line tunneling mechanism.
  • line tunneling occurs at the second source region 80, thereby improving tunneling efficiency, thereby increasing the on-state current of the tunneling transistor.
  • a large dose of Ge is annealed to form a silicon germanium material, and the energy of the Ge implantation is adjusted.
  • the silicon germanium material is located in the second source region 80 below the halo layer 100. Reducing a band gap of the source material of the tunneling transistor to further increase an on-state current of the entire device.
  • the silicon germanium material is located at the halo layer 100, reducing the The forbidden band width of the halo layer material of the tunneling transistor is further increased to further increase the on-state current of the entire device.
  • Step S107 forming a first via hole 110 on the first source region, forming a second via hole 120 on the drain region, and performing a back end process preparation of the tunneling transistor for the purpose of forming A complete tunneling transistor.
  • the first via hole 110 is formed on the first source region, and the second via hole 120 is formed on the drain region in the following manner.
  • the oxide filling layer is formed (the formation process is: before the formation of the second source region, around the substrate 10, the dummy gate region Forming an oxide or a low-k material fill) a first via hole 110 is formed on the first source region by an etching process, and a second via hole 120 is formed on the drain region.
  • the first via hole 110 and the second via hole 120 may also be formed by forming the first source region 50 region and the drain region 60 after Forming the gate dielectric layer 20 and the gate region 30 without performing a metallization process on the surface of the substrate 10 of the first source region 50 and the drain region 60, but completing the After the gate dielectric layer 20 and the gate region 30, the first via hole 110 is formed on the first source region by an etching process on the oxide filling layer, and the drain region is formed on the drain region Forming a second via hole 120 in which a metallization process is performed on the surface of the substrate 10 of the first source region 50 and the drain region 60 to Forming a silicide layer 70 in the two via locations, and on portions of the first source region 50 and the drain region 60, and then the first via 110 and the second via The through holes of 120 are filled with material.
  • FIG. 11 is a flow chart of preparing a tunneling transistor compatible with a planar CMOS process according to the present invention. It can be understood that some steps included in this embodiment may also be omitted, and other steps may also be added according to the same. It can be understood that in other embodiments, the following multiple steps may be combined into one step, or one step may be split into multiple steps, and the order between the steps may be adjusted as needed.
  • the preparation process of the tunneling transistor includes the following steps. This embodiment introduces an N-type tunneling transistor as an example.
  • the integration of a CMOS device and an N-TFET is taken as an example to describe the preparation of a tunneling transistor compatible with a planar CMOS process, and the integration of a CMOS device and a P-TFET is only required in a CMOS device and N- Based on the integrated process of the TFET, the doping type and the implant barrier layer are performed. Modify it.
  • a substrate which is a doped substrate having a shallow trench isolation process structure, as shown in FIG.
  • the substrate may be a silicon on insulator (SOI) substrate on an insulating substrate.
  • the substrate may also be silicon (Si), germanium (Ge) or germanium silicon, gallium arsenide or the like group IV, or group III-V, or group IV-IV binary or ternary, Any of a compound or a crucible on an insulating substrate.
  • the N-MOSFET region, the substrate doping type is N-type ion doping, or N-type well fabrication, P-MOSFET region, the substrate doping type is P-type ion doping Or performing P-type well fabrication.
  • the tunneling transistor is described by taking an N-TFET as an example.
  • the N-TFET region is doped with N-type ion doping or N-type.
  • the substrate doping type is P-type ion doping, or P-type well fabrication, wherein the P-type ions include boron (B) at least one of ions or indium (In) ions; the N-type ions include at least one of phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions.
  • the P-type ions include boron (B) at least one of ions or indium (In) ions
  • the N-type ions include at least one of phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions.
  • Step S202 depositing a dummy gate stack and CMOS region thinning on the substrate.
  • an oxide layer (Oxide), polysilicon (poly), oxide layer (Oxide) polysilicon (poly), and oxide-nitride-oxide material (Oxide-Nitride-Oxide) are sequentially deposited on the substrate.
  • ONO oxide-nitride-oxide material
  • a hard mask is placed on the TFET device, and then the CMOS region is thinned by photolithography.
  • Step S203 formation of a dummy gate.
  • a hard mask is respectively disposed on the N-MOSFET, the P-MOSFET, and the N-TFET, and a dummy gate is etched by a photolithography technique to form a dummy gate, thereby defining an N-MOSFET, a P- The gate region of the MOSFET and N-TFET.
  • Step S204 the formation of the side wall.
  • the remaining hard masks on the N-MOSFET, the P-MOSFET, and the N-TFET are removed, and the low pressure chemical vapor deposition (LPCVD) technique is used on the substrate, the dummy
  • LPCVD low pressure chemical vapor deposition
  • the sidewall material is silicon nitride, of course, in another implementation.
  • the material of the sidewall spacer may also be a combination of one or more of silicon oxide, low-k dielectric or other insulating materials.
  • the sidewall spacer has a protection gate region, a source/drain region, a distance between the source-drain doped region and the gate region, and a function of reducing the gate region and the source-drain contact hole capacitance.
  • Step S205 the N-MOSFET ion implantation and the formation of the N-TFET drain region.
  • the first source regions of the P-MOSFET and the N-TFET are blocked by providing a barrier layer for the N-MOSFET source region, the N-MOSFET drain region, and the N-TFET drain.
  • the pole region is N-type ion implanted to form the N-MOSFET source region, the N-MOSFET drain region, and the N-TFET drain region.
  • the first source region of the N-TFET is photolithographically blocked, the N-TFET drain region is N-type ion implanted, and in another embodiment, if the TFET is P In the tunneling transistor, the drain region of the P-TFET is photolithographically blocked, and the first source region of the P-TFET is N-type ion implanted.
  • Step S206 the P-MOSFET ion implantation and the formation of the first source region of the N-TFET.
  • the drain regions of the N-MOSFET and the N-TFET are blocked by providing a barrier layer for the P-MOSFET source region, the P-MOSFET drain region, and the N-TFET.
  • the first source region is P-type ion implanted to form the P-MOSFET source region, the P-MOSFET drain region, and the N-TFET first source region.
  • the drain region of the N-TFET is photolithographically blocked, and the first region of the N-TFET is subjected to P-type ion implantation.
  • the TFET is a P-type tunnel When the transistor is passed through, the first source region of the P-TFET is photolithographically blocked, and the P-TFET drain region is subjected to P-type ion implantation.
  • the N-MOSFET source region, the N-MOSFET drain region, the N-TFET drain region, the P-MOSFET source region, and the P-MOSFET drain are formed.
  • a rapid annealing process is performed to activate the N-MOSFET source-drain region, the P-MOSFET source-drain region, and the N-TFET first source region And ions in the drain region.
  • the remaining implant barrier layer is removed.
  • the N-MOSFET source and drain regions, the P-MOSFET source and drain regions, and the N-TFET first source region and the drain region can be connected.
  • Step S207 filling of the oxide and CMP process.
  • an oxide or low-k material is filled around the substrate, the N-MOSFET, the P-MOSFET, and the N-TFET dummy gate, for the oxide or low-k material.
  • a chemical mechanical polishing (CMP) or low temperature thermal oxidation + spin-on glass (LTO + SOG) planarization process is performed to expose the Poly layer at the upper end of the N-TFET.
  • the purpose of the CMP process is to control the total oxide fill layer thickness.
  • Step S208 the second source region of the N-TFET and the halo layer are formed such that a channel is formed between the N-TFET second source region and the N-TFET drain region.
  • the exposed Poly layer on the N-TFET and the underlying Oxide, Poly, and Oxide are removed by wet etching, and then the sidewall is used as an implantation barrier layer to implant ions at a large tilt angle to form an N-TFET.
  • the large dip angle injection direction is the first source region direction, and the large dip angle ranges from 30° to 45°, and the large dip angle implanted ions are specifically divided into three steps : 1) super-steep retrograde source (SSRS) injection of the same energy type as the first source region doping of the N-TFET to form the N-TFET second a source region; 2) a large dose of C, Ge implants, such that the N-TFET channel is amorphized, thereby reducing the subsequent implant junction depth, increasing the N-TFET halo layer and the N-TFET A tunneling electric field between the second source regions, thereby increasing the tunneling current; 3) an ultra-low energy pocket implant of the same type as the drain region doping to form the halo layer.
  • SSRS super-steep retrograde source
  • the second source region of the N-TFET is heavily doped with P-type ions, and the halo layer is heavily doped with N-type ions; in another embodiment, if the tunneling transistor When the P-type tunneling transistor is used, the second source region is heavily doped with N-type ions, and the halo layer is heavily doped with P-type ions; the P-type ions include boron ions, gallium ions or indium ions. At least one of the types; the N type The ions include at least one of phosphorus ions or arsenic ions.
  • the purpose of the large dip angle implantation is to form the implantation shadow region shown in FIG. 19 so that the halo layer can be self-aligned and not affected by the injection, so that The fixed injection shadow zone width (as shown in FIG. 19), at the same time, ensures that the second source region and the halo layer are self-aligned with the gate region.
  • the magnitude of the projection distance of the implantation shadow region in the channel can be adjusted by adjusting the planarization height and the large tilt ion implantation angle in step S207, thereby adjusting the size of the undoped region in the channel.
  • Step S209 forming a gate dielectric layer and a gate region of the N-TFET.
  • a gate dielectric layer and a metal gate material are deposited, and the filled metal gate is planarized by a CMP process to form a gate dielectric layer and a gate region of the N-TFET.
  • Step S210 forming a gate region of the N-MOSFET and the P-MOSFET.
  • an oxide is deposited in the N-TFET region to protect the N-TFET from subsequent deposition of the N-MOSFET and P-MOSFET metal gate material.
  • a CMOS gate material is deposited, and the filled metal gate is planarized by a CMP process to form gate regions of the N-MOSFET and the P-MOSFET.
  • the gate region since the gate regions are stacked on the gate dielectric layer and the second source region, when the gate region is loaded with an electrical signal, the gate region The direction of the electric field of the loaded electrical signal is the vertical direction. It can be seen that the electric field direction of the electrical signal loaded in the gate region is consistent with the tunneling direction of the electron, that is, the line tunneling mechanism.
  • line tunneling occurs at the second source region, thereby improving tunneling efficiency, thereby increasing the on-state current of the tunneling transistor.
  • a large dose of Ge is annealed to form a silicon germanium material, and the energy of the Ge implantation is adjusted.
  • the silicon germanium material is located in the second source region below the halo layer. Smaller the tunneling transistor source material band gap, further increasing the on-state current of the entire N-TFET device, in the P-type tunneling transistor, the silicon germanium material is located in the halo layer, reducing the The forbidden band width of the halo layer material of the tunneling transistor further increases the on-state current of the entire N-TFET device.
  • Step S211 performing N-MOSFET, P-MOSFET, and N-TFET vias and a standard CMOS process back-end process for forming a complete CMOS transistor and tunneling transistor.
  • N-MOSFET, P-MOSFET, and N-TFET via fabrication can be formed in the following manner. Referring to FIG. 22, the oxide-filled layer is etched in the N-MOSFET, the P-MOSFET. And forming a via hole in the first source region of the N-TFET, forming another via hole on the N-MOSFET, the P-MOSFET, and the drain region of the N-TFET, and then performing the via hole formed The metal material is deposited such that the N-MOSFET, the P-MOSFET, and the source and drain of the N-TFET are connected through the via source region and the drain region.
  • the N-MOSFET, P-MOSFET, and N-TFET via fabrication may also be formed by forming the N-MOSFET source and drain regions, the P-MOSFET source and drain regions. And after the N-TFET first source region and the drain region, the N-MOSFET source-drain region and the P-MOSFET source-drain region are not performed before the gate dielectric layer and the gate region are formed And the first source region and the drain region metallization process of the N-TFET, but after completing the gate dielectric layer and the gate region, the oxide filling layer is formed in an etching process by an etching process Forming the first via location on the N-MOSFET source region, the P-MOSFET source region, and the N-TFET first source region, forming the N-MOSFET drain region, Forming a position of the second via hole 120 on a drain region of the P-MOSFET and the drain region of the N-TFET, in which the pair of source and drain regions of the N-MOSFET

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Abstract

提供了一种隧穿晶体管及隧穿晶体管的制备方法，其中，一种隧穿晶体管，包括衬底（10）、第一源极区域（50）、漏极区域（60）、第二源极区域（80）、沟道（90）、晕环层（100）、栅介质层（20）及栅极区域（30），所述第一源极区域（50）及漏极区域（60）形成于所述衬底（10）之上，所述第二源极区域（80）形成于所述第一源极区域（50）及所述漏极区域（60）之间，使得所述第二源极区域（80）与所述漏极区域（60）之间形成沟道（90），所述晕环层（100）形成于所述第二源极区域（80）的部分表面之上，所述栅介质层（20）及所述栅极区域（30）依次形成于所述晕环层（100）之上。还提供了一种隧穿晶体管的制作方法。采用线隧穿机制提高了隧穿晶体管的隧穿几率，进而增大了隧穿晶体管的隧穿电流。

Description

隧穿晶体管及隧穿晶体管的制备方法 技术领域
本发明涉及半导体技术领域，具体涉及了一种隧穿晶体管及隧穿晶体管的制备方法。
背景技术
微电子器件一般制作在半导体衬底上然后集成电路。互补金属氧化物半导体器件(Complementary Metal Oxide Semiconductor，CMOS)是集成电路的核心单元，其尺寸遵循摩尔(Moore)定律，以获得更优异的性能、更高的集成密度以及更低的成本。
然而，随着CMOS晶体管尺寸的缩小，其功耗也持续增加。部分原因是因为短沟道效应引起的泄漏电流的增加，同时也归咎于CMOS器件的供电电压难以缩减。其中，CMOS器件的供电电压难以缩减主要是由于亚阈值摆幅SS受限，室温下不能低于60mV/decade，即如果保持过驱动电压不变的情况下降低供电电压60mV，其源漏漏电将增加一个量级。
隧穿场效应晶体管(tunnel field effect transistor，TFET)由于能突破SS限制，被认为是替代CMOS器件降低供电电压的较好的器件。目前，常规TFET的工作时的载流子的隧穿方向与栅电场不在同一方向上，即点隧穿机制。由于点隧穿机制隧穿面积较小，隧穿结的栅控电场不强，导致载流子隧穿几率较低，使得TFET存在隧穿电流小的缺点。
发明内容
本发明实施例提供隧穿晶体管的制备方法，采用线隧穿机制，提高了隧穿晶体管的隧穿几率，进而增大了隧穿晶体管的隧穿电流。
本发明实施例第一方面提供一种隧穿晶体管，包括：
衬底、第一源极区域、漏极区域、第二源极区域、沟道、晕环层、栅介质层及栅极区域，所述第一源极区域及所述漏极区域形成于所述衬底之上，所述第二源极区域形成于所述第一源极区域及所述漏极区域之间，使得所述第二源极区域与所述漏极区域之间形成沟道，所述晕环层形成于所述第二源极区域的 部分表面之上，所述栅介质层及所述栅极区域依次形成于所述晕环层之上。
结合第一方面，在第一方面的第一种可能的实施方式中，所述隧穿晶体管还包括：
形成于所述栅极区域两端的侧墙，且所述侧墙高度不低于20nm。
结合第一方面或第一方面的第一种可能的实施方式，在第一方面的第二种可能的实施方式中，述隧穿晶体管还包括：
形成于所述第一源极区域及所述漏极区域之上的硅化物层；
形成于所述硅化物层之上的第一通孔和第二通孔。
结合第一方面或第一方面的第一种可能的实施方式或第一方面的第二种可能的实施方式，在第一方面的第三种可能的实施方式中，所述隧穿晶体管为N型隧穿晶体管，所述源区域进行P型离子重掺杂，所述漏极区域及所述晕环层进行N型离子重掺杂。
结合第一方面或第一方面的第一种可能的实施方式或第一方面的第二种可能的实施方式，在第一方面的第四种可能的实施方式中，所述隧穿晶体管为P型隧穿晶体管，所述源区域进行N型离子重掺杂，所述漏极区域及所述晕环层进行P型离子重掺杂。
结合第一方面的第三种可能的实施方式或第一方面的第四种可能的实施方式，在第一方面的第五种可能的实施方式中，所述P型离子包括硼离子、二氟化硼离子或铟离子中的至少一种，所述N型离子包括磷离子、砷离子或锑离子中的至少一种。
本发明实施例第二方面提供一种隧穿晶体管的制备方法，包括：
提供衬底；
在所述衬底的一表面上形成第一源极区域及漏极区域；
在所述第一源极区域及所述漏极区域之间形成第二源极区域，使得所述第二源极区域与所述漏极区域之间形成沟道；
在所述第二源极区域的部分表面形成一晕环层；
在所述晕环层之上依次形成栅介质层及栅极区域。
结合第二方面，在第二方面的第一种可能的实施方式中，所述隧穿晶体管 的制备方法还包括：
在所述第一源极区域及所述漏极区域之上形成硅化物层；
在所述硅化物层之上形成第一通孔和第二通孔。
第二方面的第一种可能的实施方式，在第二方面的第二种可能的实施方式中，所述在所述衬底的一表面之上形成第一源极区域和漏极区域，包括：
在所述衬底之上形成一假栅，在所述假栅的两端形成所述侧墙；
在假栅的一侧提供第一注入阻挡层，以所述侧墙及所述第一注入阻挡层为掩膜进行离子注入形成所述第一源极区域；
去除余下的所述第一注入阻挡层，在所述假栅的另一侧提供第二注入阻挡层，以所述侧墙及所述第二硬掩膜层为掩膜刻蚀所述衬底，进行离子注入形成所述漏极区域。
结合第二方面的第二种可能的实施方式，在第二方面的第三种可能的实施方式中，所述在所述第一源极区域及所述漏极区域之间形成第二源极区域，包括：
在所述假栅的两端形成氧化物填充层；
去除所述假栅以形成第一区域；
以所述侧墙为注入阻挡层，对所述第一区域进行倾角离子注入形成所述第二源极区域。
结合第二方面的第三种可能的实施方式，在第二方面的第四种可能的实施方式中，所述第二源极区域的部分表面形成晕环层，包括：
在所述第二源极区域上进行倾角离子注入形成所述晕环层。
结合第二方面的第三种可能的实施方式或第二方面的第四种可能的实施方式，在第二方面的第五种可能的实施方式中，所述在所述第二源极区域上进行倾角离子注入形成所述晕环层，包括：
在所述第二源极区域上进行C、Ge离子注入，以及进行与所述漏极区域注入离子类型相同的倾角离子注入，以形成所述晕环层。
结合第二方面的第三种可能的实施方式或第二方面的第四种可能的实施方式或第二方面的第五种可能的实施方式，在第二方面的第六种可能的实施方 式中，所述倾角的范围为30°～45°。
结合第二方面的第四种可能的实施方式或第二方面的第五种可能的实施方式，在第二方面的第七种可能的实施方式中，所述在所述晕环层之上依次形成栅介质层及栅极，包括：
在所述晕环层远离所述第二源极区域的表面上依次沉积栅介质层材料及栅极材料，以形成所述栅介质层及所述栅极区域。
结合第二方面或第二方面的第一种至第七种任一种可能的实现方式，在第二方面的第八种可能的实施方式中，所述隧穿晶体管为N型隧穿晶体管，所述源区域进行P型离子重掺杂，所述漏极区域及所述晕环层进行N型离子重掺杂。
结合第二方面或第二方面的第一种至第七种任一种可能的实现方式，在第二方面的第九种可能的实施方式中，所述隧穿晶体管为P型隧穿晶体管，所述源区域进行N型离子重掺杂，所述漏极区域及所述晕环层进行P型离子重掺杂。
结合第二方面的第八种或第九种任一种可能的实现方式，在第一方面的第十种可能的实现方式中，所述P型离子包括硼离子、二氟化硼离子或铟离子中的至少一种，所述N型离子包括磷离子、砷离子或锑离子中的至少一种。
本发明提供的隧穿晶体管，由于栅极区域层叠设置在所述栅介质层及所述第二源极区域上，当所述栅极区域加载电信号时，所述栅极区域加载的电信号的电场方向为竖直方向。由此可见，所述栅极区域加载的电信号的电场方向与电子的隧穿方向一致，即为线隧穿机制。当隧穿晶体管发生隧穿时，在所述第二源极区域处发生线隧穿，从而提高了隧穿效率，进而提高了隧穿晶体管的开态电流。
另外，若本发明提供的隧穿晶体管为N型隧穿晶体管，由于在所述第二源极区域中大剂量注入Ge在经过退火后形成锗硅材料，在隧穿晶体管中，减小所述隧穿晶体管的源端材料禁带宽度，进一步提高整个器件的开态电流；若本发明提供的隧穿晶体管为P型隧穿晶体管，由于在所述晕环层中大剂量注入Ge在经过退火后形成锗硅材料，在隧穿晶体管中，减小所述隧穿晶体管的晕环层材料禁带宽度，进一步提高整个器件的开态电流。
附图说明
为了更清楚地说明本发明实施例技术方案，下面将对实施例和现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例提供的一种隧穿晶体管的剖视图；
图2为本发明一较佳实施方式的隧穿晶体管的制备流程图；
图3至图10为图2一种隧穿晶体管的制备方法的具体流程示意图；
图11为本发明一基于平面CMOS工艺兼容的隧穿晶体管的制备流程图；
图12至图22为图11一种隧穿晶体管的制备方法与CMOS器件的具体集成方案流程示意图。
具体实施方式
本发明实施例提供隧穿晶体管的制备方法，采用线隧穿机制，提高了隧穿晶体管的隧穿几率，进而增大了隧穿晶体管的隧穿电流。
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明的一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参见图1，为本发明实施例提供的一种隧穿晶体管，其包括衬底10、第一源极区域50、漏极区域60、第二源极区域80、沟道90、晕环层100、栅介质层20及栅极区域30，所述第一源极区域50及所述漏极区域60形成于所述衬底10之上，所述第二源极区域80形成于所述第一源极区域50及所述漏极区域60之间，使得所述第二源极区域50与所述漏极区域60之间形成沟道90，所述晕环层100形成于所述第二源极区域50的部分表面之上，所述栅介质层20及所述栅极区域30依次形成于所述晕环层100之上。器件开启时，在所述栅极区域30及所述栅介质层20重叠的部分的下方，在所述晕环层100与所述第二源极区域80的界面处发生隧穿，形成隧穿电流。
在本实施方式中，所述衬底10为具有浅槽隔离工艺(shallow trench  isolation，STI)结构的掺杂衬底，所述衬底10可以为绝缘体上硅(silicon on Insulator，SOI)衬底。在其他实施方式中，所述衬底10也可以为硅(Si)、锗(Ge)或者锗硅、镓砷等IV族、或III-V族、或者IV-IV族的二元或三元、化合物或者绝缘衬底上的锗中的任意一种。
在本实施方式中，当所述隧穿晶体管为N型隧穿晶体管时，所述衬底10掺杂类型为N型离子掺杂，或进行N型阱制作，当所述隧穿晶体管为P型隧穿晶体管时，所述衬底10掺杂类型为P型离子掺杂，或进行P型阱制作，其中，所述P型离子包括硼(B)离子或铟(In)离子中的至少一种；所述N型离子包括磷(P)离子、砷(As)离子或锑(Sb)离子中的至少一种。
所述第一源极区域50及所述漏极区域60可由以下方式形成：在所述衬底10的一表面上形成一假栅区域。在所述假栅区域的两端形成侧墙，在所述衬底10的一侧表面设置一注入阻挡层，以所述侧墙及所述注入阻挡层为掩膜进行离子注入形成第一源极区域50，在所述掺杂衬底10的另一侧表面设置另一注入阻挡层，以侧墙及所述注入阻挡层为掩膜进行离子注入形成漏极区域60。
在本实施方式中，在形成所述第一源极区50域及所述漏极区域60后，可以进行快速退火工艺(RTA)或者激光退火工艺(Laser Annealing)，从而激活所述第一源极区域50及所述漏极区域60的离子及修复注入造成所述衬底10的晶格损伤，然后在后期完成所述晕环层100注入后再进行另外一次退火激活所述晕环层100的离子及修复注入造成所述衬底10的晶格损伤，在另一实施方式中，所述第一源极区50域及所述漏极区域60可在后期完成所述晕环层100注入后进行退火，一次性激活所有杂质离子及修复注入造成所述衬底10的晶格损伤。
在本实施方式中，当所述隧穿晶体管为N型隧穿晶体管时，所述漏极区域60进行N型离子重掺杂，所述第一源极区域50进行P型离子重掺杂；当所述隧穿晶体管为P型隧穿晶体管时，所述漏极区域60进行P型离子重掺杂，所述第一源极区域50进行N型离子重掺杂；所述P型离子包括硼离子或铟离子中的至少一种；所述N型离子包括磷离子或砷离子、锑离子中的至少一种。
所述第二源极区域80及所述晕环层100可以以下方式形成：去除所述假栅区域，进行大倾角离子注入，以形成所述第二源极区域80以及所述晕环层100， 其中，注入方向为所述第一源极区域50方向，所述大倾角离子注入的倾角范围为30°～45°，所述大倾角注入离子具体分为三步骤：1)与所述第一源极区域50掺杂类型相同的较大能量的超陡倒退掺杂源(Super-Steep Retrograde Source，简称SSRS)注入，以形成所述第二源极区域80；2)大剂量的C、Ge注入，使得所述沟道90非晶化，从而使后续注入结深减小，增加晕环层100与第二源极区域80之间的隧穿电场，进而增大隧穿电流；3)与所述漏极区域60掺杂类型相同的超低能的pocket注入，以形成所述晕环层100。
在本实施方式中，在形成所述第二源极区域80及所述晕环层100后，进行快速退火工艺(RTA)或者激光退火工艺(Laser Annealing)，从而激活所述第二源极区域80及所述晕环层100的离子。
在本实施方式中，当所述隧穿晶体管为N型隧穿晶体管时，所述第二源极区域80进行P型离子重掺杂，所述晕环层100进行N型离子重掺杂；当所述隧穿晶体管为P型隧穿晶体管时，所述第二源极区域80进行N型离子重掺杂，所述晕环层100进行P型离子重掺杂；所述P型离子包括硼离子或铟离子中的至少一种；所述N型离子包括磷离子、砷离子或锑离子中的至少一种。
所述栅介质层20及所述栅极区域30在所述晕环层100之上依次沉积一栅介质层及金属栅极区域，刻蚀所述栅介质层及所述金属栅极区域得到本实施方式中的所述栅介质层20及所述栅极区域30。
在本实施例中，所述栅介质层20可以是热氧化形成的二氧化硅与ALD形成的HfO2的组合。在其他实施方式中，所述栅介质层20也可以为高K电介质、硅氧化物、HfSiON，或者其他氧化物材料等的一种或多种材料的组合。本实施方式中，所述金属栅材料可以是TiN，在其他实施方式中，所述金属栅材料也可以是Ti、Ta、Al、W等其他金属材料等。对沉积后的栅介质层及金属栅进行CMP平坦化，从而在所述晕环层90之上依次形成栅介质层20及栅极区域30。
在本实施方式中，由于栅极区域30层叠设置在所述栅介质层20及所述第二源极区域80上，当所述栅极区域30加载电信号时，所述栅极区域30加载的电信号的电场方向为竖直方向。由此可见，所述栅极区域30加载的电信号的电场方向与电子的隧穿方向一致，即为线隧穿机制。当隧穿晶体管发生隧穿时，在所 述第二源极区域80处发生线隧穿，从而提高了隧穿效率，进而提高了隧穿晶体管的开态电流。
另外，大剂量的Ge在经过退火后形成锗硅材料，调整Ge注入的能量，在N型隧穿晶体管中，使所述锗硅材料位于所述晕环层100下方的第二源极区域80，减小所述隧穿晶体管的源端材料禁带宽度，进一步提高整个器件的开态电流，在P型隧穿晶体管中，使所述锗硅材料位于所述晕环层100，减小所述隧穿晶体管的晕环层材料禁带宽度，进一步提高整个器件的开态电流。
在一实施方式中，所述隧穿晶体管还包括形成于所述第一源极区域及所述漏极区域之上的硅化物层70，形成于所述硅化物层之上的第一通孔110和第二通孔120，其中，所述硅化物层70、所述第一通孔110和所述第二通孔120可由以下方式形成：在形成所述第一源极区50域及所述漏极区域60后，去除余下的注入阻挡层，进行所述第一源极区域50及所述漏极区域60的所述衬底10表面的金属化工艺，以使得在所述第一源极区域50及所述漏极区域60的部分表面形成一硅化物层70；在形成所述栅介质层20及所述栅极区域30之后，对所述氧化物填充层(形成过程为：在形成所述第二源极区域之前，对所述衬底10、所述假栅区域周围进行氧化物或低K材料填充)通过刻蚀工艺在所述第一源极区域上形成第一通孔110，在所述漏极区域上形成第二通孔120。
在另一实施方式中，所述第一通孔110和所述第二通孔120也可以由以下方式形成：在形成所述第一源极区50域及所述漏极区域60后，在形成所述栅介质层20及所述栅极区域30之前不进行所述第一源极区域50及所述漏极区域60的所述衬底10表面的金属化工艺，而是在完成所述栅介质层20及所述栅极区域30之后，对所述氧化物填充层通过刻蚀工艺在所述第一源极区域上形成所述第一通孔110位置，在所述漏极区域上形成所述第二通孔120位置，在所述两个通孔位置中，对所述第一源极区域50及所述漏极区域60的所述衬底10表面的进行金属化工艺，以使得在两个通孔位置中，及在所述第一源极区域50及所述漏极区域60的部分表面形成一硅化物层70，然后对所述第一通孔110及第二通孔120的通孔进行材料填充。
请参见图2，图2为本发明一较佳实施方式的隧穿晶体管的制备流程图。可 以理解的，本实施例中包含部分步骤也可以省略，其他步骤也可以根据增加。可以理解的，在其他实施方式中，以下多个步骤可合并成一个步骤，或者一个步骤可拆分成多个步骤，步骤之间的顺序可以根据需要进行调整。所述隧穿晶体管的制备流程包括以下步骤。
步骤S101，提供一衬底10，所述衬底10为具有浅槽隔离工艺(shallow trench isolation，STI)结构的掺杂衬底，如图3所示。在本实施方式中，所述衬底10可以为绝缘衬底上的硅(silicon on Insulator，SOI)衬底。在其他实施方式中，所述衬底10也可以为硅(Si)、锗(Ge)或者锗硅、镓砷等IV族、或III-V族、或者IV-IV族的二元或三元、化合物或者绝缘衬底上的锗中的任意一种。
在本实施方式中，当所述隧穿晶体管为N型隧穿晶体管时，所述衬底10掺杂类型为N型离子掺杂，或进行N型阱制作，当所述隧穿晶体管为P型隧穿晶体管时，所述衬底10掺杂类型为P型离子掺杂，或进行P型阱制作，其中，所述P型离子包括硼(B)离子或铟(In)离子中的至少一种；所述N型离子包括磷(P)离子、砷(As)离子或锑(Sb)离子中的至少一种。
步骤S102，在所述衬底10的一表面上形成一假栅氧化层20a及一假栅区域30a。
在本实施方式中，在所述衬底10的一表面上形成一假栅氧化层20a及一假栅区域30a可以由以下方式形成：在所述衬底10的一表面依次沉积热氧化层(或者假栅氧化层)，及沉积假栅层，在所述假栅层的一表面的中部设置一刻蚀硬掩膜，刻蚀所述硬掩膜而得到本发明实施方式中的所述假栅氧化层20a及所述假栅区域30a。
具体地，请参阅如图4，利用热氧化技术在所述衬底10的一表面形成一假栅氧化层20a，在本实施例中，所述假栅氧化层20a可以是二氧化硅。在其他实施方式中，所述假栅氧化层20a也可以为高K电介质、硅氧化物、HfSiON，或者其他氧化物材料等。利用低压化学气相沉积(Low pressure chemical vapor deposition，LPCVD)技术，在所述假栅氧化层20a远离所述衬底10的一表面沉积假栅材料，形成一假栅层30a，本实施方式中，所述假栅材料可以是多晶硅(polysilicon，poly)，在其他实施方式中，所述假栅材料也可以是氮化钛等。 在所述假栅层30a的一表面的中部设置一硬掩膜a，(该硬掩膜可以为光刻胶，或者氧化物-氮化物-氧化物(ONO)的硬掩膜组合)，对表面的中部设置的硬掩膜的所述假栅层以及所述假栅氧化层进行蚀刻，从而在所述掺杂衬底10的一表面上形成所述假栅氧化层20a及所述假栅区域30a。由于所述硬掩膜a具有保护其覆盖的所述假栅层30a的表面及所述假栅层30a的表面以下的区域不被蚀刻的作用，因此，对所述设置硬掩膜a的所述假栅层30a的表面进行蚀刻时，所述假栅层30a被所述硬掩膜层覆盖的表面及所述假栅层30a表面以下的区域不被蚀刻掉，而未覆盖所述硬掩膜a的所述假栅层30a的表面及所述假栅层30a表面以下的区域则由于没有保护而逐渐蚀刻掉，从而在所述衬底10的一表面上形成一侧壁陡直的假栅氧化层20a及一假栅区域30a。
步骤S103，在所述假栅区域30a的两端形成侧墙40。
具体地，请参阅图5，在所述衬底10、所述假栅区域30a及所述假栅氧化层20a侧壁、所述假栅区域30a顶部各项同性沉积一侧墙材料，以形成一侧墙层40，在本实施方式中，所述侧墙材料为氮化硅，当然，在另一实施方式中，所述侧墙的材料也可为硅氧化物，低K电介质或者其他绝缘材料的一种或多种的组合。利用各向异性干法刻蚀(RIE)所述侧墙层40，在所述假栅区域30a的侧边留下一些残余物，作为本实施方式中的所述侧墙40。本发明实施例中，所述侧墙40具有保护栅极区域、源漏极区域，调整源漏掺杂区域与栅极区域的距离，降低栅极区域与源漏接触孔电容等作用。
步骤S104，在所述衬底10的一表面上形成第一源极区域50及一漏极区域60。
在本实施方式中，在所述衬底10的一表面形成第一源极区域50及一漏极区域60可以由以下方式形成：在所述衬底10的一侧表面设置一注入阻挡层，以所述侧墙40及所述注入阻挡层为掩膜进行离子注入形成第一源极区域50。在所述掺杂衬底10的另一侧表面设置另一注入阻挡层，以侧墙40及所述注入阻挡层为掩膜进行离子注入形成漏极区域60。
具体地，请参阅图6，在所述掺杂衬底10的右侧表面设置一注入阻挡层b，以所述侧墙40及所述注入阻挡层b为掩膜，对表面设置的所述注入阻挡层b及所 述侧墙40的所述衬底10进行离子注入，以形成所述第一源极区域50。请一并参阅图7，在所述掺杂衬底10的右侧表面设置一注入阻挡层c，以所述侧墙40及所述注入阻挡层c为掩膜，对表面设置的所述硬掩膜c及所述侧墙40的所述衬底10进行离子注入，形成所述漏极区域60。
在本实施方式中，在形成所述第一源极区50域及所述漏极区域60后，可以进行快速退火工艺(RTA)或者激光退火工艺(Laser Annealing)，从而激活所述第一源极区域50及所述漏极区域60的离子及修复注入造成所述衬底10的晶格损伤，然后在后期完成所述晕环层100注入后再进行另外一次退火激活所述晕环层100的离子及修复注入造成所述衬底10的晶格损伤。在另一实施方式中，所述第一源极区50域及所述漏极区域60也可在后期完成所述晕环层100注入后进行退火，一次性激活所有杂质离子及修复注入造成所述衬底10的晶格损伤。
在本实施方式中，在形成所述第一源极区50域及所述漏极区域60后，去除余下的注入阻挡层c，进行所述第一源极区域50及所述漏极区域60金属化工艺，以使得在所述第一源极区域50及所述漏极区域60的部分表面形成一硅化物层70(如图8所示)，以便于后续生成源极及漏极通过通孔能与所述第一源极区50域及所述漏极区域60进行连接。
在本实施方式中，当所述隧穿晶体管为N型隧穿晶体管时，所述漏极区域60进行N型离子重掺杂，所述第一源极区域50进行P型离子重掺杂；当所述隧穿晶体管为P型隧穿晶体管时，所述漏极区域60进行P型离子重掺杂，所述第一源极区域50进行N型离子重掺杂；所述P型离子包括硼离子或铟离子中的至少一种；所述N型离子包括磷离子或砷离子、锑离子中的至少一种。
步骤S105，在所述第一源极区域50及所述漏极区域60之间形成第二源极区域80以及在所述第二源极区域的部分表面形成一晕环层100，使得所述第二源极区域80与所述漏极区域60之间形成沟道90。
在本实施方式中，在所述第一源极区域50及所述漏极区域60之间形成第二源极区域80以及在所述第二源极区域的部分表面形成一晕环层100，使得所述第二源极区域80与所述漏极区域60之间形成沟道90可以由以下方式形成：去除所述假栅氧化层20a及所述假栅区域30a，大倾角离子注入形成所述第二源极区 域80，在所述第二源极区域80的部分表面上大倾角离子注入形成所述晕环层100，使得所述第二源极区域80与所述漏极区域60之间形成沟道90。
具体地，请参阅图9，对所述衬底10、所述假栅氧化层20a及所述假栅区域30a周围进行氧化物或低K材料填充，对所述氧化物或低K材料进行化学机械研磨(CMP)或低温热氧化+旋涂玻璃(LTO+SOG)平坦化工艺，暴露出所述假栅区域30a。利用湿法腐蚀所述假栅区域30a及所述假栅氧化层20a，然后以所述侧墙40为注入阻挡层，进行大倾角离子注入，以形成所述第二源极区域80以及所述晕环层100，其中，注入方向为所述第一源极区域50方向，所述大倾角离子注入的倾角范围为30°～45°，所述大倾角注入离子具体分为三步骤：1)与所述第一源极区域50掺杂类型相同的较大能量的超陡倒退掺杂源(Super-Steep Retrograde Source，简称SSRS)注入，以形成所述第二源极区域80；2)大剂量的C、Ge注入，使得所述沟道90非晶化，从而使后续注入结深减小，增加晕环层100与第二源极区域80之间的隧穿电场，进而增大隧穿电流；3)与所述漏极区域60掺杂类型相同的超低能的pocket注入，以形成所述晕环层100。
在本实施方式中，在形成所述第二源极区域80及所述晕环层100后，进行快速退火工艺(RTA)或者激光退火工艺(Laser Annealing)，从而激活所述第二源极区域80及所述晕环层100的离子。
在本实施方式中，当所述隧穿晶体管为N型隧穿晶体管时，所述第二源极区域80进行P型离子重掺杂，所述晕环层100进行N型离子重掺杂；当所述隧穿晶体管为P型隧穿晶体管时，所述第二源极区域80进行N型离子重掺杂，所述晕环层100进行P型离子重掺杂；所述P型离子包括硼离子或铟离子中的至少一种；所述N型离子包括磷离子或砷离子、锑离子中的至少一种。
在本实施方式中，大倾角注入的目的是形成图中所示的注入阴影区，使所述沟道90中靠近所述漏端区域60能自对准的不受注入的影响，这样达到即固定注入阴影区宽度(如图8所示)，又同时能保证所述第二源极区域80与所述晕环层100能与栅极区域30自对准的进行掺杂。在本实施方式中，可以通过调节步骤S105中的平坦化高度及大倾角离子注入角度来调节注入阴影区在所述沟道 90中投射距离的大小，从而调节所述沟道90中非掺杂区域的大小。
步骤S106，在所述晕环层100之上依次形成栅介质层20及栅极区域30。
在本实施方式中，在所述晕环层100之上依次形成栅介质层20及栅极区域30可以由以下方式形成：在所述晕环层100之上依次沉积一栅介质层及一金属栅极区域，刻蚀所述栅介质层及所述金属栅极区域得到本实施方式中的所述栅介质层20及所述栅极区域30。
具体地，请参阅图9，利用热氧化技术在所述晕环层100的一表面形成一栅介质层或原子层沉积(ALD)一层高K栅介质层20，在本实施例中，所述栅介质层20可以是热氧化形成的二氧化硅与ALD形成的HfO2的组合。在其他实施方式中，所述栅介质层20也可以为高K电介质、硅氧化物、HfSiON，或者其他氧化物材料等的一种或多种材料的组合。利用原子层淀积(ALD)技术、低压化学气相沉积(Low pressure chemical vapor deposition，LPCVD)技术、物理气相沉积(PVD)技术等，在所述栅介质层20远离所述晕环层20的一表面沉积金属栅，形成一栅极区域，本实施方式中，所述金属栅材料可以是TiN，在其他实施方式中，所述金属栅材料也可以是Ti、Ta、Al、W等其他金属材料等。对沉积后的栅介质层及金属栅进行CMP平坦化，从而在所述晕环层90之上依次形成栅介质层20及栅极区域30。
在本实施方式中，由于栅极区域30层叠设置在所述栅介质层20及所述第二源极区域80上，当所述栅极区域30加载电信号时，所述栅极区域30加载的电信号的电场方向为竖直方向。由此可见，所述栅极区域30加载的电信号的电场方向与电子的隧穿方向一致，即为线隧穿机制。当隧穿晶体管发生隧穿时，在所述第二源极区域80处发生线隧穿，从而提高了隧穿效率，进而提高了隧穿晶体管的开态电流。
另外，大剂量的Ge在经过退火后形成锗硅材料，调整Ge注入的能量，在N型隧穿晶体管中，使所述锗硅材料位于所述晕环层100下方的第二源极区域80，减小所述隧穿晶体管的源端材料禁带宽度，进一步提高整个器件的开态电流，在P型隧穿晶体管中，使所述锗硅材料位于所述晕环层100，减小所述隧穿晶体管的晕环层材料禁带宽度，进一步提高整个器件的开态电流。
步骤S107，在所述第一源极区域上形成第一通孔110，在所述漏极区域上形成第二通孔120，以及进行所述隧穿晶体管的后端工艺制备，目的是为了形成一个完整的隧穿晶体管。
在本实施例中，在所述第一源极区域上形成第一通孔110，在所述漏极区域上形成第二通孔120可以由以下的方式形成，请参阅图10，在形成所述栅介质层20及所述栅极区域30之后，对所述氧化物填充层(形成过程为：在形成所述第二源极区域之前，对所述衬底10、所述假栅区域周围进行氧化物或低K材料填充)通过刻蚀工艺在所述第一源极区域上形成第一通孔110，在所述漏极区域上形成第二通孔120。
在另一实施方式中，所述第一通孔110和所述第二通孔120也可以由以下方式形成：在形成所述第一源极区50域及所述漏极区域60后，在形成所述栅介质层20及所述栅极区域30之前不进行所述第一源极区域50及所述漏极区域60的所述衬底10表面的金属化工艺，而是在完成所述栅介质层20及所述栅极区域30之后，对所述氧化物填充层通过刻蚀工艺在所述第一源极区域上形成所述第一通孔110位置，在所述漏极区域上形成所述第二通孔120位置，在所述两个通孔位置中，对所述第一源极区域50及所述漏极区域60的所述衬底10表面的进行金属化工艺，以使得在两个通孔位置中，及在所述第一源极区域50及所述漏极区域60的部分表面形成一硅化物层70，然后对所述第一通孔110及第二通孔120的通孔进行材料填充。
请参见图11，图11为本发明一基于平面CMOS工艺兼容的隧穿晶体管的制备流程图。可以理解的，本实施例中包含部分步骤也可以省略，其他步骤也可以根据增加。可以理解的，在其他实施方式中，以下多个步骤可合并成一个步骤，或者一个步骤可拆分成多个步骤，步骤之间的顺序可以根据需要进行调整。所述隧穿晶体管的制备流程包括以下步骤。本实施例以N型隧穿晶体管为例进行一一介绍。
本实施方式以CMOS器件与N-TFET的集成为例，对基于平面CMOS工艺兼容的隧穿晶体管的制备进行详细的说明，而CMOS器件与P-TFET的集成，只需在CMOS器件与N-TFET的集成工艺的基础上，对掺杂类型及注入阻挡层进行 修改即可。
步骤S201，提供一衬底，所述衬底为具有浅槽隔离工艺结构的掺杂衬底，如图12所示。在本实施方式中，所述衬底可以为绝缘衬底上的硅(silicon on Insulator，SOI)衬底。在其他实施方式中，所述衬底也可以为硅(Si)、锗(Ge)或者锗硅、镓砷等IV族、或III-V族、或者IV-IV族的二元或三元、化合物或者绝缘衬底上的锗中的任意一种。
在本实施方式中，N-MOSFET区域，所述衬底掺杂类型为N型离子掺杂，或进行N型阱制作，P-MOSFET区域，所述衬底掺杂类型为P型离子掺杂，或进行P型阱制作，本实施方式中，所述隧穿晶体管以N-TFET为例进行说明，N-TFET区域，所述衬底掺杂类型为N型离子掺杂，或进行N型阱制作，在其他实施方式中，若所述隧穿晶体管为P-TFET，所述衬底掺杂类型为P型离子掺杂，或进行P型阱制作，其中，所述P型离子包括硼(B)离子或铟(In)离子中的至少一种；所述N型离子包括磷(P)离子、砷(As)离子或锑(Sb)离子中的至少一种。
步骤S202，在所述衬底上沉积假栅叠层及CMOS区域减薄。如图13所示，在所述衬底依次沉积一氧化层(Oxide)、多晶硅(poly)、氧化层(Oxide)多晶硅(poly)以及氧化物-氮化物–氧化物材料(Oxide-Nitride-Oxide，ONO)，在TFET器件上设置一硬掩膜，然后通过光刻技术实现CMOS区域减薄。
步骤S203，假栅的形成。如图14所示，在N-MOSFET、P-MOSFET以及N-TFET上分别设置一硬掩膜，通过光刻技术进行假栅刻蚀，以形成假栅，从而定义了N-MOSFET、P-MOSFET及N-TFET的栅极区域。
步骤S204，侧墙的形成。如图15所示，去除N-MOSFET、P-MOSFET以及N-TFET上余下的硬掩膜，利用低压化学气相沉积(Low pressure chemical vapor deposition，LPCVD)技术，在所述衬底、所述假栅区域侧边以及所述假栅区域顶部顶部各项同性沉积一侧墙材料，以形成一侧墙层，在本实施方式中，所述侧墙材料为氮化硅，当然，在另一实施方式中，所述侧墙的材料也可为硅氧化物，低K电介质或者其他绝缘材料的一种或多种的组合。利用各向异性干法刻蚀(RIE)所述侧墙层，在所述假栅区域的侧边留下一些残余物，作为 N-MOSFET、P-MOSFET以及N-TFET器件的侧墙。本发明实施例中，所述侧墙具有保护栅极区域、源漏极区域，调整源漏掺杂区域与栅极区域的距离，降低栅极区域与源漏接触孔电容等作用。
步骤S205，所述N-MOSFET离子注入及所述N-TFET漏极区域的形成。如图16所示，对P-MOSFET及N-TFET的第一源极区域通过设置阻挡层进行阻挡，对所述N-MOSFET源极区域、所述N-MOSFET漏极区域及N-TFET漏极区域进行N型离子注入，以形成所述N-MOSFET源极区域、所述N-MOSFET漏极区域以及所述N-TFET漏极区域。
在本实施方式中，将所述N-TFET的第一源极区域进行光刻阻挡，所述N-TFET漏极区域进行N型离子注入，在另一实施方式中，若所述TFET为P型隧穿晶体管时，将所述P-TFET的漏极区域进行光刻阻挡，所述P-TFET的第一源极区域进行N型离子注入。
步骤S206，所述P-MOSFET离子注入及所述N-TFET第一源极区域的形成。如图17所示，对N-MOSFET及N-TFET的漏极区域通过设置一阻挡层进行阻挡，对所述P-MOSFET源极区域、所述P-MOSFET漏极区域及所述N-TFET的第一源极区域进行P型离子注入，以形成所述P-MOSFET源极区域、所述P-MOSFET漏极区域以及所述N-TFET第一源极区域。
在本实施方式中，将所述N-TFET的漏极区域进行光刻阻挡，所述N-TFET第一区域进行P型离子注入，在另一实施方式中，若所述TFET为P型隧穿晶体管时，将所述P-TFET的第一源极区域进行光刻阻挡，所述P-TFET漏极区域进行P型离子注入。
在本实施方式中，在形成所述N-MOSFET源极区域、所述N-MOSFET漏极区域、所述N-TFET漏极区域、所述P-MOSFET源极区域、所述P-MOSFET漏极区域以及所述N-TFET第一源极区域后，进行快速退火工艺，从而激活所述N-MOSFET源漏区域、所述P-MOSFET源漏区域、所述N-TFET第一源极区域及漏极区域的离子。
在本实施方式中，在形成所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域后，去除余下的注入阻挡层， 进行所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域金属化工艺，以使得在所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域的部分表面形成一硅化物层(如图18所示)，以便于后续生成源极及漏极通过通孔能与所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域进行连接。
步骤S207，氧化物的填充及CMP工艺。如图17所示，在所述衬底、所述N-MOSFET、所述P-MOSFET以及所述N-TFET假栅周围进行氧化物或低K材料填充，对所述氧化物或低K材料进行化学机械研磨(CMP)或低温热氧化+旋涂玻璃(LTO+SOG)平坦化工艺，暴露出N-TFET上端的Poly层，CMP工艺的目的为对总的氧化物填充层厚度进行控制。
步骤S208，所述N-TFET第二源极区域及晕环层的形成，使得所述N-TFET第二源极区域与所述N-TFET漏极区域之间形成沟道。如图19所示，利用湿法腐蚀去除N-TFET上暴露出的Poly层及下方Oxide、Poly、Oxide，然后以所述侧墙为注入阻挡层，进行大倾角注入离子以形成N-TFET的第二源极区域及晕环层，其中，大倾角注入方向为所述第一源极区域方向，所述大倾角的范围为30°～45°，所述大倾角注入离子具体分为三步骤：1)与所述N-TFET第一源极区域掺杂类型相同的较大能量的超陡倒退掺杂源(Super-Steep Retrograde Source，简称SSRS)注入，以形成所述N-TFET第二源极区域；2)大剂量的C、Ge注入，使得所述N-TFET沟道非晶化，从而使后续注入结深减小，增加所述N-TFET晕环层与所述N-TFET第二源极区域之间的隧穿电场，进而增大隧穿电流；3)与所述漏极区域掺杂类型相同的超低能的pocket注入，以形成所述晕环层。
在本实施方式中，在形成所述N-TFET第二源极区域及所述晕环层后，进行快速退火工艺，从而激活所述N-TFET第二源极区域及所述晕环层的离子。
在本实施方式中，所述N-TFET第二源极区域进行P型离子重掺杂，所述晕环层进行N型离子重掺杂；在另一实施方式中，若所述隧穿晶体管为P型隧穿晶体管时，所述第二源极区域进行N型离子重掺杂，所述晕环层进行P型离子重掺杂；所述P型离子包括硼离子、镓离子或铟离子中的至少一种；所述N型 离子包括磷离子或砷离子中的至少一种。
在本实施方式中，大倾角注入的目的是形成图19中所示的注入阴影区，使所述晕环层中靠近所述漏端区域能自对准的不受注入的影响，这样达到即固定注入阴影区宽度(如图19所示)，又同时能保证所述第二源极区域与所述晕环层能与所述栅极区域自对准的进行掺杂。在本实施方式中，可以通过调节步骤S207中的平坦化高度及大倾角离子注入角度来调节注入阴影区在所述沟道中投射距离的大小，从而调节所述沟道中非掺杂区域的大小。
步骤S209，N-TFET的栅介质层及栅极区域的形成。如图20所示，沉积一栅介质层及金属栅材料，通过CMP工艺对填充后的金属栅进行平坦化，以形成所述N-TFET的栅介质层及栅极区域。
步骤S210，N-MOSFET及P-MOSFET栅极区域的形成。如图21所示，在N-TFET区域沉积一层氧化物，以实现保护N-TFET在后续沉积N-MOSFET及P-MOSFET金属栅极材料不受影响。沉积一CMOS属栅材料，过CMP工艺对填充后的金属栅进行平坦化，以形成所述N-MOSFET及P-MOSFET的栅极区域。
在本实施方式中，关于N-TFET器件，由于栅极区域层叠设置在所述栅介质层及所述第二源极区域上，当所述栅极区域加载电信号时，所述栅极区域加载的电信号的电场方向为竖直方向。由此可见，所述栅极区域加载的电信号的电场方向与电子的隧穿方向一致，即为线隧穿机制。当N-TFET隧穿晶体管发生隧穿时，在所述第二源极区域处发生线隧穿，从而提高了隧穿效率，进而提高了隧穿晶体管的开态电流。
另外，大剂量的Ge在经过退火后形成锗硅材料，调整Ge注入的能量，在N型隧穿晶体管中，使所述锗硅材料位于所述晕环层下方的第二源极区域，减小所述隧穿晶体管的源端材料禁带宽度，进一步提高整个N-TFET器件的开态电流，在P型隧穿晶体管中，使所述锗硅材料位于所述晕环层，减小所述隧穿晶体管的晕环层材料禁带宽度，进一步提高整个N-TFET器件的开态电流。
步骤S211，进行N-MOSFET、P-MOSFET以及N-TFET通孔以及标准CMOS工艺后端工艺制作，目的是为了形成一个完整的CMOS晶体管及隧穿晶体管。
进行N-MOSFET、P-MOSFET以及N-TFET通孔制作可以由以下的方式形成，请参阅图22，对所述氧化物填充层通过刻蚀工艺在所述N-MOSFET、所述P-MOSFET以及所述N-TFET第一源极区域上形成一通孔，在所述N-MOSFET、所述P-MOSFET以及所述N-TFET漏极区域上形成另一通孔，然后对形成的通孔进行金属材料沉积，以使得所述N-MOSFET、所述P-MOSFET以及所述N-TFET的源漏极穿过通孔源极区域及漏极区域连接。
在另一实施方式中，所述进行N-MOSFET、P-MOSFET以及N-TFET通孔制作也可以由以下方式形成：在形成所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域后，在形成所述栅介质层及所述栅极区域之前不进行所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域金属化工艺，而是在完成所述栅介质层及所述栅极区域之后，对所述氧化物填充层通过刻蚀工艺在形成所述N-MOSFET源极区域、所述P-MOSFET源极区域以及所述N-TFET第一源极区域上形成所述第一通孔位置，在形成所述N-MOSFET漏极区域、所述P-MOSFET漏极区域以及所述N-TFET漏极区域上形成所述第二通孔120位置，在所述两个通孔位置中，对形成所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域的所述衬底表面的进行金属化工艺，以使得在两个通孔位置中，及在形成所述N-MOSFET源漏区域、所述P-MOSFET源漏区域以及所述N-TFET第一源极区域及漏极区域的部分表面形成一硅化物层，然后对所述第一通孔及第二通孔的通孔进行材料填充。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解；其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (17)

  1. 一种隧穿晶体管，其特征在于，包括：
    衬底、第一源极区域、漏极区域、第二源极区域、沟道、晕环层、栅介质层及栅极区域，所述第一源极区域及所述漏极区域形成于所述衬底之上，所述第二源极区域形成于所述第一源极区域及所述漏极区域之间，使得所述第二源极区域与所述漏极区域之间形成沟道，所述晕环层形成于所述第二源极区域的部分表面之上，所述栅介质层及所述栅极区域依次形成于所述晕环层之上。
  2. 根据权利要求1所述的隧穿晶体管，其特征在于，所述隧穿晶体管还包括：
    形成于所述栅极区域两端的侧墙，且所述侧墙高度不低于20nm。
  3. 根据权利要求1至2任一项所述的隧穿晶体管，其特征在于，所述隧穿晶体管还包括：
    形成于所述第一源极区域及所述漏极区域之上的硅化物层；
    形成于所述硅化物层之上的第一通孔和第二通孔。
  4. 根据权利要求1至3任一项所述的隧穿晶体管，其特征在于，所述隧穿晶体管为N型隧穿晶体管，所述源区域进行P型离子重掺杂，所述漏极区域及所述晕环层进行N型离子重掺杂。
  5. 根据权利要求1～3任一项所述的隧穿晶体管，其特征在于，所述隧穿晶体管为P型隧穿晶体管，所述源区域进行N型离子重掺杂，所述漏极区域及所述晕环层进行P型离子重掺杂。
  6. 根据权利要求4或5任一项所述的隧穿晶体管，其特征在于，所述P型离子包括硼离子、二氟化硼离子或铟离子中的至少一种，所述N型离子包括磷离子、砷离子或锑离子中的至少一种。
  7. 一种隧穿晶体管的制备方法，其特征在于，包括：
    提供衬底；
    在所述衬底的一表面上形成第一源极区域及漏极区域；
    在所述第一源极区域及所述漏极区域之间形成第二源极区域，使得所述第二源极区域与所述漏极区域之间形成沟道；
    在所述第二源极区域的部分表面形成晕环层；
    在所述晕环层之上依次形成栅介质层及栅极区域。
  8. 根据权利要求7所述的隧穿晶体管的制备方法，其特征在于，所述隧穿晶体管的制备方法还包括：
    在所述第一源极区域及所述漏极区域之上形成硅化物层；
    在所述硅化物层之上形成第一通孔和第二通孔。
  9. 根据权利要求7所述的隧穿晶体管的制备方法，其特征在于，所述在所述衬底的一表面之上形成第一源极区域和漏极区域，包括：
    在所述衬底之上形成一假栅，在所述假栅的两端形成所述侧墙；
    在假栅的一侧提供第一注入阻挡层，以所述侧墙及所述第一注入阻挡层为掩膜进行离子注入形成所述第一源极区域；
    去除余下的所述第一注入阻挡层，在所述假栅的另一侧提供第二注入阻挡层，以所述侧墙及所述第二硬掩膜层为掩膜刻蚀所述衬底，进行离子注入形成所述漏极区域。
  10. 根据权利要求9所述的隧穿晶体管的制备方法，其特征在于，所述在所述第一源极区域及所述漏极区域之间形成第二源极区域，包括：
    在所述假栅的两端形成氧化物填充层；
    去除所述假栅以形成第一区域；
    以所述侧墙为注入阻挡层，对所述第一区域进行倾角离子注入形成所述第二源极区域。
  11. 根据权利要求10所述的隧穿晶体管的制备方法，其特征在于，所述第二源极区域的部分表面形成晕环层，包括：
    在所述第二源极区域上进行倾角离子注入形成所述晕环层。
  12. 根据权利要求11所述的隧穿晶体管的制备方法，其特征在于，所述在所述第二源极区域上进行倾角离子注入形成所述晕环层，包括：
    在所述第二源极区域上进行C、Ge离子注入，以及进行与所述漏极区域注入离子类型相同的倾角离子注入，以形成所述晕环层。
  13. 根据权利要求10～12任一项所述的隧穿晶体管的制备方法，其特征在 于，所述倾角的范围为30°～45°。
  14. 根据权利要求11或12任一项所述的隧穿晶体管的制备方法，其特征在于，所述在所述晕环层之上依次形成栅介质层及栅极，包括：
    在所述晕环层远离所述第二源极区域的表面上依次沉积栅介质层材料及栅极材料，以形成所述栅介质层及所述栅极区域。
  15. 根据权利要求7～14任一项所述的隧穿晶体管的制备方法，其特征在于，所述隧穿晶体管为N型隧穿晶体管，所述源区域进行P型离子重掺杂，所述漏极区域及所述晕环层进行N型离子重掺杂。
  16. 根据权利要求7～14任一项所述的隧穿晶体管的制备方法，其特征在于，所述隧穿晶体管为P型隧穿晶体管，所述源区域进行N型离子重掺杂，所述漏极区域及所述晕环层进行P型离子重掺杂。
  17. 根据权利要求15或16任一项所述的隧穿晶体管的制备方法，其特征在于，其特征在于，所述P型离子包括硼离子、二氟化硼离子或铟离子中的至少一种，所述N型离子包括磷离子、砷离子或锑离子中的至少一种。
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