CN108074968B - 具有自对准栅极的穿隧finfet - Google Patents

具有自对准栅极的穿隧finfet Download PDF

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CN108074968B
CN108074968B CN201710831733.3A CN201710831733A CN108074968B CN 108074968 B CN108074968 B CN 108074968B CN 201710831733 A CN201710831733 A CN 201710831733A CN 108074968 B CN108074968 B CN 108074968B
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dielectric
tunneling
drift
source
region
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CN108074968A (zh
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E·J·诺瓦克
R·阿斯拉
M·V·R·M·科塔
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Abstract

本发明涉及具有自对准栅极的穿隧FINFET，其用于穿隧场效应晶体管(TFET)的结构及方法。该TFET包括栅极电极、具有第一导电类型的源极区、具有与该第一导电类型相反的第二导电类型的漏极区、以及使该栅极电极与该源极区及该漏极区分开的介电层。该介电层在该源极区与该漏极区之间提供沟道区。该沟道区包括介于该源极区与该栅极电极之间的较薄穿隧介电质、及介于该栅极电极与该漏极区之间的较厚漂移介电质。

Description

具有自对准栅极的穿隧FINFET
技术领域
本发明关于半导体装置，并且更尤指用于形成穿隧场效应晶体管(TFET)的结构及方法。
背景技术
纳米级装置显现更大的短沟道效应而导致漏电流增加。以硅形成有沟道及源极/漏极区的TFET典型会有低导通电流的问题，这是一种与穿隧阻障物的大电阻有关的缺点。在TFET中，导通电流与断开电流都是通过半导体材料自价带至导带的带间穿隧来判定。控制自源极穿过带间穿隧至沟道的电流注射会导致泄漏降低。穿隧电流是通过穿隧阻障物高度、宽度及穿隧面积来限制。已提出各种用以增强导通电流的方法，诸如使用小能隙原料以降低穿隧阻障物高度与宽度，还有在窄能隙沟道材料上施作穿隧FET。使用窄能隙材料虽然使导通电流增强，但仍具有缺点。
还没有人揭示用于制造具有高导通电流(Ion)及低漏电流(Ioff)的TFET装置的程序流程。
发明内容
需要一种TFET装置及用于此TFET装置的制造程序以在源极区实现带间穿隧。这导致接面边缘处的场域非常高，也导致自源极至漏极产生寄生栅极诱发型漏极漏电(GIDL)流。这导致漏电层衰减。根据本文中的结构及方法，两部分栅极介电质形成有对源极自对准而实现低穿隧电压的薄部分、及对漏极自对准而导致低GIDL电流的厚部分。
换句话说，较薄介电质是设于源极区与栅极之间以通过穿隧产生沟道载子。更厚的介电质是就漂移区而设，但薄区域的对准容许源极载子有效率地抵达漂移区。
根据本文中的例示性穿隧场效应晶体管(TFET)，该TFET包括栅极电极、具有第一导电类型的源极区、具有与该第一导电类型相反的第二导电类型的漏极区、以及使该栅极电极与该源极区及漏极区分开的介电层。该介电层在该源极区与该漏极区之间提供沟道区。该沟道区包括介于该源极区与该栅极电极之间的穿隧介电质、及介于该栅极电极与该漏极区之间的漂移介电质。该穿隧介电质比该漂移介电质更薄。
根据本文中的另一例示性穿隧场效应晶体管(TFET)，该TFET包括栅极电极、源极区、漏极区、以及使该栅极电极与该源极区及漏极区分开的介电层，该源极区与漏极区呈相反导电类型。该介电层是由两个部分所制成。第一部分包括穿隧栅极介电质，而第二部分包括漂移介电质。该穿隧介电质介于该源极区与该栅极电极之间，相比于该漂移介电质较薄，而该漂移介电质介于该栅极电极与该漏极区之间，相比于该穿隧介电质较厚。
根据制造穿隧场效应晶体管(TFET)的例示性方法，在衬底上方形成漂移层。掺杂该衬底的第一部分以在该衬底中形成源极区。在该源极区及漂移层上方形成穿隧介电层。在该穿隧介电质上方形成栅极电极。向下至该衬底蚀刻掉该穿隧介电层及栅极电极的一部分。掺杂该衬底的第二部分以在该衬底中形成漏极区。
附图说明
前述及其它例示性目的、态样及优点将会参照图式经由本文中例示性具体实施例的以下详细说明而更加让人了解，此等图式不必然按照比例绘制，其中：
图1至10是根据本文中的结构及方法制作TFET装置时的半导体结构的截面图的示意图；
图11是根据本文中的结构及方法的TFET装置的平面图；以及
图12是绘示本文具体实施例的流程图。
具体实施方式
如上述，以硅形成有沟道及源极/漏极区的TFET典型会有低导通电流的问题，这是一种与穿隧阻障物的大电阻有关的缺点。在TFET中，导通电流与断开电流都是通过半导体材料自价带至导带的带间穿隧来判定。控制自源极穿过带间穿隧至沟道的电流注射会导致泄漏降低。穿隧电流是受到穿隧阻障物高度、宽度及穿隧面积来限制。
鉴于前述，本文中所揭示的是TFET装置，其包括栅极电极、具有第一导电类型的源极区、具有与该第一导电类型相反的第二导电类型的漏极区、以及使该栅极电极与该源极区及该漏极区分开的介电层。该介电层在该源极区与该漏极区之间提供沟道区。该沟道区包括介于该源极区与该栅极电极之间的较薄穿隧介电质、及介于该栅极电极与该漏极区之间的较厚漂移介电质。具体而言，两部分栅极介电质形成有对源极自对准而实现低穿隧电压的薄部分、及对漏极自对准而实现低电流的厚部分，该低电流产生自栅极诱发型漏极漏电(GIDL)流。栅极诱发型漏极漏电是一种在FET中因漏极接面中的大场效应所导致的漏电机制。
为达本文的目的，“半导体”是可包括经布植杂质的材料或结构，此杂质基于电子与空穴载子浓度，容许此材料有时成为导体，而有时成为绝缘体。“布植程序”于本文中使用时，可采用任何适当形式(无论是目前已知或未来才开发的形式)，并且举例而言，可包含离子布植等。
图1至10根据本文中的装置，绘示用于形成穿隧场效应晶体管(TFET)的处理步骤。在图1中，提供衬底101。衬底101可以是任何现有的半导体衬底，举例如主体硅衬底或硅绝缘体(SOI)晶片的主动半导体材料层。
在图2中，于衬底101上形成并且图型化漂移介电质202。漂移介电质202可由适当的介电材料所构成，诸如SiO2。本文中所述的介电质举例而言，可通过使四乙基正硅酸盐(TEOS)或硅烷与O2或活化的O2(即O3或O-)起反应，透过等离子体沉积SiO2或SiO2为基础的材料所形成。或者，本文中的介电质可由许多候选的高介电常数(高k)材料中任一种形成，包括但不局限于氮化硅、氮氧化硅、SiO2与Si3N4的栅极介电质堆叠、及与氧化钽相似的金属氧化物。本文中介电质的厚度可因所需要的装置效能而异。在一些具体实施例中，漂移介电质202可具有介于约3nm与约50nm之间的厚度。
在图3中，掺杂源极区303以获得所欲导电性类型。举例而言，根据本文中的结构及方法，源极区303可掺有诸如硼的p型杂质物种，使其呈现空穴为多数载子并且主导成分半导体材料导电性的p型。或者，源极区303可掺有诸如砷的n型杂质物种，使其呈现电子为多数载子并且主导成分半导体材料导电性的n型。在掺杂源极区303时，可将漂移介电质202当作掩模使用，或可将该漂移介电质上面的牺牲膜当作掩模使用，诸如图2中的204。牺牲膜204若有用到，可以是在光刻期间保护漂移介电质202的Si3N4或其它膜件。或者，源极区303可通过使用材料移除程序(例如：等离子体蚀刻等)所形成，用以移除衬底101的一区段的未受保护部分，并且可进行适度传导多晶的选择性外延生长程序以形成源极区303。
在图4中，于源极区303及漂移介电质202上方形成穿隧介电质404。若有运用牺牲膜204，则会在形成穿隧介电质404前先将其移除。穿隧介电质404可由适当的介电材料所构成，诸如SiO2或HfO等。穿隧介电质404在源极区303上方形成有薄部分，其实现低穿隧电压。穿隧介电质404的薄部分可具有介于约0.5nm与约1nm的厚度。如下文所述，源极区303是对栅极的穿隧侧自对准。
在图5中，在该穿隧介电质404上方形成栅极电极505。可在穿隧介电质404上沉积栅极电极505，并且视需要地将其平坦化。栅极电极505是导体。本文中所述的导体可由诸如多结晶硅(多晶硅)、非晶硅、非晶硅与多晶硅的组合、及多晶硅-锗等任何导电材料所构成，因存在合适的掺质而具有导电性。或者，本文中的导体可以是一或多种金属，诸如TiN、钨、铪、钽、钼、钛、镍、铝、或铜等、或此类金属的金属硅化物及合金，并且可使用物理气相沉积、化学气相沉积、或任何其它所属技术领域已知的技术来沉积。
接着可穿过穿隧介电质404及漂移介电质202将栅极电极505图型化及蚀刻以使衬底101的一部分曝露，如图6所示。可使用任何适当的材料移除程序。
当图型化本文中的任何材料时，待图型化的材料可按照已知方式来生长或沉积，而图型化层(例如：有机光阻)可在此材料上方形成。图型化层(阻剂)可曝露至光曝照图型中所提供的光辐射(例如：图型化曝照、激光曝照等)的某图型，然后阻剂使用化学剂来显影。此程序改变阻剂待曝露至光的部分的物理特性。接着，可将阻剂的一部分清洗掉，留下阻剂要保护待图型化材料的其它部分。接着进行材料移除程序(例如：等离子体蚀刻等)以移除待图型化材料未受保护的部分。随后移除阻剂以留下根据光曝照图型进行图型化的下层材料。
在图7中，于栅极电极505的周界处形成间隔物707。为达本文的目的，“间隔物”是所属领域技术人员众所周知的结构，而且在形成方面大体上是先沉积或生长保形绝缘层，然后再进行定向蚀刻程序(各向异性)，以比从垂直表面将材料移除更大的速率将材料从水平表面蚀刻掉，藉此沿着结构的垂直侧壁留下绝缘材料。此留在垂直侧壁上的材料称为间隔物。又为达本文的目的，“绝缘体”是一相对用语，意为容许流动的电流比“导体”实质更小(<95％)的材料或结构。本文中所述的介电质(绝缘体)举例而言，可自干氧环境或蒸汽生长，并且接着予以图型化。或者，本文中的介电质可由许多候选的高介电常数(高k)材料中任一种形成，包括但不局限于氮化硅、氮氧化硅、SiO2与Si3N4的介电质堆叠、及与氧化钽相似的金属氧化物。本文中介电质的厚度可因所需要的装置效能而异。
在图8中，掺杂漏极区808以获得与源极区303的导电性类型相反的所欲导电性类型。举例而言，如以上所述，源极区303可掺有诸如硼的p型杂质物种，使其呈现p型。因此，漏极区808可掺有诸如砷的n型杂质物种，使其呈现n型。漏极区808可通过使用材料移除程序(例如：等离子体蚀刻等)所形成，于其中铺设掩模于该结构以便移除衬底101的一区段的未受保护部分，并且可进行适度传导多晶的选择性外延生长程序以形成漏极区808。漏极区808对栅极的漂移侧自对准。所属领域技术人员理解的是，可在掺杂漏极区808时，通过对光阻进行现有的图型化或其它众所周知的手段，包覆晶片的源极区303及其它非漏极区。
掩模可由任何合适的材料所构成，无论该材料属于目前已知或未来才开发，诸如金属或有机或无机(Si3N4、SiC、SiO2C(钻石))硬罩，其比衬底、及结构剩余部分中使用的绝缘体材料具有更大的蚀刻电阻。
在图9中，在结构上方形成层间介电质909，诸如SiO2。分别建立连至源极、漏极及栅极的电接触104、106、108，如图10所示。
使用在源极周围具有沟道的鳍片架构会导致大穿隧面积。再者，鳍式穿隧FET会使导通电流(Ion)增加，其亦与FinFET CMOS流动相容。为了抑制GIDL电流而就漂移介电质202提供更厚的介电质，但源极区303上方的穿隧介电质404的薄区域的对准容许源极载子以有效率的方式抵达漂移区。换句话说，穿隧介电质404及漂移介电质202在源极区303与漏极区808之间建立沟道区111。举例而言，当栅极电极505上的偏压足以确保本质沟道区的导带与P型源极区303的价带对准时，出现穿隧现象(亦即，电子自P型源极区的价带穿隧到本质沟道区的导带内)，并且电流朝N型漏极区808流动。
图11是根据本文中的结构及方法的穿隧FinFET的截面的平面图。正如所属领域技术人员已知，在鳍片上形成源极区303与漏极区808。如以上所述，形成漂移介电质202作为介于源极区303与漏极区808之间的较厚沉积物。在源极区303与漂移介电质202上方与周围形成穿隧介电质404，并且在穿隧介电质404上方及周围形成栅极电极505。可于栅极电极505的周界处形成间隔物707。根据本文中的结构及方法，在图11中如113所示，源极是对穿隧栅极自对准。另外，在图11中如118所示，漏极是对漂移栅极自对准。
如下文所述，硅晶片可按照一系列步骤来制造，各阶段在晶片上置放材料图型；按照这种方式，敷设全部由不同材料所制成的晶体管、接点等。为使最终装置正确作用，这些不同图型必须正确对准，例如，接点、线路及晶体管全都必须排列整齐。“自对准”于本文中使用时，暗示着接点形成不需要光刻图型化程序。根据本文中的结构及方法，两部分栅极介电质形成有对源极自对准而实现低穿隧电压的薄部分、及对漏极自对准而导致低GIDL电流的厚部分。这会对漂移区产生高密度载子并且注入源极电流至该漂移区，但不会因此产生寄生漏电流。
图12根据本文中的结构及方法，绘示制造穿隧场效应晶体管(TFET)的例示性方法用的逻辑流程图。于步骤1205，提供衬底。该衬底可以是任何现有的半导体衬底，举例如主体硅衬底或硅绝缘体(SOI)晶片的主动半导体材料层。于步骤1210，在该衬底上形成并且图型化漂移层。该漂移介电质可由适当的介电材料所构成，诸如SiO2。于步骤1215，掺杂该衬底的第一部分以在该衬底中形成源极区。根据本文中的结构及方法，该源极区可掺有诸如硼的p型杂质物种，使其呈现空穴为多数载子并且主导成分半导体材料导电性的p型。或者，该源极区可掺有诸如砷的n型杂质物种，使其呈现电子为多数载子并且主导成分半导体材料导电性的n型。于步骤1220，在该源极区及漂移层上方形成穿隧介电层。该穿隧介电质可由适当的介电材料所构成，诸如SiO2或HfO等。该穿隧介电质在该源极区上方形成有薄部分，其实现低穿隧电压。该源极区对该栅极的穿隧侧自对准。于步骤1225，在该穿隧介电质上方形成栅极电极。该栅极电极可由诸如多结晶硅(多晶硅)、非晶硅、非晶硅与多晶硅的组合、及多晶硅-锗等任何导电材料所构成，因存在合适的掺质而具有导电性。于步骤1230，向下至该衬底蚀刻掉该穿隧介电层及栅极电极的一部分。可使用任何适当的材料移除程序。于步骤1235，掺杂该衬底的第二部分以在该衬底中形成漏极区。该漏极区与该源极区具有相反的导电性。于步骤1240，形成连至各该源极、漏极及栅极的电接触。该电接触可以是一或多种金属诸如钨、铪、钽、钼、钛、镍、铝、或铜等、或此类金属的金属硅化物及合金。
凭借其独特且新颖的特征，本文中的结构及方法教示例示性穿隧场效应晶体管(TFET)。该TFET包括栅极电极、源极区以及漏极区。该源极区与漏极区呈相反导电性类型。介电层使该栅极电极与该源极区及漏极区分开。该介电层在该源极区与该漏极区之间提供沟道。该沟道是由穿隧栅极介电质与漂移介电质所制成。该穿隧栅极介电质在该源极区与该栅极电极之间较薄，而该漂移介电质在该栅极电极与该漏极区之间较厚。
本方法如以上所述，可用于制造集成电路晶片。产生的集成电路芯片可由制造商以空白晶片形式(也就是说，作为具有多个未封装芯片的单一晶片)、当作裸晶粒、或以封装形式来配送。在已封装的例子中，芯片嵌装于单一芯片封装(诸如塑胶载体，具有黏贴至主机板或其它更高阶载体的引线)中，或多芯片封装(诸如具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。在任一例子中，该芯片接着与其它芯片、离散电路元件、及/或其它信号处理装置整合成下列任一者的一部分：(a)诸如主机板的中间产品，或(b)最终产品。最终产品可以是包括集成电路芯片的任何产品，范围涵盖玩具及其它低阶应用至具有显示器、键盘或其它输入装置、及中央处理器的进阶计算机产品。
本发明的态样在本文中是根据本文中的具体实施例，参照方法、设备(系统)及计算机程序产品的流程图说明及/或方块图来描述。将会理解的是，流程图说明及/或二维方块图的各功能块、以及流程图说明及/或方块图中的功能块组合可通过电脑程序指令来实施。可提供这些电脑程序指令至通用型计算机、特殊用途计算机、或其它可编程数据处理器具的处理器以生产机器，使得经由计算机或其它可编程数据处理器具的处理器执行的指令，建立用于实施流程图及/或方块图一或多个功能块中所指定功能/动作的手段。
计算机程序指令亦可载入到计算机、其它可编程数据处理器具、或其它装置，而在计算机、其它可编程器具或其它装置上进行一连串操作步骤以产生计算机实施程序，使得计算机或其它可编程器具上执行的指令提供用于实施流程图及/或方块图一或多个功能块中所指定功能/动作的程序。
应了解的是，本文所用术语的目的仅在于说明特殊具体实施例并且意图不在于限制本揭示。如本文中所用，单数形式“一”、“一种”、“一个”、以及“该”的用意在于同时包括复数形式，上下文另有所指除外。将进一步了解的是，“包含”(及/或其变形)等词于本说明书中使用时，指明所述特征、整体、步骤、操作、元件及/或组件的存在，但并未排除一或多个其它特征、整体、步骤、操作、元件、组件及/或其群组的存在或新增。
另外，了解本文中所使用诸如“右”、“左”、“垂直”、“水平”、“顶端”、“底端”、“上”、“下”、“底下”、“下面”、“下层”、“上方“、“上层”、“平行”、“垂直”等用语在于说明此等用语在图式中取向及绘示时的相对位置(除非另有所指)。诸如“触及”、“上”、“直接接触”、“毗连”、“直接相邻于”等用语意为至少一个元件实体接触另一元件(此等所述元件之间没有用其它元件来分隔)。
下面权利要求书中所有手段或步骤加上功能元件的对应结构、材料、动作及均等者用意在于包括结合如具体主张的其它主张专利权的元件进行任何结构、材料或动作。本发明的各项具体实施例的描述已为了说明目的而介绍，但用意不在于穷举或受限于所揭示的具体实施例。许多修改及变例对于所属领域技术人员将会显而易知，但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让所属领域技术人员能够理解本文中所揭示的具体实施例而选择。
以上所揭示的是具有自对准栅极的穿隧FinFET(或TFET)，其容许接面边缘处有高场域(high fields)，也容许低栅极诱发型漏极漏电(GIDL)流。具体而言，所揭示的TFET可在源极穿隧区与栅极之间合并较薄介电质，以通过穿隧来产生沟道载子，并且就漂移区产生更厚的介电质，其中薄区域的对准容许源极载子有效率地抵达漂移区。该TFET装置包括栅极电极、具有第一导电类型的源极区、具有与该第一导电类型相反的第二导电类型的漏极区、以及使该栅极电极与该源极区及该漏极区分开的介电层。该介电层在该源极区与该漏极区之间提供沟道区。该沟道区包括在该源极区与该栅极电极之间具有较薄介电质的穿隧区、及介于该栅极电极与该漏极区之间的较厚漂移介电质。具体而言，两部分栅极介电质形成有对源极自对准而实现低穿隧电压的薄部分、及对漏极自对准而实现低电流的厚部分，该低电流产生自栅极诱发型漏极漏电(GIDL)。

Claims (17)

1.一种穿隧场效应晶体管，包含：
栅极电极；
源极区，具有第一导电类型；
漏极区，具有与该第一导电类型相反的第二导电类型；
漂移介电质，在该源极区与该漏极区之间；
穿隧介电质，在该源极区与该栅极电极之间，其中，该穿隧介电质的一部分在该漂移介电质上方；
其中，该漂移介电质和该穿隧介电质在该源极区与该漏极区之间提供沟道区，该穿隧介电质比该漂移介电质更薄，
其中，以该漂移介电质为掩膜形成该源极区，该源极区位于该穿隧场效应晶体管的没有该漂移介电质且具有该穿隧介电质的一侧，且该源极区延伸至该穿隧介电质与该漂移介电质之间的界面，
其中，该穿隧介电质包含第一水平段、位于该第一水平段上方的第二水平段、以及连接该第一水平段与该第二水平段的垂直段，
其中，该源极区的一部分位于该垂直段正下方。
2.如权利要求1所述的穿隧场效应晶体管，该漏极区与该漂移介电质自对准。
3.如权利要求1所述的穿隧场效应晶体管，更包含：
衬底，该源极区与漏极区是在该衬底中形成。
4.如权利要求1所述的穿隧场效应晶体管，其中，该穿隧介电质具有比约1nm更小的厚度。
5.如权利要求1所述的穿隧场效应晶体管，其中，该漂移介电质具有介于3nm与50nm之间的厚度。
6.一种穿隧场效应晶体管，包含：
栅极电极；
源极区；
漏极区，该源极区与漏极区呈相反导电类型；以及
介电层，使该栅极电极与该源极区及漏极区分开，该介电层包含在该源极区与该栅极电极之间的穿隧介电质及在该源极区与该漏极区之间的漂移介电质，
其中，该穿隧介电质的一部分在该漂移介电质上方，而该漂移介电质比该穿隧介电质更厚，
其中，以该漂移介电质为掩膜形成该源极区，该源极区位于该穿隧场效应晶体管的没有该漂移介电质且具有该穿隧介电质的一侧，且该源极区延伸至该穿隧介电质与该漂移介电质之间的界面，
其中，该穿隧介电质包含第一水平段、位于该第一水平段上方的第二水平段、以及连接该第一水平段与该第二水平段的垂直段，
其中，该源极区的一部分位于该垂直段正下方。
7.如权利要求6所述的穿隧场效应晶体管，该漏极区与该漂移介电质自对准。
8.如权利要求6所述的穿隧场效应晶体管，更包含：
衬底，该源极区与漏极区是在该衬底中形成。
9.如权利要求6所述的穿隧场效应晶体管，其中，该穿隧介电质具有比约1nm更小的厚度。
10.如权利要求6所述的穿隧场效应晶体管，其中，该漂移介电质具有介于3nm与50nm之间的厚度。
11.如权利要求6所述的穿隧场效应晶体管，更包含：
电接触，连接至各该源极区、漏极区及栅极电极。
12.一种制造穿隧场效应晶体管的方法，该方法包含：
在衬底上方形成漂移介电质；
以该漂移介电质为掩膜，掺杂该衬底的第一部分以在该衬底中形成源极区；
在该源极区及漂移介电质上方形成穿隧介电质；
在该穿隧介电质上方形成栅极电极；
向下至该衬底蚀刻掉该穿隧介电质及栅极电极的一部分；以及
掺杂该衬底的第二部分以在该衬底中形成漏极区，就相反导电类型掺杂该源极区与漏极区，
其中，该源极区位于该穿隧场效应晶体管的没有该漂移介电质且具有该穿隧介电质的一侧，且该源极区延伸至该穿隧介电质与该漂移介电质之间的界面，
其中，该穿隧介电质包含第一水平段、位于该第一水平段上方的第二水平段、以及连接该第一水平段与该第二水平段的垂直段，
其中，该源极区的一部分位于该垂直段正下方。
13.如权利要求12所述的方法，该漂移介电质具有介于3nm与50nm之间的厚度。
14.如权利要求12所述的方法，该穿隧介电质具有比约1nm更小的厚度。
15.如权利要求12所述的方法，更包含：
在向下至该衬底蚀刻掉该穿隧介电质及栅极电极的一部分之后，在该栅极电极的周界上形成间隔物。
16.如权利要求12所述的方法，更包含：
在该源极区、栅极电极及漏极区上方沉积层间介电质。
17.如权利要求12所述的方法，更包含：
形成连接至各该源极区、漏极区及栅极电极的电接触。
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