CN105990239A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN105990239A
CN105990239A CN201510062339.9A CN201510062339A CN105990239A CN 105990239 A CN105990239 A CN 105990239A CN 201510062339 A CN201510062339 A CN 201510062339A CN 105990239 A CN105990239 A CN 105990239A
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fin structure
laying
doped layer
lower half
layer
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CN105990239B (zh
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冯立伟
蔡世鸿
林昭宏
刘鸿辉
洪世芳
郑志祥
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/637,400 priority patent/US9502252B2/en
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Priority to US15/294,797 priority patent/US10068808B2/en
Priority to US16/053,737 priority patent/US10692777B2/en
Priority to US16/872,395 priority patent/US11387148B2/en
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Abstract

本发明优选公开一种半导体元件及其制作方法。该制作方法包括：首先提供一基底，该基底上设有至少一鳍状结构，其中鳍状结构包含一上半部及一下半部，然后形成一掺杂层以及一第一衬垫层于鳍状结构的下半部周围。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，尤其是涉及一种于鳍状结构下半部形成掺杂层及衬垫层的半导体元件及其制作方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(drain induced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的设计仍存在许多瓶颈，进而影响整个元件的漏电流及整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明优选实施例揭露一种制作半导体元件的方法。首先提供一基底，该基底上设有至少一鳍状结构，其中鳍状结构包含一上半部及一下半部，然后形成一掺杂层以及一第一衬垫层于鳍状结构的下半部周围。
本发明另一实施例揭露一种制作半导体元件的方法。首先提供一基底，该基底上定义有一第一区域及一第二区域，然后形成一第一鳍状结构于该第一区域上以及一第二鳍状结构于该第二区域上，其中该第一鳍状结构及该第二鳍状结构各包含一上半部与一下半部。之后形成一第一掺杂层及一第一衬垫层于该第二鳍状结构的该下半部周围，以及形成一第二掺杂层及一第二衬垫层于该第一鳍状结构的该下半部周围。
本发明又一实施例揭露一种半导体元件，其包含一基底、一鳍状结构设于基底上、一掺杂层环绕鳍状结构的下半部以及一衬垫层设于掺杂层上。
附图说明
图1至图4为本发明第一实施例制作一半导体元件的方法示意图；
图5至图10为本发明第二实施例制作一CMOS半导体元件的方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 硬掩模 18 上半部
20 下半部 22 衬垫层
24 掺杂层 26 衬垫层
28 介电层 30 介电层
32 基底 34 PMOS区域(P型金属-氧化物-半导体区域)
36 NMOS区域(N型金属- 38 鳍状结构氧化物-半导体区域)
40 鳍状结构 42 硬掩模
44 上半部 46 下半部
48 衬垫层 50 掺杂层
52 衬垫层 54 掺杂层
56 衬垫层 58 介电层
60 介电层
具体实施方式
请参照图1至图4，图1至图4为本发明第一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。基底12上具有至少一鳍状结构14以及一硬掩模16设于各鳍状结构14上，其中各鳍状结构14具有一上半部18与一下半部20。在本实施例中，鳍状结构14的数量虽以两根为例，但不局限于此。
鳍状结构14的形成方式可以包含先形成一图案化掩模(图未示)，例如前述的硬掩模于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构。除此之外，鳍状结构14的形成方式另也可以是先制作一图案化硬掩模层(图未示)在基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出半导体层，此半导体层即可作为相对应的鳍状结构14。另外，当基底12为硅覆绝缘(SOI)基板时，则可利用图案化掩模来蚀刻基底上的一半导体层，并停止于此半导体层下方的一底氧化层以形成鳍状结构。
然后可选择性利用临场蒸气产生技术(in situ steam generation,ISSG)于鳍状结构14表面形成一衬垫层22，其中衬垫层22优选由氧化硅所构成，且衬垫层22除了覆盖鳍状结构14的上半部18及下半部20之外又同时盖住基底12表面。接着依序形成一掺杂层24以及另一衬垫层26于衬垫层22上并覆盖整个鳍状结构14。在本实施例中，衬垫层26优选由氮化硅所构成，掺杂层24的材料则优选因应所制作晶体管的的型态而不同，例如若所制备的晶体管为NMOS晶体管，则所形成的掺杂层24优选包含硼硅酸盐(borosilicate glass,BSG)等的含有P型掺质的薄膜，反之若所制备的晶体管为PMOS晶体管，则所形成的掺杂层24优选包含磷硅酸盐(phosphosilicate glass,PSG)等的含有N型掺质的薄膜。
然后如图2所示，先形成一保护层，例如一介电层28于衬垫层26上全面性覆盖鳍状结构14，接着进行一回蚀刻制作工艺，去除部分介电层28使剩余的介电层28上表面约略介于鳍状结构14的上半部18及下半部20之间。在本实施例中，介电层28优选为一有机介电层(organic dielectric layer,ODL)所构成，但不局限于此。
如图3所示，接着利用介电层28为蚀刻掩模进行另一蚀刻制作工艺，去除未被介电层28所保护的衬垫层26与掺杂层24，例如原本设于鳍状结构14上半部18周围的衬垫层26及掺杂层24，由此暴露出鳍状结构14的上半部18及硬掩模16。需注意的是，衬垫层26可于蚀刻过程中保护鳍状结构14上半部18使其不致于蚀刻过程受到损害。
随后如图4所示，先完全去除介电层28，然后利用可流动式化学气相沉积(flowable chemical vapor deposition,FCVD)制作工艺形成一由氧化硅所构成的介电层30于鳍状结构14上，并搭配进行一退火制作工艺，将掺杂层24中的掺质趋入鳍状结构14下半部20以及/或基底12内以形成一抗接面击穿(anti-punch-through,APT)层用来避免漏电。需注意的是，由于本实施例优选依据晶体管的型态于鳍状结构14上覆盖由BSG或PSG所构成的掺杂层24，因此利用退火制作工艺所趋入的掺质优选依据掺杂层24以及晶体管的型态而有所不同。举例来说，若所制备的为NMOS晶体管且覆盖于鳍状结构14上的为BSG所构成的掺杂层24，则退火制作工艺优选将硼离子等的P型掺质趋入鳍状结构14下半部20以及/或基底12，反之若制备的为PMOS晶体管且覆盖于鳍状结构14上的为PSG所构成的掺杂层24，则退火制作工艺优选将磷离子等的N型掺质趋入鳍状结构14下半部20以及/或基底12。之后可利用蚀刻以及/或化学机械研磨去除部分介电层30以形成一浅沟隔离，并可再依据制作工艺需求进行后续栅极结构以及源极/漏极区域等晶体管元件的制作，在此不另加赘述。
值得注意的是，此退火处理不但可将掺杂层24中的掺质趋入鳍状结构14下半部20以及/或基底12内以形成抗接面击穿(APT)层，同时又可使原来具有流动性和粘度的FCVD介质材料固化成更致密结构，并去除FCVD介质材料中的部分N、H等杂质，修复缺陷，提高隔离效果。
另外本实施例虽于沉积完介电层30后才进行退火制作工艺将掺杂层24中的掺质趋入鳍状结构14下半部20以及/或基底12，但不局限于此顺序，又可选择于形成介电层30之前，例如去除未被介电层28所保护的衬垫层26与掺杂层24之后与去除介电层28之前，或是去除介电层28之后与形成介电层30之前，便进行退火制作工艺，且迨退火制作工艺结束后便直接将掺杂层24完全去除，然后再将介电层30直接覆盖于鳍状结构14上，此实施例也属本发明所涵盖的范围。
请再参照图4，其同时揭露一种半导体元件结构。如图4所示，半导体元件主要包含一基底12、至少一鳍状结构14设于基底12上、一衬垫层22设于鳍状结构14的上半部18与下半部20、一掺杂层24环绕鳍状结构14的下半部18以及另一衬垫层26设于掺杂层24上。在本实施例中，衬垫层22优选包含氧化硅，掺杂层24可包含硼硅酸盐(borosilicate glass,BSG)或磷硅酸盐(phosphosilicate glass,PSG)，而衬垫层26则包含氮化硅。
接着请参照图5至图10，图5至图10为本发明第二实施例制作一CMOS半导体元件的方法示意图。如图5所示，首先提供一基底32，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有一PMOS区域34与一NMOS区域36。基底32上具有至少一鳍状结构38设于PMOS区域34、至少一鳍状结构40设于NMOS区域34以及一硬掩模42设于各鳍状结构38、40上，其中各鳍状结构38、40另具有一上半部44与一下半部46。在本实施例中，PMOS区域34与NMOS区域36的鳍状结构38、40数量虽各以两根为例，但不局限于此。
然后可选择性利用临场蒸气产生技术(ISSG)于鳍状结构38、40表面形成一衬垫层48，其中衬垫层48优选由氧化硅所构成，且衬垫层48除了覆盖鳍状结构38、40的上半部44及下半部46之外又同时盖住基底表面。接着依序形成一掺杂层50以及另一衬垫层52于衬垫层48上并覆盖整个鳍状结构38、40。在本实施例中，衬垫层52优选由氮化硅所构成，掺杂层50的材料则由硼硅酸盐(BSG)等的含有P型掺质的材料所构成。
然后如图6所示，先形成一图案化光致抗蚀剂(图未示)覆盖NMOS区域36的鳍状结构40，利用图案化光致抗蚀剂为掩模进行一蚀刻制作工艺，去除PMOS区域34的衬垫层52与掺杂层50并暴露出PMOS区域34鳍状结构38上的衬垫层48与硬掩模42。接着去除图案化光致抗蚀剂，形成另一掺杂层54覆盖PMOS区域34所暴露出的衬垫层48与硬掩模42以及NMOS区域36的衬垫层52，其中掺杂层54优选由磷硅酸盐(PSG)等的含有N型掺质的材料所构成。
如图7所示，随后形成另一图案化光致抗蚀剂(图未示)于PMOS区域34的掺杂层54上，利用该图案化光致抗蚀剂为掩模进行一蚀刻制作工艺去除NMOS区域36的掺杂层54并再次暴露出衬垫层52。之后去除设于PMOS区域34的图案化光致抗蚀剂，然后形成另一衬垫层56覆盖PMOS区域34及NMOS区域36，包括PMOS区域34的掺杂层54与NMOS区域36的衬垫层52上。
如图8所示，先形成一保护层，例如一介电层58于PMOS区域34及NMOS区域36的衬垫层56上，然后进行一回蚀刻制作工艺，去除部分介电层58并使剩余的介电层58上表面介于鳍状结构38、40的上半部44及下半部46之间。在本实施例中，介电层58优选为一有机介电层(organic dielectriclayer,ODL)所构成，但不局限于此。
如图9所示，接着利用介电层58为蚀刻掩模进行另一蚀刻制作工艺，同时去除未被介电层58所保护的衬垫层56、掺杂层54、衬垫层52及掺杂层50，例如原本设于鳍状结构38、40上半部44周围的衬垫层56、52及掺杂层54、50，由此暴露出鳍状结构38、40的上半部44及硬掩模42。
接着如图10所示，先完全去除介电层58，然后利用可流动式化学气相沉积(FCVD)制作工艺形成一介电层60于鳍状结构38、40上，并搭配进行一退火制作工艺，将掺杂层54、50中的掺质趋入鳍状结构38、40下半部46以及/或基底32内，例如将PMOS区域34中由PSG所构成的掺杂层54的磷离子趋入至鳍状结构38下半部46，以及将NMOS区域36中由BSG所构成的掺杂层50的硼离子趋入至鳍状结构40下半部46，以于各晶体管区形成抗接面击穿(anti-punch-through)层用来避免漏电。之后可利用蚀刻以及/或化学机械研磨去除部分介电层60以形成一浅沟隔离，并可再依据制作工艺需求进行后续栅极结构以及源极/漏极区域等晶体管元件的制作，在此不另加赘述。同样的，此退火处理不但可将掺杂层54、50中的掺质分别趋入鳍状结构38、40下半部46以及/或基底32内以形成抗接面击穿(APT)层，同时又可使原来具有流动性和粘度的FCVD介质材料固化成更致密结构，并去除FCVD介质材料中的部分N、H等杂质，修复缺陷，提高隔离效果。
另外如同前述实施例，本实施例虽于沉积完介电层60后才进行退火制作工艺将掺杂层中的掺质趋入基底，但不局限于此顺序，又可选择于形成介电层60之前便进行退火制作工艺，例如去除介电层58之前或是去除介电层58之后，且迨退火制作工艺结束后便直接将掺杂层完全去除，然后再将介电层60直接覆盖于鳍状结构上，此实施例也属本发明所涵盖的范围。
综上所述，本发明主要揭露一种针对鳍状场校晶体管所进行的固态掺质(solid state doping,SSD)技术，其特别于基底上形成鳍状结构后依序于鳍状结构下半部形成一掺杂层与衬垫层，然后利用一退火制作工艺将掺杂层中的掺质驱入鳍状结构下半部以及/或基底中形成抗接面击穿层，由此改善整个元件的漏电流问题。在本实施例中，掺杂层的材料可依据所制备的晶体管型态而有所不同，例如若所制备的晶体管为NMOS晶体管，掺杂层优选由BSG所构成，反之若所制备的晶体管为PMOS晶体管，掺杂层则优选由PSG所构成。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上设有至少一鳍状结构，其中该鳍状结构包含一上半部及一下半部；以及
形成一掺杂层以及一第一衬垫层于该鳍状结构的该下半部周围。
2.如权利要求1所述的方法，还包含：
形成该掺杂层于该鳍状结构上；
形成该第一衬垫层于该掺杂层上；
形成一介电层于该第一衬垫层上并环绕该鳍状结构的该下半部；以及
去除该鳍状结构的该上半部周围的该掺杂层及该第一衬垫层。
3.如权利要求2所述的方法，还包含：
形成该介电层于该第一衬垫层上；
去除部分该介电层并使该介电层的上表面介于该鳍状结构的该上半部及该下半部之间；以及
去除该掺杂层及该第一衬垫层以暴露出该鳍状结构的该上半部。
4.如权利要求2所述的方法，还包含于去除该鳍状结构的该上半部周围的该掺杂层及该第一衬垫层后对该鳍状结构的该下半部周围的该掺杂层及该第一衬垫层进行一退火制作工艺。
5.如权利要求1所述的方法，其中该掺杂层包含硼硅酸盐(borosilicateglass,BSG)或磷硅酸盐(phosphosilicate glass,PSG)。
6.如权利要求1所述的方法，还包含于形成该掺杂层之前形成一硬掩模于该鳍状结构上。
7.如权利要求1所述的方法，还包含于形成该掺杂层之前形成一第二衬垫层于该鳍状结构的该上半部及该下半部上。
8.如权利要求7所述的方法，其中该第一衬垫层包含氮化硅且该第二衬垫层包含氧化硅。
9.一种制作半导体元件的方法，包含：
提供一基底，该基底上定义有一第一区域及一第二区域；
形成一第一鳍状结构于该第一区域上以及一第二鳍状结构于该第二区域上，其中该第一鳍状结构及该第二鳍状结构各包含一上半部与一下半部；
形成一第一掺杂层及一第一衬垫层于该第二鳍状结构的该下半部周围；以及
形成一第二掺杂层及一第二衬垫层于该第一鳍状结构的该下半部周围。
10.如权利要求9所述的方法，还包含：
形成该第一掺杂层于该第一鳍状结构及该第二鳍状结构上；
形成该第一衬垫层于该第一掺杂层上；
去除该第一鳍状结构上的该第一衬垫层及该第一掺杂层；
形成该第二掺杂层于该第一鳍状结构及该第二鳍状结构上；
去除该第二鳍状结构上的该第二掺杂层；
形成该第二衬垫层于该第一鳍状结构及该第二鳍状结构上；
形成一介电层于该第二衬垫层上并环绕该第一鳍状结构及该第二鳍状结构的该下半部；以及
去除该第一鳍状结构及该第二鳍状结构的该上半部周围的该第二衬垫层、该第二掺杂层、该第一衬垫层及该第一掺杂层。
11.如权利要求10所述的方法，还包含：
形成该介电层于该第二衬垫层上；
去除部分该介电层并使该介电层的上表面介于该第一鳍状结构及该第二鳍状结构的该上半部及该下半部之间；以及
去除该第二衬垫层、该第二掺杂层、该第一衬垫层及该第一掺杂层以暴露出该第一鳍状结构及该第二鳍状结构的该上半部。
12.如权利要求10所述的方法，还包含于去除该第一鳍状结构及该第二鳍状结构的该上半部周围的该第二衬垫层、该第二掺杂层、该第一衬垫层及该第一掺杂层之后对该第一鳍状结构及该第二鳍状结构的该下半部周围的该第二衬垫层、第二掺杂层、该第一衬垫层及该第一掺杂层进行一退火制作工艺。
13.如权利要求9所述的方法，其中该第一区域包含一PMOS区域，该第一掺杂层包含硼硅酸盐(borosilicate glass,BSG)，该第二区域包含一NMOS区域，且该第二掺杂层包含磷硅酸盐(phosphosilicate glass,PSG)。
14.如权利要求9所述的方法，还包含于形成该第一掺杂层之前形成一硬掩模于该第一鳍状结构及该第二鳍状结构上。
15.如权利要求9所述的方法，还包含于形成该第一掺杂层之前形成一第三衬垫层于该第一鳍状结构及该第二鳍状结构的该上半部及该下半部上。
16.如权利要求15所述的方法，其中该第一衬垫层及该第二衬垫层包含氮化硅且该第三衬垫层包含氧化硅。
17.一种半导体元件，包含：
基底，该基底上设有一鳍状结构，其中该鳍状结构包含一上半部及一下半部；
掺杂层环绕该鳍状结构的该下半部；以及
第一衬垫层设于该掺杂层上。
18.如权利要求17所述的半导体元件，其中该掺杂层包含硼硅酸盐(borosilicate glass,BSG)或磷硅酸盐(phosphosilicate glass,PSG)。
19.如权利要求17所述的半导体元件，还包含一第二衬垫层设于该鳍状结构的该上半部及该下半部上。
20.如权利要求17所述的半导体元件，其中该第一衬垫层及该第二衬垫层包含不同材料。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106067479A (zh) * 2015-04-22 2016-11-02 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN109390401A (zh) * 2017-08-10 2019-02-26 联华电子股份有限公司 半导体元件及其制作方法
CN109830462A (zh) * 2017-11-23 2019-05-31 联华电子股份有限公司 制作半导体元件的方法
CN110391231A (zh) * 2018-04-16 2019-10-29 联华电子股份有限公司 半导体元件及其制作方法
CN113394108A (zh) * 2021-05-31 2021-09-14 上海华力集成电路制造有限公司 一种用于FinFET多阈值电压的无损伤掺杂方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10818558B2 (en) 2015-04-24 2020-10-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure having trench and manufacturing method thereof
US9805987B2 (en) 2015-09-04 2017-10-31 International Business Machines Corporation Self-aligned punch through stopper liner for bulk FinFET
CN106952873B (zh) * 2016-01-07 2019-11-01 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
CN106952822A (zh) * 2016-01-07 2017-07-14 中芯国际集成电路制造(上海)有限公司 改善鳍式场效应管性能的方法
US10504821B2 (en) * 2016-01-29 2019-12-10 United Microelectronics Corp. Through-silicon via structure
CN107799421B (zh) * 2016-09-05 2021-04-02 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN109309056B (zh) 2017-07-27 2020-12-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10504898B2 (en) * 2017-08-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field-effect transistor structure and method for forming the same
US10410928B2 (en) * 2017-11-28 2019-09-10 International Business Machines Corporation Homogeneous densification of fill layers for controlled reveal of vertical fins
US11527653B2 (en) * 2020-07-22 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US20220037197A1 (en) * 2020-07-28 2022-02-03 Nanya Technology Corporation Method of manufacturing semiconductor structure and semiconductor structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386230A (zh) * 2010-09-01 2012-03-21 台湾积体电路制造股份有限公司 半导体组件及形成多位鳍状场效晶体管组件的方法
US20130115763A1 (en) * 2011-11-04 2013-05-09 ASM International. N.V. Methods for forming doped silicon oxide thin films
CN103531478A (zh) * 2012-07-03 2014-01-22 台湾积体电路制造股份有限公司 多栅极fet及其形成方法
CN103579002A (zh) * 2012-08-03 2014-02-12 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN104051502A (zh) * 2013-03-14 2014-09-17 国际商业机器公司 通过阳极化形成具有介质隔离的体SiGe鳍片

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7955928B2 (en) 2009-03-30 2011-06-07 International Business Machines Corporation Structure and method of fabricating FinFET
US8207032B2 (en) * 2010-08-31 2012-06-26 Micron Technology, Inc. Methods of forming pluralities of vertical transistors, and methods of forming memory arrays
US9219115B2 (en) * 2013-10-11 2015-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Forming conductive STI liners for FinFETS
US9362404B2 (en) * 2014-02-21 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Doping for FinFET

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386230A (zh) * 2010-09-01 2012-03-21 台湾积体电路制造股份有限公司 半导体组件及形成多位鳍状场效晶体管组件的方法
US20130115763A1 (en) * 2011-11-04 2013-05-09 ASM International. N.V. Methods for forming doped silicon oxide thin films
CN103531478A (zh) * 2012-07-03 2014-01-22 台湾积体电路制造股份有限公司 多栅极fet及其形成方法
CN103579002A (zh) * 2012-08-03 2014-02-12 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN104051502A (zh) * 2013-03-14 2014-09-17 国际商业机器公司 通过阳极化形成具有介质隔离的体SiGe鳍片

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106067479B (zh) * 2015-04-22 2019-10-15 台湾积体电路制造股份有限公司 半导体结构及其制造方法
US10535768B2 (en) 2015-04-22 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
CN106067479A (zh) * 2015-04-22 2016-11-02 台湾积体电路制造股份有限公司 半导体结构及其制造方法
US11355635B2 (en) 2015-04-22 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and methods of forming same
CN109390401A (zh) * 2017-08-10 2019-02-26 联华电子股份有限公司 半导体元件及其制作方法
CN109390401B (zh) * 2017-08-10 2022-07-05 联华电子股份有限公司 半导体元件及其制作方法
CN109830462B (zh) * 2017-11-23 2021-06-22 联华电子股份有限公司 制作半导体元件的方法
CN109830462A (zh) * 2017-11-23 2019-05-31 联华电子股份有限公司 制作半导体元件的方法
CN110391231B (zh) * 2018-04-16 2020-09-22 联华电子股份有限公司 半导体元件及其制作方法
US10804365B2 (en) 2018-04-16 2020-10-13 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN110391231A (zh) * 2018-04-16 2019-10-29 联华电子股份有限公司 半导体元件及其制作方法
US11799012B2 (en) 2018-04-16 2023-10-24 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN113394108A (zh) * 2021-05-31 2021-09-14 上海华力集成电路制造有限公司 一种用于FinFET多阈值电压的无损伤掺杂方法

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US20170033019A1 (en) 2017-02-02
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