CN109390401A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN109390401A
CN109390401A CN201710679485.5A CN201710679485A CN109390401A CN 109390401 A CN109390401 A CN 109390401A CN 201710679485 A CN201710679485 A CN 201710679485A CN 109390401 A CN109390401 A CN 109390401A
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solid
area
dopant source
layer
state dopant
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CN109390401B (zh
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刘恩铨
童宇诚
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/691,717 priority patent/US10205005B1/en
Priority to US16/212,700 priority patent/US10312353B2/en
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Abstract

本发明公开一种半导体元件及其制作方法。制作半导体结构的方法的步骤包含分别在第一区域、第二区域以及虚置区域上形成多个鳍结构、在第一区域中形成一第一固态掺质来源层以及一第一绝缘缓冲层、在第二区域以及虚置区域中形成一第二固态掺质来源层以及一第二绝缘缓冲层、以及进行一蚀刻制作工艺削减该虚置区域中的鳍结构。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法有关，特别是涉及一种利用固态掺质(solid state doping,SSD)技术于鳍状结构下半部形成掺杂层的半导体元件及其制作方法。
背景技术
近年来，随着关键元件尺寸持续地缩小，现有的平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面式(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,FinFET)等元件来取代平面晶体管元件的设计已成为目前的主流发展趋势。
由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增进栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(drain induced barrier lowering,DIBL)效应，并可以抑制短通道效应(shortchannel effect,SCE)。
再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数来加以调控。
现时，具有鳍状场效晶体管架构的微集成电路元件可依靠固态掺杂扩散方式，将掺质来源层形成在较基底靠近主动区域的子鳍部(sub-fin)区域部位的侧壁上。掺质会从掺质来源层被驱入靠近来源层的子鳍部区域。
然而，现行的鳍状场效晶体管元件制作工艺仍需要加以改进，例如如何在固态掺质阶段后有效率地去移除主动区域间不需要的虚置鳍(dummy fins)结构。因此，如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明的其一目的即在于提供一种在固态掺杂后阶段移除虚置鳍结构的制作工艺。
为了达到此目的，本发明优选实施例提出了一种制作半导体元件的方法，其步骤包含：提供一基底，其具有一第一区域、一第二区域以及一虚置区域；分别在该第一区域、该第二区域以及该虚置区域中形成多个鳍结构；在第一区域中形成一第一固态掺质来源层；在该第一固态掺质来源层上形成一第一绝缘缓冲层；在第二区域以及该虚置区域中形成一第二固态掺质来源层；在第二固态掺质来源层及第一绝缘缓冲层上形成一第二绝缘缓冲层；以及进行一蚀刻制作工艺来削减该虚置区域中的鳍结构。
本发明也提出了一种以上述方法制得的半导体结构，其结构包含：一基底，其具有一第一区域、一第二区域以及介于该第一区域与该第二区域之间的虚置区域；多个鳍结构位于该第一区域与该第二区域中；至少一虚置鳍结构位于该虚置区域中；一第一固态掺质来源层位于第一区域中；一第一绝缘缓冲层位于该第一固态掺质来源层上；一第二固态掺质来源层位于第二区域与该虚置区域中；一第二绝缘缓冲层位于第二固态掺质来源层上；以及一介电层位于基底上，其中该介电层、该第二绝缘缓冲层、该第一绝缘缓冲层、该第一固态掺质来源层以及该第二固态掺质来源层的顶面低于该些鳍结构的顶面，且该虚置鳍结构的顶面低于该介电层、该第二绝缘缓冲层、该第一绝缘缓冲层、该第一固态掺质来源层以及该第二固态掺质来源层的顶面。
本发明的这类目的与其他目的在阅者读过下文以多种图示与绘图来描述的优选实施例细节说明后必然可变得更为明了显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些图示描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些图示中：
图1至图8以及图12为本发明实施例制作半导体结构的制作工艺方法的截面示意图；
图9为本发明另一实施例一半导体结构的截面示意图；
图10为本发明又一实施例一半导体结构的截面示意图；以及
图11为本发明又一实施例一半导体结构的截面示意图；
图12为本发明在鳍结构以及虚置鳍结构上形成栅极的截面示意图；以及
图13为本发明虚置鳍结构上不具有栅极的截面示意图。
需注意本说明书中的所有图示都为图例性质，为了清楚与方便图示说明之故，图示中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
100 基底
100a 第一区域
100b 第二区域
100c 虚置区域
102 鳍结构
102a 凸出部位
104 硬掩模层
106 衬垫氧化层
108 第一固态掺质来源层
110 第一绝缘缓冲层
112 第二固态掺质来源层
114 第二绝缘缓冲层
116 介电层
118 蚀刻掩模
118a 开口
119 虚置鳍结构
120 沟槽
122 栅极
122a,122b,122c 栅极区段
具体实施方式
在下文的本发明细节描述中，元件符号会标示在随附的图示中成为其中的一部份，并且以可实行该实施例的特例描述方式来表示。这类的实施例会说明足够的细节使该领域的一般技术人士得以具以实施。为了图例清楚之故，图示中可能有部分元件的厚度会加以夸大。阅者需了解到本发明中也可利用其他的实施例或是在不悖离所述实施例的前提下作出结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由随附的权利要求来加以界定。
在说明优选实施例之前，通篇说明书中会使用特定的词汇来进行描述。例如文中所使用的「蚀刻」一词一般是用来描述图形化一材料的制作工艺，如此制作工艺完成后至少会有部分的该材料余留下来。需了解蚀刻硅材料的制作工艺都会牵涉到在硅材料上图形化一光致抗蚀剂层的步骤，并在之后移除未被光致抗蚀剂层保护的硅区域。如此，被光致抗蚀剂层保护的硅区域会在蚀刻制作工艺完成后保留下来。然而在其他例子中，蚀刻动作也可能指的是不使用光致抗蚀剂层的制作工艺，但其在蚀刻制作工艺完成后仍然会余留下来至少部分的目标材料层。
上述说明的用意在于区别「蚀刻」与「移除」两词。当蚀刻某材料时，制作工艺完成后至少会有部分的该材料于留下来。相较之下，当移除某材料时，基本上所有的该材料在该制作工艺中都会被移除。然而在某些实施例中，「移除」一词也可能会有含括蚀刻意涵的广义解释。
文中所说明的「基底」、「半导体基底」或「晶片」等词通常大多为硅基底或是硅晶片。然而，「基底」、或「晶片」等词也可能指的是任何半导体材质，诸如锗、砷化锗、磷化铟等种类的材料。在其他实施例中，「基底」、或「晶片」等词也可能指的是非导体类的玻璃或是蓝宝石基板等材料。
图1至图8是本发明的截面示意图，其描绘出根据本发明实施例制作一半导体晶体管元件的制作工艺范例。首先如图1所示，提供一半导体基底100。半导体基底100含有一第一区域100a、一第二区域100b、以及一位于第一区域100a与第二区域100b之间的虚置区域100c。例如，第一区域100a可为一NMOS区域而第二区域100b可为一PMOS区域。第一区域100a与第二区域100b不会重叠。接着，分别在第一区域100a、一第二区域100b、以及虚置区域100c中形成多个鳍结构102。在此实施例中，虚置区域100c可设置在第二区域100b的外围，但不限于此。在其他实施例中，它也可以是设置在第一区域100a的外围。在半导体基底上形成半导体鳍结构的制作工艺是公知技术，其可能包含光刻蚀刻等步骤，其细节此处将不予赘述。
根据本发明实施例，每根鳍结构的顶部都可以选择性地具有一衬垫氧化层(未示出)，如二氧化硅层，以及一硬掩模层(未示出)，如一氮化硅硬掩模层。再者，鳍结构上可以选择性地形成一氧化层(未示出)，如以临场蒸气产生技术(in-situ steam generation,ISSG)所形成的氧化硅层，但不限于此。
接着，如图2所示，半导体基底100的第一区域100a中形成一第一固态掺质来源层108，如通过化学气相沉积法。第一固态掺质来源层108是共形地沉积在半导体基底100上。根据本发明实施例，第一固态掺质来源层108可包含p类型的掺质，如一硼硅玻璃(borosilicate glass,BSG)层，但不限于此。之后形成一第一绝缘缓冲层110在第一区域100a中的第一固态掺质来源层108上。第一绝缘缓冲层110可包含氮化硅，但不限于此。第一绝缘缓冲层110可通过化学气相沉积法来形成。
详细来说，可先在整个基底上形成第一固态掺质来源层108以及第一绝缘缓冲层110，之后通过光致抗蚀剂等蚀刻掩模(未示出)遮挡住第一区域100a而不遮挡第二区域100b与虚置区域100c，再进行蚀刻制作工艺移除第二区域100b与虚置区域100c中未被蚀刻掩模覆盖的第一固态掺质来源层108与第一绝缘缓冲层110，如此第一固态掺质来源层108与第一绝缘缓冲层110只会形成在第一区域100a中。在该蚀刻制作工艺后蚀刻掩模会被移除。
接着，如图3所示，沉积一第二固态掺质来源层112在半导体基底100的第二区域100b中，如通过化学气相沉积法。第二固态掺质来源层112是共形地沉积在半导体基底100上。根据本发明实施例，第二固态掺质来源层112可包含n类型的掺质，如一磷硅玻璃(phosphosilicate glass,PSG)层或一砷硅玻璃(arsenic silicate glass,PSG)层，但不限于此。
详细来说，可先在整个基底上形成第二固态掺质来源层112，之后通过光致抗蚀剂等蚀刻掩模(未示出)遮挡住第二区域100b以及虚置区域100c而不遮挡第一区域100a，再进行蚀刻制作工艺移除第一区域100a中未被蚀刻掩模覆盖的第二固态掺质来源层112，如此裸露出第一区域100a中的第一绝缘缓冲层110，而第二固态掺质来源层112只会形成在第二区域100b以及虚置区域100c中。在该蚀刻制作工艺后蚀刻掩模会被移除。
如图4所示，之后形成一第二绝缘缓冲层114在第一区域100a中的第一绝缘缓冲层110上以及第二区域100b与虚置区域100c中的第二固态掺质来源层112上。第二绝缘缓冲层114可包含氮化硅，但不限于此。第二绝缘缓冲层114可通过化学气相沉积法来形成。
接着，如图5所示，在鳍结构102之间的基底100上形成一介电层116，如二氧化硅层。根据本发明实施例，介电层116可通过化学气相沉积法来形成，但不限于此，来填入鳍结构102之间凹槽中。再者，之后可进行一平坦化制作工艺，如化学机械研磨制作工艺，来移除部分的介电层116以及鳍结构102至一预定高度。在该平坦化制作工艺后，介电层116、鳍结构102、第一固态掺质来源层108、第二固态掺质来源层112、第一绝缘缓冲层110、以及第二绝缘缓冲层114的顶面会齐平。
再者，在上述的平坦化制作工艺后，进行一热掺杂制作工艺将第一固态掺质来源层108以及第二固态掺质来源层112中的掺质分别驱入第一区域100a、第二区域100b以及虚置区域100c中的鳍结构102中。以此方式，第一区域100a与第二区域100b的鳍结构102中会分别形成具有不同导电类型的掺杂部位。除了鳍结构102外，所形成的掺杂部位也可能延伸进入基底100内达一预定的深度。
接下来如图6所示，介电层116、第二绝缘缓冲层114、第一绝缘缓冲层110、第一固态掺质来源层108以及第二固态掺质来源层112会被回蚀至低于鳍结构102顶面的一预定高度，而裸露出每一鳍结构102的凸出部位102a。第一固态掺质来源层108以及第二固态掺质来源层112被回蚀后的高度会决定出后续每一鳍结构102的通道部位。
接着，如图7所示，使用一蚀刻掩模118，如一光致抗蚀剂，来阻挡住第一区域100a与第二区域100b。蚀刻掩模118会具有一开口118a裸露出第一区域100a与第二区域100b之间的虚置区域100c中的鳍结构102。
在蚀刻掩模118形成后，进行一各向异性蚀刻制作工艺来从开口118a裸露出的鳍结构102，使得该鳍结构被削减至低于周围介电层116顶面的高度，而形成一虚置鳍结构119，如图8所示。之后再将蚀刻掩模118移除。
尽管在此实施例中虚置鳍结构119的两侧都是第二固态掺质来源层112与第二绝缘缓冲层114，然而在其他实施例中，虚置鳍结构119也可能是一侧为第二固态掺质来源层112与第二绝缘缓冲层114，另一侧为第一固态掺质来源层108与第一绝缘缓冲层110，端视第一固态掺质来源层108与第二固态掺质来源层112所预定形成的区域而定。
在本发明另一实施例中，如图9所示，该鳍结构102也可被完全移除而在第一区域100a与第二区域100b之间形成一没有鳍结构的虚置区域100c，其鳍结构102削减后所形成的沟槽119a可深入基底100至低于掺杂区域的深度。
在本发明又一实施例中，削减制作工艺也可能会移除部分的第二固态掺质来源层112以及第二绝缘缓冲层114，使得其顶面低于介电层116的顶面。特别是削减制作工艺对第二固态掺质来源层112以及第二绝缘缓冲层114具有不同的蚀刻速率，如此会形成如图10所示虚置鳍结构119两侧的第二固态掺质来源层112的顶面高于第二绝缘缓冲层114的顶面，而两者的顶面又高于虚置鳍结构119顶面的态样。
在本发明又另一实施例中，削减制作工艺也可能对于第二固态掺质来源层112以及第二绝缘缓冲层114具有较的鳍结构而言较大的蚀刻速率，使得削减制作工艺后虚置鳍结构119两侧的第二固态掺质来源层112以及第二绝缘缓冲层114会被完全移除，形成如图11所示介于虚置鳍结构119与介电层116之间的沟槽120，其沟槽120可稍微深入基底100中的掺杂区域。
接着，如图12所示，在介电层116上形成一栅极122。栅极122会横跨每根鳍结构102的凸出部位102a并完全覆盖虚置区域100c。根据本发明实施例，栅极122可包含金属栅极，其可通过取代式金属栅极(replacement metal gate)制作工艺来形成，例如先在基底以及鳍结构上形成一虚置栅极(dummy gate)以及层间介电层，之后再将虚置栅极移除填入金属材料的方式来形成。之后可在栅极122两对侧的凸出部位102a中形成源极区域与漏极区域(未示出)，并在之后可在该源极区域与漏极区域中形成锗化硅(SiGe)或磷化硅(SiP)等外延结构。
最后，根据本发明实施例，如图12所示，其后还可包含将栅极122切成多个栅极区段122a,122b,122c的步骤。为图示简明之故，其他金属栅极中的现有部件，如高介电常数层、功函数层、或低阻质金属层等，在图12中不予示出。
在其他实施例中，如图13所示，虚置区域100c以及虚置鳍结构119上也可能设计成不具有栅极122，其图12中原本上方的栅极区段122c在栅极切割步骤中会被移除。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (19)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底具有第一区域、第二区域、以及虚置区域；
在该第一区域、该第二区域以及该虚置区域中形成多个鳍结构；
在该第一区域中形成一第一固态掺质来源层；
在该第一固态掺质来源层上形成一第一绝缘缓冲层；
在该第二区域以及该虚置区域中形成一第二固态掺质来源层；
在该第一绝缘缓冲层上以及该第二固态掺质来源层上形成一第二绝缘缓冲层；以及
进行一蚀刻制作工艺来削减该虚置区域上的该鳍结构以形成虚置鳍结构。
2.如权利要求1所述的制作半导体元件的方法，其中在该第一区域中形成该第一固态掺质来源层的步骤还包含：
遮挡该第一区域；以及
移除该第二区域上的该第一固态掺质来源层以及该第一绝缘缓冲层，使得该第二区域中的该鳍结构以及该基底裸露出来。
3.如权利要求1所述的制作半导体元件的方法，其中在该第二区域以及该虚置区域中形成该第二固态掺质来源层的步骤还包含：
在该第一区域、该第二区域以及该虚置区域上形成该第二固态掺质来源层；
遮挡该第二区域与该虚置区域；以及
移除该第一区域上的该第二固态掺质来源层，使得该第一区域中的该第一绝缘缓冲层裸露出来。
4.如权利要求1所述的制作半导体元件的方法，其中在形成该光致抗蚀剂前还包含：
在该第一区域、该第二区域以及该虚置区域上形成一介电层；
回蚀刻该介电层、该第二绝缘缓冲层、该第一绝缘缓冲层、该第一固态掺质来源层以及该第二固态掺质来源层至低于该些鳍结构的顶面，以裸露出每一该些鳍结构的凸出部位；以及
将该第一固态掺质来源层中以及该第二固态掺质来源层中的掺质分别扩散进入该第一区域与该第二区域的该鳍结构中。
5.如权利要求4所述的制作半导体元件的方法，还包含：
在削减该虚置区域上的该鳍结构后形成一金属栅极横跨该些鳍结构并覆盖该虚置区域；
在该金属栅极两侧的该些鳍结构的该些凸出部位中形成源极与漏极；以及
将该金属栅极切成多个栅极区段。
6.如权利要求4所述的制作半导体元件的方法，其中该虚置区域中的该鳍结构被削减至低于该介电层、该第二绝缘缓冲层、该第一固态掺质来源层以及该第二固态掺质来源层的顶面。
7.如权利要求1所述的制作半导体元件的方法，其中该虚置区域中的该鳍结构被完全削减与移除。
8.如权利要求1所述的制作半导体元件的方法，其中该虚置鳍结构两侧的该第二绝缘缓冲层以及该第二固态掺质来源层的顶面在该削减步骤后高于剩余的该虚置鳍结构但低于该介电层，且该虚置鳍结构两侧的该第二绝缘缓冲层的顶面在该削减步骤后低于该第二固态掺质来源层的顶面。
9.如权利要求1所述的制作半导体元件的方法，其中在该虚置鳍结构两侧的该第二绝缘缓冲层以及该第二固态掺质来源层在该削减步骤被完全移除，使得剩余的该虚置鳍结构与该介电层之间形成沟槽。
10.一种半导体元件，包含：
具有第一区域、第二区域以及虚置区域的半导体基底；
多个鳍结构，位于该第一区域与该第二区域中；
虚置区域，位于该第一区域与该第二区域之间，其中该虚置区域具有一沟槽；
第一固态掺质来源层，位于该第一区域中；
第一绝缘缓冲层，位于该第一固态掺质来源层上；
第二固态掺质来源层，位于该第二区域以及该虚置区域中；
第二绝缘缓冲层，位于该第二固态掺质来源层上；以及
介电层，位于该基底；
其中该介电层、该第二绝缘缓冲层、该第一绝缘缓冲层、该第一固态掺质来源层以及该第二固态掺质来源层的顶面低于该些第一半导体鳍结构与该些第二半导体鳍结构的顶面，且该虚置区域中的该沟槽的底面低于该介电层。
11.如权利要求10所述的半导体元件，其中该虚置区域中具有至少一虚置鳍结构位于该沟槽中。
12.如权利要求11所述的半导体元件，其中该虚置鳍结构两侧的该第二绝缘缓冲层的顶面低于该第二固态掺质来源层的顶面。
13.如权利要求11所述的半导体元件，其中该虚置鳍结构的顶面低于该介电层、该第二绝缘缓冲层、该第一绝缘缓冲层、该第一固态掺质来源层以及该第二固态掺质来源层的顶面。
14.如权利要求11所述的半导体元件，还包含两沟槽分别位于该虚置鳍结构的两侧与该介电层之间。
15.如权利要求11所述的半导体元件，其中该第二绝缘缓冲层覆盖在该第一区域中的该第一绝缘缓冲层上。
16.如权利要求11所述的半导体元件，还包含一金属栅极横跨该些鳍结构并覆盖该虚置区域。
17.如权利要求11所述的半导体元件，其中该第一固态掺质来源层包含硼硅玻璃(borosilicate glass,BSG)。
18.如权利要求11所述的半导体元件，其中该第二固态掺质来源层包含磷硅玻璃(phosphosilicate glass,PSG)或砷硅玻璃(arsenic silicate glass,AsSG)。
19.如权利要求11所述的半导体元件，其中该第一绝缘缓冲层与该第二绝缘缓冲层包含氮化硅。
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