CN106067479A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
CN106067479A
CN106067479A CN201510979036.3A CN201510979036A CN106067479A CN 106067479 A CN106067479 A CN 106067479A CN 201510979036 A CN201510979036 A CN 201510979036A CN 106067479 A CN106067479 A CN 106067479A
Authority
CN
China
Prior art keywords
semiconductor fin
impurity
semiconductor
ldd
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510979036.3A
Other languages
English (en)
Other versions
CN106067479B (zh
Inventor
蔡俊雄
游国丰
陈科维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106067479A publication Critical patent/CN106067479A/zh
Application granted granted Critical
Publication of CN106067479B publication Critical patent/CN106067479B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

半导体结构包括衬底、第一半导体鳍、第二半导体鳍和第一轻掺杂漏极(LDD)区。第一半导体鳍设置在衬底上。第一半导体鳍具有顶面和侧壁。第二半导体鳍设置在衬底上。第一半导体鳍和第二半导体鳍彼此间隔开纳米尺度的距离。第一轻掺杂漏极(LDD)区至少设置在第一半导体鳍的顶面和侧壁中。本发明的实施例还涉及半导体结构的制造方法。

Description

半导体结构及其制造方法
优先权声明和交叉引用
本申请要求2015年4月22日提交的美国临时申请第62/151,286号的优先权，其内容结合于此作为参考。
技术领域
本发明总的来说涉及半导体器件，更具体地涉及鳍式场效应晶体管(FinFET)。
背景技术
双栅极金属氧化物半导体场效应晶体管(双栅极MOSFET)为将两个栅极并入单个器件中的MOSFET。由于它们的结构包括从衬底延伸的薄“鳍”，因此这些器件还称为鳍式场效应晶体管(FinFET)。双栅极是指在沟道两侧上均存在栅极，其允许栅极从两侧控制沟道。此外，FinFET可减少短沟道效应以及提供较高的电流。其他FinFET结构也可包括三个或多个有效栅极。
发明内容
本发明的实施例提供了一种半导体结构，包括：衬底；第一半导体鳍，设置在所述衬底上，其中，所述第一半导体鳍具有顶面和侧壁；第二半导体鳍，设置在所述衬底上，其中，所述第一半导体鳍和所述第二半导体鳍彼此间隔开纳米尺度的距离；以及第一轻掺杂漏极(LDD)区，至少设置在所述第一半导体鳍的顶面和侧壁中。
本发明的另一实施例提供了一种制造半导体结构的方法，所述方法包括：在衬底上形成至少一个半导体鳍，其中，所述半导体鳍具有顶面和侧壁；在所述半导体鳍的顶面和侧壁上形成至少一个介电层；在所述介电层上形成包含至少一种杂质的富掺杂剂层；以及驱使所述杂质通过所述介电层进入所述半导体鳍中。
本发明的又一实施例提供了一种制造半导体结构的方法，所述方法包括：在衬底上形成至少一个第一半导体鳍和至少一个第二半导体鳍，其中，所述第一半导体鳍具有顶面和侧壁；在所述第一半导体鳍的顶面和侧壁上形成至少一个第一介电层；形成第一光刻胶以覆盖所述第二半导体鳍，所述第一介电层未被覆盖；将至少一种第一杂质注入所述第一介电层中；去除所述第一光刻胶；以及将所述第一杂质驱至所述第一半导体鳍中。
附图说明
在阅读附图时，本发明的各个方面可从下列详细描述获得最深入理解。应当注意，根据工业中的标准实践，各个部件并非按比例绘制。实际上，为了清楚的讨论，可任意增大或减小各个部件的尺寸。
图1至图17是根据一些实施例的在制造鳍式场效应晶体管(FinFET)的中间阶段的截面图。
图18示出了用于实施等离子体离子辅助沉积(PIAD)的装置。
图19示出在等离子体离子辅助沉积(PIAD)期间施加的示意性射频(RF)和直流(DC)偏压。
具体实施方式
下列公开提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下文描述组件和布置的具体实例以简化本公开。当然，这些仅为实例并且不旨在限制本发明。例如，下列描述中，第二部件上方或上形成第一部件可包括其中第一和第二部件直接接触形成的实施例，并且还可包括在第一和第二部件之间可形成额外部件，使得所述第一和第二部件可以不直接接触的实施例。此外，本公开在各个实施例中可重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且本身并不指示所讨论的各个实施例和/或配置之间的关系。
此外，为便于描述，空间相对术语如“在…之下(beneath)”、“在…下方(below)”、“下部(lower)”、“在…之上(above)”、“上部(upper)”等在本文可用于描述附图中示出的一个元件或部件与另一个(或另一些)元件或部件的关系。除附图中描述的方位之外，空间相对术语旨在包括器件在使用中或运行中的不同方位。装置可以其他方式定向(旋转90度或在其他方位上)，本文使用的空间相对描述符可同样地作相应解释。
参考图1，形成集成电路结构。示出的集成电路结构包括部分晶圆100，晶圆100包括衬底110。衬底110可由诸如金刚石、硅(Si)、锗(Ge)、碳化硅(SiC)、硅-锗(SiGe)或其组合的半导体材料制成。衬底110可掺杂p-型或n-型杂质。可在衬底110中或上方形成诸如浅沟槽隔离(STI)区域120的隔离区域。在STI区域120的顶面之上形成半导体鳍130和140。衬底110包括第一器件区I中的部分和第二器件区II中的部分。半导体鳍130位于第一器件区I中，而半导体鳍140位于第二器件区II中。在一些实施例中，第一器件区I用于形成N-型鳍式场效应晶体管(FinFET)，而第二器件区II用于形成P-型FinFET。
在一些实施例中，通过首先形成浅沟槽隔离(STI)区域120，然后使STI区域120的顶面凹进至低于衬底110的起始顶面的水平面而形成半导体鳍130和140。由此，STI区域120之间的衬底110的剩余部分成为半导体鳍130和140。在半导体鳍130和140由与衬底110不同的材料制成的实施例中，可通过使相邻STI区域120之间的衬底110的顶部凹进以形成凹槽和在凹槽中重新生长与衬底110不同的半导体材料来形成半导体鳍130和140。然后，可去除STI区域120的顶部，但不去除STI区域120的底部，使得相邻STI区域120之间的重新生长的半导体材料的顶部成为半导体鳍130和140。半导体鳍130和140可具有沟道掺杂剂，该沟道掺杂剂通过注入或者通过与生长半导体鳍130和140同时实施的原位掺杂引入。
参考图2，在半导体鳍130和140上方形成栅极介电层150和栅电极层160。在一些实施例中，栅极介电层150由例如二氧化硅(SiO2)制成并通过原位蒸汽生成(ISSG)氧化形成。栅极介电层150具有从约0.5nm至约10nm的范围内的厚度。在一些其他实施例中，例如，栅极介电层150由高-k介电材料制成。高-k介电材料的介电常数大于二氧化硅(SiO2)的介电常数，具体为约4，或甚至大于约7。高-k介电材料可包括含铝电介质，诸如Al2O3、HfAlO、HfAlON、AlZrO；含Hf材料，诸如HfO2、HfSiOx、HfAlOx、HfZrSiOx、HfSiON；和/或其他材料，诸如LaAlO3和ZrO2。在栅极介电层150上形成栅电极层160。栅电极层160可由诸如掺杂多晶硅、金属、金属氮化物或其组合的导电材料制成。
参考图3，然后，将栅电极层160图案化以形成栅极堆叠件。在一些实施例中，可使用栅极介电层150覆盖半导体鳍130和140。在一些其他实施例中，还将栅极介电层150图案化，使得半导体鳍130和140具有未被栅极介电层150和栅电极层160覆盖的部分。
参考图4，在半导体鳍130和140上方形成密封间隔件170。密封间隔件170由诸如氮化硅(Si3N4)、碳氮氧化硅(SiCON)、碳氮化硅(SiCN)或其组合的介电材料制成。密封间隔件170具有从约1nm至约10nm、从约1nm至约7nm或从约5nm至约10nm的范围内的厚度。图4至图17为沿着图3的线A-A截取的截面图。因此，未示出图案化的栅电极层160。
参考图5，形成光刻胶180并将其图案化以覆盖第二器件区II，同时保持第一器件区I未覆盖。具体地，通过例如旋转涂覆将光刻胶180施加在晶圆100上。然后，预烘焙光刻胶180以驱除过量的光刻胶溶剂。在预烘焙后，将光刻胶180暴露于强光的图案。暴露于光引起化学变化，该化学变化使一些光刻胶180可溶于显影剂。可在显影之前实施曝光后烘焙(PEB)以帮助减少驻波现象，驻波现象由入射光的破坏性和建设性干涉图案所致。然后，将显影剂施加在光刻胶180上以去除一些可溶于显影剂的光刻胶180。然后，硬烘焙剩余的光刻胶180以固化剩余的光刻胶180。
在图案化光刻胶180后，在密封间隔件170上形成富掺杂剂层190。例如，可通过等离子体离子辅助沉积(PIAD)形成富掺杂剂层190。具体地，可将晶圆100放入如图18所示的用于实施PIAD的装置300中。装置300包括室310以及与室310连接的电源320和330，在室310中放置晶圆100。电源320可为具有可程序化脉冲调制功能的射频(RF)电源，同时电源330可为用于提供DC偏压的直流(DC)电源。
电源320和330可彼此独立地运行。可将电源320和330程序化以独立地打开和关闭而不彼此影响。如图5示出的，使用如图18所示的装置300，在第一器件区I中的密封间隔件170上形成富掺杂剂层190。富掺杂剂层190具有至少一种杂质，其用于在半导体鳍130中形成轻掺杂漏极(LLD)区。取决于产生的鳍式场效应晶体管(FinFET)的导电类型，富掺杂剂层190可具有n-型杂质(杂质)或p-型杂质(杂质)。例如，如果产生的FinFET为n-型FinFET，则富掺杂剂层190中的杂质可为磷、砷或其组合，而如果产生的FinFET为p-型FinFET，则富掺杂剂层190中的杂质可为硼、铟或其组合。在一些实施例中，第一器件区I用于形成N-型FinFET，因此富掺杂剂层190中的杂质为磷、砷或其组合。富掺杂剂层190中的杂质的原子百分比可大于约80％、90％、95％或甚至99％，并且实际上可为纯杂质层。
取决于富掺杂剂层190的组成，室310(图18所示)中的工艺气体可包括AsH3、B2H6、PH3、BF3、诸如Xe、Ar、He、Ne、Kr等的稀释气体。将射频(RF)电源320(图18所示)打开以产生等离子体350。例如，RF电源320的功率可在从约50瓦至约1000瓦的范围内，尽管也可使用更大或更小的功率。在一些实施例中，在形成富掺杂剂层190的整个期间将RF电源320持续打开。在一些其他实施例中，如在图19中示意性示出的，使RF电源320脉冲化(处于开和关模式)以提高富掺杂剂层190的一致性(阶梯覆盖性)，其中如图5所示的，富掺杂剂层190的一致性可使用比值T’/T表示，厚度T’为富掺杂剂层190侧壁部分的厚度，厚度T为富掺杂剂层190的顶部的厚度。在一些实施例中，一致性(比值T’/T)可大于约50％。
在富掺杂剂层190的形成期间，或者将图18所示的直流(DC)电源330关闭，或者使其具有低于约1.5kV的较低偏压，使得在富掺杂剂层形成期间没有不需要的无定形化层形成。在一些实施例中，DC电源330的偏压输出在从约0kV至约1.5kV的范围内。较低或甚至零的DC偏压可降低形成工艺的定向性，因此可将富掺杂剂层190作为单独的层沉积在密封间隔件170上方。在富掺杂剂层190的形成期间由DC电源330提供的DC偏压也可为脉冲的(打开和关闭)，如图19示意性示出的。
参考图6，实施撞击注入(knock-on implantation)以撞击富掺杂剂层190中的杂质进入密封间隔件170、栅极介电层150和/或半导体鳍130中。撞击注入中使用的离子可包括诸如Xe、Ar、Ne、He、Kr或其组合的惰性气体离子，或对产生的鳍式场效应晶体管(FinFET)的特征没有不利影响的其他离子。在一些实施例中，撞击注入通过惰性气体离子的散射诱导。此外，可通过如图18所示的装置300实施撞击注入和等离子体离子辅助沉积(PIAD)。在一些实施例中，可认为PIAD和撞击注入是沉积和离子模式的等离子体掺杂(PLAD)工艺。
参考图7，在如图6所示的撞击注入后，可在富掺杂剂层190上形成覆盖层200。在随后的退火工艺期间，覆盖层200可防止杂质从富掺杂剂层190外扩散。覆盖层200由诸如氮化硅(Si3N4)、碳氮氧化硅(SiCON)、碳氮化硅(SiCN)或其组合的介电材料制成。在一些实施例中，覆盖层200可为偏置(offset)或伪间隔件电介质。覆盖层200具有从约0.5nm至约10nm的范围内的厚度。例如，通过化学气相沉积(CVD)形成覆盖层200。
参考图8，在将晶圆100退火前，例如，通过等离子体灰化或剥离将光刻胶180从晶圆100中去除。等离子体灰化使用等离子体源以产生诸如氧或氟的单原子活性物质。活性物质与光刻胶180结合以形成灰，使用真空泵去除灰。剥离使用诸如丙酮或苯酚溶剂的光刻胶剥离剂以从晶圆100中去除光刻胶180。
参考图9，富掺杂剂层190、密封间隔件170和/或栅极介电层150中的杂质通过固相扩散(SPD)驱动的退火工艺扩散至半导体鳍130中以形成轻掺杂漏极(LDD)区135。可在去除光刻胶180后实施SPD驱动的退火工艺，使得退火工艺可在高温下进行较长一段时间(例如，从约1秒至约10秒的范围内)，温度例如在从约950℃至1050℃的范围内。例如，退火工艺可为尖峰退火。可选地，光刻胶180(图5至图7中所示)可由可耐受退火工艺的高温的硬掩模代替。在一些实施例中，硬掩模可由氮化硅、氮氧化硅或其组合制成。因此，可在去除硬掩模之前实施退火工艺。这些实施例的剩余工艺可与如图5至图7中所示的基本上相同，因此在本文不重复描述。
在实施例中，通过实施富掺杂剂层190，然后驱使杂质进入半导体鳍130，杂质可在半导体鳍130的顶面132和侧壁134中到达期望的深度而无需考虑遮蔽效应(shadowing effect)和/或等离子体鞘层效应，甚至在半导体鳍130和140彼此间隔开纳米尺度的距离时。因此，可在半导体鳍130的顶面132和侧壁134中形成轻掺杂漏极(LDD)区135。
从结构的观点来看，轻掺杂漏极(LDD)区135和覆盖LDD区135的密封间隔件170可掺杂基本上相同类型的杂质，和/或LDD区135和覆盖LDD区135的栅极介电层150也可掺杂基本上相同类型的杂质。由于通过覆盖LDD区135的密封间隔件170和/或栅极介电层150驱使杂质进入LDD区135中，覆盖LDD区135的密封间隔件170和/或栅极介电层150中残留的杂质和驱至LDD区135中的杂质可为基本上相同的类型。
参考图10，形成光刻胶210并将其图案化以覆盖第一器件区I，同时保持第二器件区II未覆盖。具体地，例如，通过旋转涂覆将光刻胶210施加在晶圆100上。然后，预烘焙光刻胶210以驱除过量的光刻胶溶剂。在预烘焙后，将光刻胶210暴露于强光的图案。暴露于光引起化学变化，该化学变化使一些光刻胶180可溶于显影剂。可在显影之前实施曝光后烘焙(PEB)以帮助减少驻波现象，驻波现象由入射光的破坏性和建设性干涉图案所致。然后，将显影剂施加在光刻胶210上以去除一些可溶于显影剂的光刻胶210。然后，硬烘焙剩余的光刻胶210以固化剩余的光刻胶210。
参考图11和12，可将增强扩散掺杂剂掺杂至第二器件区II中的密封间隔件170和/或栅极介电层150中。增强扩散掺杂剂能够增强杂质的扩散，密封间隔件170和/或栅极介电层150中的杂质将在随后的步骤中扩散至半导体鳍140中。在一些实施例中，第二器件区II用于形成P-型鳍式场效应晶体管(FinFET)，因此在随后的步骤中将扩散至半导体鳍140的杂质可为硼。然而，由氮化物材料、氧化物材料或其组合制成的密封间隔件170和/或栅极介电层150倾向于阻止硼在密封间隔件170和/或栅极介电层150中的扩散。因此，可将增强扩散掺杂剂掺杂至密封间隔件170和/或栅极介电层150中以增强杂质在密封间隔件170和/或栅极介电层150中的扩散。在一些实施例中，例如，增强扩散掺杂剂为氟。
在一些实施例中，如讨论的，增强扩散掺杂剂的掺杂可使用基本上相同的工艺(包括等离子体离子辅助沉积(PIAD)和撞击注入工艺)，除了增强扩散掺杂剂可为例如氟之外。具体地，如图11所示，通过PIAD在密封间隔件170上形成富增强扩散掺杂剂层215。如图12所示，实施撞击注入以撞击富增强扩散掺杂剂层215中的增强扩散掺杂剂进入密封间隔件170和/或栅极介电层150中。撞击注入中使用的离子可包括诸如Xe、Ar、Ne、He、Kr或其组合的惰性气体离子，或对产生的鳍式场效应晶体管(FinFET)的特征没有不利影响的其他离子。在一些实施例中，撞击注入由惰性气体离子的散射诱导。
参考图13，在富增强扩散掺杂剂层215上形成富掺杂剂层220。可通过等离子体离子辅助沉积(PIAD)形成富掺杂剂层220。富掺杂剂层220的形成可使用与富掺杂剂层170的形成基本上相同的工艺，除了富掺杂剂层220可能具有与富掺杂剂层170不同类型的杂质之外，因此在本文不重复描述。
参考图14，实施撞击注入以撞击富掺杂剂层220中的杂质进入富增强扩散掺杂剂层215、密封间隔件170、栅极介电层150和/或半导体鳍140中。撞击注入中使用的离子可包括诸如Xe、Ar、Ne、He、Kr或其组合的惰性气体离子，或对产生的鳍式场效应晶体管(FinFET)的特征没有不利影响的其他离子。在一些实施例中，撞击注入由惰性气体离子的散射诱导。图14所示的撞击注入可与图6所示的撞击注入基本上相同，除了富掺杂剂层220可能具有与富掺杂剂层170不同类型的杂质之外，因此在本文不重复描述。
参考图15，在如图14所示的撞击注入后，可在富掺杂剂层220上形成覆盖层230。在随后的退火工艺期间，覆盖层230可防止杂质从富掺杂剂层220外扩散。覆盖层230由诸如氮化硅(Si3N4)、碳氮氧化硅(SiCON)、碳氮化硅(SiCN)或其组合的介电材料制成。在一些实施例中，覆盖层230可为偏置(offset)或伪间隔件电介质。覆盖层230具有从约0.5nm至约10nm的范围内的厚度。例如，通过化学气相沉积(CVD)形成覆盖层230。
参考图16，在将晶圆100退火前，通过例如等离子体灰化或剥离将光刻胶210从晶圆100中去除。等离子体灰化使用等离子体源以产生诸如氧或氟的单原子活性物质。活性物质与光刻胶210结合以形成灰，使用真空泵去除灰。剥离使用诸如丙酮或苯酚溶剂的光刻胶剥离剂以从晶圆100中去除光刻胶210。
参考图17，富掺杂剂层220、富增强扩散掺杂剂层215、密封间隔件170和/或栅极介电层150中的杂质通过固相扩散(SPD)驱动的退火工艺扩散至半导体鳍140中以形成轻掺杂漏极(LDD)区145。可在去除光刻胶210后实施SPD驱动的退火工艺，使得退火工艺可在高温下进行较长一段时间(例如，从约1秒至约10秒的范围内)，温度例如在从约950℃至1050℃的范围内。例如，退火工艺可为尖峰退火或浸泡退火。在一些实施例中，图17所示的退火工艺可具有比图9所示的退火工艺更大的热预算。可选地，光刻胶210(图10至图15所示)可由可耐受退火工艺的高温的硬掩模代替。在一些实施例中，硬掩模可由氮化硅、氮氧化硅或其组合制成。因此，可在去除硬掩模之前实施退火工艺。这些实施例的剩余工艺可与图10至图15中所示的基本上相同，因此在本文不重复描述。
在一些实施例中，当扩散至半导体鳍140中的杂质为硼时，可在O2环境中实施退火工艺。由氮化物材料、氧化物材料或其组合制成的密封间隔件170和/或栅极介电层150倾向于阻止硼在密封间隔件170和/或栅极介电层150中的扩散。因此，可在O2环境中实施退火工艺以增强硼在密封间隔件170和/或栅极介电层150中的扩散。
在实施例中，通过形成富掺杂剂层220，然后驱使杂质进入半导体鳍140，杂质可在半导体鳍140的顶面142和侧壁144中到达期望的深度而无需考虑遮蔽效应(shadowing effect)和/或等离子体鞘层效应，甚至在半导体鳍130和140彼此间隔开纳米尺度的距离时。因此，可在半导体鳍140的顶面142和侧壁144中形成轻掺杂漏极(LDD)区145。
从结构的观点来看，轻掺杂漏极(LDD)区145和覆盖LDD区145的密封间隔件170可掺杂基本上相同类型的杂质，和/或LDD区145和覆盖LDD区145的栅极介电层150也可掺杂基本上相同类型的杂质。由于通过覆盖LDD区145的密封间隔件170和/或栅极介电层150将杂质驱至LDD区145中，覆盖LDD区145的密封间隔件170和/或栅极介电层150中残留的杂质和驱至LDD区145中的杂质可具有基本上相同的类型。
应当理解，对于上文所示实施例，可实施额外工艺以完成半导体器件的制造。例如，这些额外工艺可包括源极/漏极外延循环、接触件的形成、互连结构的形成(例如，提供半导体器件的电互连的线和通孔、金属层和层间电介质)、钝化层的形成和半导体器件的封装。
为了在半导体鳍的顶面和侧壁中形成轻掺杂漏极(LDD)区而无需考虑遮蔽效应和/或等离子体鞘层效应，在实施例中，实施间接等离子体掺杂(PLAD)工艺。即，形成富掺杂剂层，然后将富掺杂剂层中的杂质驱至半导体鳍中。通过实施PLAD工艺，杂质可在半导体鳍的顶面和侧壁中到达期望的深度而无需考虑遮蔽效应和/或等离子体鞘层效应。
根据一些实施例，半导体结构包括衬底、第一半导体鳍、第二半导体鳍和第一轻掺杂漏极(LDD)区。第一半导体鳍设置在衬底上。第一半导体鳍具有顶面和侧壁。第二半导体鳍设置在衬底上。第一半导体鳍和第二半导体鳍彼此间隔开纳米尺度的距离。第一轻掺杂漏极(LDD)区至少设置在第一半导体鳍的顶面和侧壁中。
在上述半导体结构中，还包括：至少覆盖所述第一轻掺杂漏极(LDD)区的密封间隔件。
在上述半导体结构中，还包括：至少覆盖所述第一轻掺杂漏极(LDD)区的密封间隔件，其中，所述第一轻掺杂漏极(LDD)区和所述密封间隔件掺杂基本上相同类型的杂质。
在上述半导体结构中，还包括：至少覆盖所述第一轻掺杂漏极(LDD)区的栅极介电层。
在上述半导体结构中，还包括：至少覆盖所述第一轻掺杂漏极(LDD)区的栅极介电层，其中，所述第一轻掺杂漏极(LDD)区和所述栅极介电层掺杂基本上相同类型的杂质。
在上述半导体结构中，其中，所述第二半导体鳍具有顶面和侧壁；并且还包括：第二轻掺杂漏极(LDD)区，至少设置在所述第二半导体鳍的顶面和侧壁中，其中，所述第一LDD区和所述第二LDD区掺杂不同类型的杂质。
根据一些实施例，提供了制造半导体结构的方法。所述方法包括在衬底上形成至少一个半导体鳍，其中半导体鳍具有顶面和侧壁；在半导体鳍的顶面和侧壁上形成至少一个介电层；在介电层上形成包含至少一种杂质的富掺杂剂层；以及驱使杂质通过介电层进入半导体鳍中。
在上述方法中，其中，所述驱使包括：实施撞击注入以撞击所述杂质进入所述介电层中。
在上述方法中，其中，所述驱使包括：实施撞击注入以撞击所述杂质进入所述介电层中，其中，使用至少一种惰性气体离子实施所述撞击注入。
在上述方法中，还包括：在所述驱使之前将至少一种增强扩散掺杂剂注入所述介电层中，其中，所述增强扩散掺杂剂能够增强所述杂质在所述介电层中的扩散。
在上述方法中，还包括：在所述驱使之前将至少一种增强扩散掺杂剂注入所述介电层中，其中，所述增强扩散掺杂剂能够增强所述杂质在所述介电层中的扩散，其中，所述增强扩散掺杂剂为氟。
在上述方法中，其中，所述驱使包括：实施退火工艺以将所述杂质驱至所述半导体鳍中。
在上述方法中，其中，所述驱使包括：实施退火工艺以将所述杂质驱至所述半导体鳍中，所述方法还包括：在所述退火工艺之前在所述富掺杂剂层上形成覆盖层。
在上述方法中，其中，所述驱使包括：实施退火工艺以将所述杂质驱至所述半导体鳍中，其中，在O2环境中实施所述退火工艺。
在上述方法中，其中，形成所述介电层包括：在所述半导体鳍的顶面和侧壁上形成栅极介电层。
在上述方法中，其中，形成所述介电层包括：至少在所述半导体鳍的顶面和侧壁上形成密封间隔件。
在上述方法中，其中，通过等离子体离子辅助沉积(PIAD)形成所述富掺杂剂层。
根据一些实施例，提供了制造半导体结构的方法。所述方法包括在衬底上形成至少一个第一半导体鳍和至少一个第二半导体鳍，其中第一半导体鳍具有顶面和侧壁；在第一半导体鳍的顶面和侧壁上形成至少一个第一介电层；形成第一光刻胶以覆盖第二半导体鳍，第一介电层未被覆盖；将至少一种第一杂质注入第一介电层中；去除第一光刻胶；以及将第一杂质驱至第一半导体鳍中。
在上述方法中，其中，所述第二半导体鳍具有顶面和侧壁；其中，形成所述第一介电层还在所述第二半导体鳍的顶面和侧壁上形成至少一个第二介电层；所述方法还包括：形成第二光刻胶以覆盖所述第一介电层，所述第二介电层未被覆盖；将至少一种第二杂质注入所述第二介电层中，其中，所述第一杂质和所述第二杂质具有不同的类型；去除所述第二光刻胶；以及将所述第二杂质驱至所述第二半导体鳍中。
在上述方法中，其中，所述注入包括等离子体掺杂工艺。
上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本公开的各个方面。本领域技术人员应当理解他们可容易地使用本公开作为基础来设计或修改其他工艺和结构以进行与本文介绍的实施例相同的目的和/或实现与其相同的优势。本领域技术人员还应认识到这种等同结构并不背离本公开的实质和范围，并且应认识到在不背离本公开实质和范围的情况下他们可对本文进行多种改变、替换和修改。

Claims (10)

1.一种半导体结构，包括：
衬底；
第一半导体鳍，设置在所述衬底上，其中，所述第一半导体鳍具有顶面和侧壁；
第二半导体鳍，设置在所述衬底上，其中，所述第一半导体鳍和所述第二半导体鳍彼此间隔开纳米尺度的距离；以及
第一轻掺杂漏极(LDD)区，至少设置在所述第一半导体鳍的顶面和侧壁中。
2.根据权利要求1所述的半导体结构，还包括：
至少覆盖所述第一轻掺杂漏极(LDD)区的密封间隔件。
3.根据权利要求2所述的半导体结构，其中，所述第一轻掺杂漏极(LDD)区和所述密封间隔件掺杂基本上相同类型的杂质。
4.根据权利要求1所述的半导体结构，还包括：
至少覆盖所述第一轻掺杂漏极(LDD)区的栅极介电层。
5.根据权利要求4所述的半导体结构，其中，所述第一轻掺杂漏极(LDD)区和所述栅极介电层掺杂基本上相同类型的杂质。
6.根据权利要求1所述的半导体结构，其中，所述第二半导体鳍具有顶面和侧壁；并且
还包括：
第二轻掺杂漏极(LDD)区，至少设置在所述第二半导体鳍的顶面和侧壁中，其中，所述第一LDD区和所述第二LDD区掺杂不同类型的杂质。
7.一种制造半导体结构的方法，所述方法包括：
在衬底上形成至少一个半导体鳍，其中，所述半导体鳍具有顶面和侧壁；
在所述半导体鳍的顶面和侧壁上形成至少一个介电层；
在所述介电层上形成包含至少一种杂质的富掺杂剂层；以及
驱使所述杂质通过所述介电层进入所述半导体鳍中。
8.根据权利要求7所述的方法，其中，所述驱使包括：
实施撞击注入以撞击所述杂质进入所述介电层中。
9.根据权利要求8所述的方法，其中，使用至少一种惰性气体离子实施所述撞击注入。
10.一种制造半导体结构的方法，所述方法包括：
在衬底上形成至少一个第一半导体鳍和至少一个第二半导体鳍，其中，所述第一半导体鳍具有顶面和侧壁；
在所述第一半导体鳍的顶面和侧壁上形成至少一个第一介电层；
形成第一光刻胶以覆盖所述第二半导体鳍，所述第一介电层未被覆盖；
将至少一种第一杂质注入所述第一介电层中；
去除所述第一光刻胶；以及
将所述第一杂质驱至所述第一半导体鳍中。
CN201510979036.3A 2015-04-22 2015-12-23 半导体结构及其制造方法 Active CN106067479B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562151286P 2015-04-22 2015-04-22
US62/151,286 2015-04-22
US14/853,839 US9978866B2 (en) 2015-04-22 2015-09-14 Semiconductor structure and manufacturing method thereof
US14/853,839 2015-09-14

Publications (2)

Publication Number Publication Date
CN106067479A true CN106067479A (zh) 2016-11-02
CN106067479B CN106067479B (zh) 2019-10-15

Family

ID=57110297

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510979036.3A Active CN106067479B (zh) 2015-04-22 2015-12-23 半导体结构及其制造方法

Country Status (5)

Country Link
US (4) US9978866B2 (zh)
KR (1) KR101795875B1 (zh)
CN (1) CN106067479B (zh)
DE (1) DE102015116975B4 (zh)
TW (1) TWI599037B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108074812A (zh) * 2016-11-08 2018-05-25 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的制造方法
CN109585292A (zh) * 2017-09-29 2019-04-05 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9112003B2 (en) 2011-12-09 2015-08-18 Asm International N.V. Selective formation of metallic films on metallic surfaces
TWI686499B (zh) 2014-02-04 2020-03-01 荷蘭商Ａｓｍ Ｉｐ控股公司 金屬、金屬氧化物與介電質的選擇性沉積
US10047435B2 (en) 2014-04-16 2018-08-14 Asm Ip Holding B.V. Dual selective deposition
US20150372107A1 (en) * 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
US9490145B2 (en) 2015-02-23 2016-11-08 Asm Ip Holding B.V. Removal of surface passivation
US10428421B2 (en) 2015-08-03 2019-10-01 Asm Ip Holding B.V. Selective deposition on metal or metallic surfaces relative to dielectric surfaces
US10695794B2 (en) 2015-10-09 2020-06-30 Asm Ip Holding B.V. Vapor phase deposition of organic films
US9837487B2 (en) * 2015-11-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with gate stack
WO2017163438A1 (ja) * 2016-03-24 2017-09-28 東京エレクトロン株式会社 半導体装置の製造方法
US11081342B2 (en) 2016-05-05 2021-08-03 Asm Ip Holding B.V. Selective deposition using hydrophobic precursors
US10373820B2 (en) 2016-06-01 2019-08-06 Asm Ip Holding B.V. Deposition of organic films
US10453701B2 (en) 2016-06-01 2019-10-22 Asm Ip Holding B.V. Deposition of organic films
US10014212B2 (en) * 2016-06-08 2018-07-03 Asm Ip Holding B.V. Selective deposition of metallic films
US10515969B2 (en) * 2016-11-17 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10700181B2 (en) * 2016-11-28 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (finFET) device structure and method for forming the same
US11430656B2 (en) 2016-11-29 2022-08-30 Asm Ip Holding B.V. Deposition of oxide thin films
US11094535B2 (en) 2017-02-14 2021-08-17 Asm Ip Holding B.V. Selective passivation and selective deposition
US11501965B2 (en) 2017-05-05 2022-11-15 Asm Ip Holding B.V. Plasma enhanced deposition processes for controlled formation of metal oxide thin films
CN115233183A (zh) 2017-05-16 2022-10-25 Asm Ip 控股有限公司 电介质上氧化物的选择性peald
TWI729285B (zh) * 2017-06-14 2021-06-01 荷蘭商Ａｓｍ Ｉｐ控股公司 金屬薄膜的選擇性沈積
US10629494B2 (en) * 2017-06-26 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10163657B1 (en) * 2017-08-25 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
JP2020056104A (ja) 2018-10-02 2020-04-09 エーエスエム アイピー ホールディング ビー．ブイ． 選択的パッシベーションおよび選択的堆積
US11965238B2 (en) 2019-04-12 2024-04-23 Asm Ip Holding B.V. Selective deposition of metal oxides on metal surfaces
US11139163B2 (en) 2019-10-31 2021-10-05 Asm Ip Holding B.V. Selective deposition of SiOC thin films
TW202140832A (zh) 2020-03-30 2021-11-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 氧化矽在金屬表面上之選擇性沉積
TW202204658A (zh) 2020-03-30 2022-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 在兩不同表面上同時選擇性沉積兩不同材料
TW202140833A (zh) 2020-03-30 2021-11-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 相對於金屬表面在介電表面上之氧化矽的選擇性沉積
DE102020126060A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Mehrschichtige high-k-gatedielektrikumstruktur

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237278A (zh) * 2010-04-28 2011-11-09 台湾积体电路制造股份有限公司 鳍式场效应晶体管的掺杂方法
US20140377926A1 (en) * 2013-06-21 2014-12-25 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device
US9111962B1 (en) * 2014-03-20 2015-08-18 International Business Machines Corporation Selective dielectric spacer deposition for exposing sidewalls of a finFET
CN105990239A (zh) * 2015-02-06 2016-10-05 联华电子股份有限公司 半导体元件及其制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1892765A1 (en) 2006-08-23 2008-02-27 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Method for doping a fin-based semiconductor device
US8187928B2 (en) * 2010-09-21 2012-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
US8273617B2 (en) * 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8785286B2 (en) * 2010-02-09 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Techniques for FinFET doping
TWI606136B (zh) 2011-11-04 2017-11-21 Ａｓｍ國際股份有限公司 沉積摻雜氧化矽的方法以及用於沉積摻雜氧化矽至基板上的原子層沉積製程
US9318367B2 (en) * 2013-02-27 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structure with different fin heights and method for forming the same
US9362404B2 (en) * 2014-02-21 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Doping for FinFET
US9558946B2 (en) * 2014-10-03 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming FinFETs
US9330982B1 (en) * 2015-08-14 2016-05-03 Globalfoundries Inc. Semiconductor device with diffusion barrier film and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237278A (zh) * 2010-04-28 2011-11-09 台湾积体电路制造股份有限公司 鳍式场效应晶体管的掺杂方法
US20140377926A1 (en) * 2013-06-21 2014-12-25 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device
US9111962B1 (en) * 2014-03-20 2015-08-18 International Business Machines Corporation Selective dielectric spacer deposition for exposing sidewalls of a finFET
CN105990239A (zh) * 2015-02-06 2016-10-05 联华电子股份有限公司 半导体元件及其制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108074812A (zh) * 2016-11-08 2018-05-25 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的制造方法
CN108074812B (zh) * 2016-11-08 2020-07-10 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的制造方法
CN109585292A (zh) * 2017-09-29 2019-04-05 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US11342454B2 (en) 2017-09-29 2022-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Also Published As

Publication number Publication date
US20200152792A1 (en) 2020-05-14
US20220262951A1 (en) 2022-08-18
DE102015116975A1 (de) 2016-10-27
US9978866B2 (en) 2018-05-22
DE102015116975B4 (de) 2022-09-15
US10535768B2 (en) 2020-01-14
KR20160125870A (ko) 2016-11-01
TWI599037B (zh) 2017-09-11
CN106067479B (zh) 2019-10-15
US11355635B2 (en) 2022-06-07
US20180277678A1 (en) 2018-09-27
US20160315191A1 (en) 2016-10-27
TW201639153A (zh) 2016-11-01
KR101795875B1 (ko) 2017-11-08

Similar Documents

Publication Publication Date Title
CN106067479A (zh) 半导体结构及其制造方法
US9450097B2 (en) Methods for doping Fin field-effect transistors and Fin field-effect transistor
US8703593B2 (en) Techniques for FinFET doping
US7446379B2 (en) Transistor with dopant-bearing metal in source and drain
TWI696246B (zh) 控制矽-氧化物-氮化物-氧化物-矽電晶體之阻擋氧化物厚度的方法、製造半導體裝置的方法、半導體裝置以及記憶體裝置
CN104241250B (zh) 用于形成接触件的掺杂保护层
CN109216459A (zh) 用于制造半导体器件的方法
CN103247535A (zh) 用于finfet器件的位错smt
CN101079380A (zh) 半导体结构及其制造方法
CN107919324B (zh) 半导体器件的形成方法
CN104217955B (zh) N型晶体管及其制作方法、互补金属氧化物半导体
CN107785313A (zh) 半导体结构及其形成方法
CN110034067A (zh) 半导体器件及其形成方法
CN109285778B (zh) 半导体器件及其形成方法
CN103107139B (zh) 具有鳍状结构的场效晶体管的结构及其制作方法
CN109148581A (zh) 一种半导体器件的制造方法
CN108281485A (zh) 半导体结构及其形成方法
CN108807268B (zh) 半导体结构及其形成方法
CN104934376B (zh) 一种制作半导体器件的方法
CN103367128A (zh) 超陡倒掺杂沟道的形成方法、半导体器件及其制造方法
CN107045982A (zh) 半导体结构的形成方法
CN104637815B (zh) Mos晶体管及其制备方法
KR100810430B1 (ko) 반도체 소자의 제조 방법
CN108346578A (zh) 一种半导体器件的制造方法
CN108346563A (zh) 一种半导体器件及其制造方法和电子装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant