CN103358410A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
- Publication number
- CN103358410A CN103358410A CN2013101190653A CN201310119065A CN103358410A CN 103358410 A CN103358410 A CN 103358410A CN 2013101190653 A CN2013101190653 A CN 2013101190653A CN 201310119065 A CN201310119065 A CN 201310119065A CN 103358410 A CN103358410 A CN 103358410A
- Authority
- CN
- China
- Prior art keywords
- wafer
- retainer belt
- semiconductor device
- ring
- interarea
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005520 cutting process Methods 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000003014 reinforcing effect Effects 0.000 abstract 3
- 238000002844 melting Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 51
- 238000011900 installation process Methods 0.000 description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 9
- 230000002787 reinforcement Effects 0.000 description 7
- 230000002950 deficient Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000010926 purge Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- QGZKDVFQNNGYKY-AKLPVKDBSA-N Ammonia-N17 Chemical compound [17NH3] QGZKDVFQNNGYKY-AKLPVKDBSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67115—Apparatus for thermal treatment mainly by radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Dicing (AREA)
Abstract
本发明涉及半导体装置的制造方法。得到一种在利用保持带将在主面的中央部设置有多个半导体装置并在主面的外周部设置有环状加强部的晶片安装于切割架时能够对环状加强部的阶梯差无气泡地粘贴保持带的半导体装置的制造方法。首先,将保持带(8)粘贴于晶片(1)的主面。然后,通过将保持带(8)加热至保持带(8)的熔点的0.6倍以上,从而沿着环状加强部(7)的阶梯差粘贴保持带(8)。
Description
技术领域
本发明涉及利用保持带将在主面的中央部设置有多个半导体装置并且在主面的外周部设置有环状加强部的晶片安装于切割架(dicing frame)的方法,特别涉及能够对环状加强部的阶梯差无气泡地粘贴保持带的半导体装置的制造方法。
背景技术
在LSI中,通过三维安装等进行封装的高密度化,薄晶片化发展到在工艺完成时的晶片厚度为10μm左右。
此外,IGBT(绝缘栅型双极晶体管)或MOSFET(MOS型场效应晶体管)等的功率器件作为工业用电动机或汽车用电动机等的变换器电路、大容量服务器的电源装置以及不间断电源装置等的半导体开关而被广泛使用。在功率器件的制造中,为了改善导通特性等的通电性能,将半导体基板加工得较薄。
近年来,为了改善成本方面、特性方面,使用通过FZ(Floating Zone,浮区)法制作的使晶片薄型化到50μm左右的极薄晶片来制造半导体装置。
通常,在晶片的薄型化中,进行利用背面研磨(back grinding)或抛光的机械研磨以及用于除去在机械研磨中产生的加工变形的湿法蚀刻或干法蚀刻。然后,在背面侧通过离子注入或热处理形成扩散层,通过溅射法等形成电极。
在这样的状况中,在晶片的背面加工时的晶片破裂的发生频度变高。因此,提出了将晶片外周部按其原样较厚地保留来作为环状加强部(加强筋(rib)),而仅将晶片中心部加工得较薄的加工方法(例如,参照专利文献1)。通过使用这样的带有加强筋的晶片,从而晶片的翘曲被大幅度地缓和,在处理装置中的晶片输送变得容易,并且,晶片的强度大幅度地提高,在操作时能够减轻晶片的破裂或缺损。
在将芯片单片化时,利用保持带将晶片安装于切割架,之后,利用刀片或激光进行切割。此时,若未对环状加强部的阶梯差充分地粘贴保持片材,则在切割时芯片飞溅,由于飞溅的芯片导致刀片的破损等,使半导体装置的生产变得困难。
为了解决该问题,提出了如下方法:利用与环状加强部的内径匹配地精密调整了的环状凸部来与带有加强筋的晶片的形状匹配地将保持带按压变形,从而使对阶梯差部的粘附性提高(例如,参照专利文献2)。此外,也提出了通过利用压缩空气的导入来将保持带按压变形而使对阶梯差的粘附性提高的方法(例如,参照专利文献3)。
现有技术文献
专利文献
专利文献1:日本特开2007–19379号公报;
专利文献2:日本特开2008–42016号公报;
专利文献3:日本特开2010–118584号公报。
发明要解决的课题
在利用环状凸部与加强筋内径匹配地压入保持带的方法中,由于在研削时的加强筋宽度的偏差或压入位置的偏差而导致存在按压时晶片破裂的问题、在保持带中产生气泡的问题。
在利用压缩空气的导入按压保持带的方法中,由于保持带的刚性导致不能通过压缩空气得到充分的按压,存在保持带中产生气泡的问题。
发明内容
本发明是为了解决上述那样的课题而完成的,其目的在于,得到一种能够对环状加强部的阶梯差无气泡地粘贴保持带的半导体装置的制造方法。
用于解决问题的方案
本发明提供一种半导体装置的制造方法,利用保持带将在主面的中央部设置有多个半导体装置并且在所述主面的外周部设置有环状加强部的晶片安装于切割架,其特征在于,具备:将所述保持带粘贴于所述晶片的所述主面的工序;以及通过将所述保持带加热至所述保持带的熔点的0.6倍以上,从而沿着所述环状加强部的阶梯差粘贴所述保持带的工序。
发明效果
利用本发明,能够对环状加强部的阶梯差无气泡地粘贴保持带。
附图说明
图1是表示本发明实施方式1的安装装置的俯视图。
图2是本发明实施方式1的半导体装置的制造方法的流程图。
图3是表示本发明实施方式1的晶片安装处理部的剖视图。
图4是表示本发明实施方式1的晶片安装处理部的剖视图。
图5是表示本发明实施方式1的晶片安装处理部的剖视图。
图6是表示本发明实施方式1的晶片安装处理部的剖视图。
图7是表示本发明实施方式1的保持带的紧贴不良区域的宽度和加热温度的关系的图。
图8是用保持带的熔点将图7的加热温度进行标准化后的图。
图9是表示本发明实施方式2的晶片安装处理部的剖视图。
图10是表示本发明实施方式3的晶片安装处理部的剖视图。
具体实施方式
参照附图对本发明实施方式的半导体装置的制造方法进行说明。对相同或者对应的结构要素标注相同的附图标记,存在省略重复说明的情况。
实施方式1.
图1是表示本发明实施方式1的安装装置的俯视图。在将带有加强筋的晶片1通过对准部2进行晶片对准等的位置调整之后,通过输送臂4将其输送至晶片安装处理部3。在将带有保持带的切割架5通过对准部2进行位置调整之后,通过输送臂4将其输送至晶片安装处理部3。在晶片安装处理部3将晶片1和带有保持带的切割架5粘合,通过输送臂4收容在晶片收容部6中。
图2是本发明实施方式1的半导体装置的制造方法的流程图。图3至图6是表示本发明实施方式1的晶片安装处理部的剖视图。参照这些图对本发明实施方式1的半导体装置的制造方法进行说明。
在晶片1的主面的中央部设置有MOSFET、IGBT等的多个半导体装置,在主面的外周部设置有环状加强部7,在晶片1的背面设置有扩散层、电极。本实施方式的方法是利用保持带8将这样的带有加强筋的晶片1安装于切割架9的方法。
首先,如图3所示,利用输送臂4将晶片1放置在工作台10上(步骤S1)。然后,利用输送臂4将粘贴了保持带8的切割架9放置在晶片1上(步骤S2)。
接着,如图4所示,上部腔11从上方向下部腔12的方向下降,由上部腔11的O型环13和下部腔12的O型环14夹着保持带8。由上部腔11和保持带8构成上室,由下部腔12和保持带8构成下室。接着,使用真空泵15、16分别将上室和下室真空抽吸至1000Pa以下(步骤S3)。
接着,如图5所示,使真空泵15停止,利用氮气17对上部腔11进行充气,利用下部腔的1000Pa以下的真空和上部腔的大气的压差将保持带8粘贴于晶片1的主面(步骤S4)。然后吹洗下室(步骤S5)。接着,如图6所示,利用灯加热将保持带8加热至保持带8的熔点的0.6倍以上,由此沿着环状加强部7的阶梯差粘贴保持带8(步骤S6)。再有,如图2的流程图所示,存在改变了步骤S4~S6的保持带8的加热或充气的顺序的3种方法。
接着,利用输送臂4取出晶片1,并收容至晶片收容部6中(步骤S7)。进而,通过使用了刀片或激光的切割加工,除去环状加强部7,然后分割成各个半导体装置。
在此,图7是表示本发明实施方式1中的保持带的紧贴不良区域的宽度和加热温度的关系的图。横轴是通过加热用灯18进行加热的晶片的实测温度。纵轴是以该温度进行了1分钟的处理之后的紧贴不良区域的宽度w(参照图5)。根据该数据可知,通过使加热温度为60℃以上,从而能够大幅度地减少紧贴不良区域宽度。
图8是用保持带的熔点将图7的加热温度进行标准化的图。以作为聚丙烯类保持带的熔点的130℃将加热温度进行标准化。根据该数据可知,通过使加热温度为保持带8的熔点的0.6倍以上,从而能够大幅度地减少紧贴不良区域宽度。再有,虽然存在改变了步骤S4~S6的顺序的3种方法,但是在本次评价中,用哪种方法都未在紧贴不良区域的宽度方面发现差异。
在本实施方式中,通过将保持带8加热至保持带8的熔点的0.6倍以上,从而保持带8变得柔软,因此,能够对环状加强部7的阶梯差无气泡地粘贴保持带8。
此外,在本实施方式中,通过灯加热来加热保持带8。只要是灯加热,则有能够在真空中进行加热的优点。
此外,在本实施方式中,利用1000Pa以下的真空和大气的压差,将保持带8粘贴于晶片1的主面。由于利用该压差将保持带8和晶片1紧贴,所以保持带8的粘贴变得容易。
实施方式2.
图9是表示本发明实施方式2的晶片安装处理部的剖视图。参照这些图对本发明实施方式2的半导体装置的制造方法进行说明。
首先,与实施方式1同样地执行到步骤S3。接着,使真空泵15停止,以利用氮气加热用加热器19加热至高温的氮气17对上部腔11进行充气,利用下部腔和上部腔的压差将保持带8粘贴于晶片1的主面。此时,利用加热后的氮气17使保持带8热变形,由此,沿着环状加强部7的阶梯差粘贴保持带8。然后吹洗下室。
像这样使用由氮气加热用加热器19加热至高温的氮气来加热保持带8,也能得到与实施方式1相同的效果。
实施方式3.
图10是表示本发明实施方式3的晶片安装处理部的剖视图。参照这些图对本发明的实施方式3的半导体装置的制造方法进行说明。
首先,与实施方式1同样地执行到步骤S5。接着,使用工作台加热用加热器20经由晶片1加热保持带8,沿着环状加强部7的阶梯差粘贴保持带8。然后吹洗下室。
像这样使用晶片工作台加热用加热器20来加热保持带8,也能够得到与实施方式1相同的效果。
附图标记的说明:
1 晶片;
7 环状加强部;
8 保持带;
9 切割架。
Claims (3)
1.一种半导体装置的制造方法,利用保持带将在主面的中央部设置有多个半导体装置并且在所述主面的外周部设置有环状加强部的晶片安装于切割架,其特征在于,具备:
将所述保持带粘贴于所述晶片的所述主面的工序;以及
通过将所述保持带加热至所述保持带的熔点的0.6倍以上,从而沿着所述环状加强部的阶梯差粘贴所述保持带的工序。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,通过灯加热来加热所述保持带。
3.根据权利要求1或2所述的半导体装置的制造方法,其特征在于,利用1000Pa以下的真空和大气的压差将所述保持带粘贴于所述晶片的所述主面。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012088437A JP5895676B2 (ja) | 2012-04-09 | 2012-04-09 | 半導体装置の製造方法 |
JP2012-088437 | 2012-04-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103358410A true CN103358410A (zh) | 2013-10-23 |
CN103358410B CN103358410B (zh) | 2016-03-02 |
Family
ID=49210070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310119065.3A Active CN103358410B (zh) | 2012-04-09 | 2013-04-08 | 半导体装置的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9324581B2 (zh) |
JP (1) | JP5895676B2 (zh) |
KR (1) | KR101475384B1 (zh) |
CN (1) | CN103358410B (zh) |
DE (1) | DE102013205126B4 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110335825A (zh) * | 2019-05-29 | 2019-10-15 | 宁波芯健半导体有限公司 | 一种晶圆级芯片封装方法 |
CN110391162A (zh) * | 2018-04-19 | 2019-10-29 | 株式会社迪思科 | 搬送机构 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5772092B2 (ja) * | 2011-03-11 | 2015-09-02 | 富士電機株式会社 | 半導体製造方法および半導体製造装置 |
US9583364B2 (en) * | 2012-12-31 | 2017-02-28 | Sunedison Semiconductor Limited (Uen201334164H) | Processes and apparatus for preparing heterostructures with reduced strain by radial compression |
JP2019212786A (ja) * | 2018-06-06 | 2019-12-12 | 株式会社ディスコ | ウェーハの加工方法 |
JP2019212788A (ja) * | 2018-06-06 | 2019-12-12 | 株式会社ディスコ | ウェーハの加工方法 |
JP2019212787A (ja) * | 2018-06-06 | 2019-12-12 | 株式会社ディスコ | ウェーハの加工方法 |
JP2019212785A (ja) * | 2018-06-06 | 2019-12-12 | 株式会社ディスコ | ウェーハの加工方法 |
JP7039135B2 (ja) * | 2018-06-06 | 2022-03-22 | 株式会社ディスコ | ウェーハの加工方法 |
JP7039136B2 (ja) * | 2018-06-06 | 2022-03-22 | 株式会社ディスコ | ウェーハの加工方法 |
JP2019220550A (ja) * | 2018-06-19 | 2019-12-26 | 株式会社ディスコ | ウエーハの加工方法 |
JP2020009871A (ja) * | 2018-07-06 | 2020-01-16 | 株式会社ディスコ | ウェーハの加工方法 |
JP2020009873A (ja) * | 2018-07-06 | 2020-01-16 | 株式会社ディスコ | ウェーハの加工方法 |
JP2020024967A (ja) * | 2018-08-06 | 2020-02-13 | 株式会社ディスコ | ウェーハの加工方法 |
JP2020024968A (ja) * | 2018-08-06 | 2020-02-13 | 株式会社ディスコ | ウェーハの加工方法 |
JP7191458B2 (ja) * | 2018-08-06 | 2022-12-19 | 株式会社ディスコ | ウェーハの加工方法 |
JP2020031183A (ja) * | 2018-08-24 | 2020-02-27 | 株式会社ディスコ | ウエーハの保護方法、保護部材、及び保護部材生成方法 |
JP7173792B2 (ja) * | 2018-08-28 | 2022-11-16 | 株式会社ディスコ | ウエーハの保護方法 |
JP7175568B2 (ja) * | 2018-10-17 | 2022-11-21 | 株式会社ディスコ | ウェーハの加工方法 |
JP7175569B2 (ja) * | 2018-10-17 | 2022-11-21 | 株式会社ディスコ | ウェーハの加工方法 |
JP7204294B2 (ja) * | 2018-10-17 | 2023-01-16 | 株式会社ディスコ | ウェーハの加工方法 |
JP7204296B2 (ja) * | 2018-10-17 | 2023-01-16 | 株式会社ディスコ | ウェーハの加工方法 |
JP7175570B2 (ja) * | 2018-10-17 | 2022-11-21 | 株式会社ディスコ | ウェーハの加工方法 |
JP7204295B2 (ja) * | 2018-10-17 | 2023-01-16 | 株式会社ディスコ | ウェーハの加工方法 |
JP6653032B2 (ja) * | 2019-01-29 | 2020-02-26 | 日東電工株式会社 | 半導体ウエハのマウント方法および半導体ウエハのマウント装置 |
JP2021064627A (ja) * | 2019-10-10 | 2021-04-22 | 株式会社ディスコ | ウェーハの加工方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1144396A (zh) * | 1995-06-14 | 1997-03-05 | 三菱电机株式会社 | 半导体器件的制造方法和半导体器件 |
JP2005317570A (ja) * | 2004-04-26 | 2005-11-10 | Fuji Electric Device Technology Co Ltd | 半導体素子の製造方法 |
JP2007311570A (ja) * | 2006-05-18 | 2007-11-29 | Lintec Corp | 貼替装置および貼替方法 |
CN101620986A (zh) * | 2008-07-03 | 2010-01-06 | 株式会社迪思科 | 粘接带的粘贴方法 |
JP2012038879A (ja) * | 2010-08-06 | 2012-02-23 | Lintec Corp | シート貼付装置及び貼付方法 |
WO2012026275A1 (ja) * | 2010-08-26 | 2012-03-01 | リンテック株式会社 | シート貼付装置および貼付方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2712521C2 (de) * | 1977-03-22 | 1987-03-05 | Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen | Verfahren zum Aufkitten von Scheiben |
JPH0254564A (ja) | 1988-08-18 | 1990-02-23 | Nec Corp | 半導体ウェハースの粘着テープ貼付け装置 |
JPH0737768A (ja) * | 1992-11-26 | 1995-02-07 | Sumitomo Electric Ind Ltd | 半導体ウェハの補強方法及び補強された半導体ウェハ |
JP4780828B2 (ja) * | 2000-11-22 | 2011-09-28 | 三井化学株式会社 | ウエハ加工用粘着テープ及びその製造方法並びに使用方法 |
JP2004022784A (ja) * | 2002-06-17 | 2004-01-22 | Nitto Denko Corp | ウエハ加工用粘着シート |
JP4239974B2 (ja) * | 2002-06-25 | 2009-03-18 | サンケン電気株式会社 | 半導体素子の製造方法およびリング状補強部材 |
JP5313973B2 (ja) * | 2003-08-08 | 2013-10-09 | 有限会社都波岐精工 | テープ接着装置およびテープ接着方法 |
JP4738758B2 (ja) | 2003-08-08 | 2011-08-03 | 有限会社都波岐精工 | テープ接着装置およびテープ接着方法 |
CN100440474C (zh) | 2004-05-25 | 2008-12-03 | 有限会社都波岐精工 | 胶带粘结装置 |
JP2007019379A (ja) | 2005-07-11 | 2007-01-25 | Disco Abrasive Syst Ltd | ウェーハの加工方法 |
JP4637692B2 (ja) | 2005-09-07 | 2011-02-23 | 株式会社ディスコ | 粘着フィルム貼着装置 |
JP2007258437A (ja) * | 2006-03-23 | 2007-10-04 | Nippon Steel Chem Co Ltd | ダイボンドダイシング積層フィルム |
JP4796430B2 (ja) * | 2006-04-19 | 2011-10-19 | 株式会社ディスコ | 保護テープ貼着方法 |
JP4841355B2 (ja) * | 2006-08-08 | 2011-12-21 | 日東電工株式会社 | 半導体ウエハの保持方法 |
JP2008085148A (ja) | 2006-09-28 | 2008-04-10 | Tokyo Seimitsu Co Ltd | 接着剤フィルムの接着力発現方法および接着力発現装置 |
US20080242052A1 (en) * | 2007-03-30 | 2008-10-02 | Tao Feng | Method of forming ultra thin chips of power devices |
JP2009064801A (ja) * | 2007-09-04 | 2009-03-26 | Disco Abrasive Syst Ltd | ウエーハ |
JP5317267B2 (ja) * | 2008-11-14 | 2013-10-16 | 株式会社タカトリ | ウエハのマウント装置 |
KR20100117859A (ko) | 2009-04-27 | 2010-11-04 | 주식회사 휘닉스 디지탈테크 | 웨이퍼 마운팅 장치 및 방법소스 |
JP5542582B2 (ja) | 2010-08-26 | 2014-07-09 | リンテック株式会社 | シート貼付装置および貼付方法 |
JP5689269B2 (ja) * | 2010-09-16 | 2015-03-25 | 日東電工株式会社 | 粘着テープ |
JP2012088437A (ja) | 2010-10-18 | 2012-05-10 | Sumitomo Electric Ind Ltd | 光ファイバ接続器 |
US8785296B2 (en) * | 2012-02-14 | 2014-07-22 | Alpha & Omega Semiconductor, Inc. | Packaging method with backside wafer dicing |
JP5981154B2 (ja) * | 2012-02-02 | 2016-08-31 | 三菱電機株式会社 | 半導体装置の製造方法 |
-
2012
- 2012-04-09 JP JP2012088437A patent/JP5895676B2/ja active Active
-
2013
- 2013-01-11 US US13/739,946 patent/US9324581B2/en active Active
- 2013-03-21 KR KR1020130030099A patent/KR101475384B1/ko active IP Right Grant
- 2013-03-22 DE DE102013205126.3A patent/DE102013205126B4/de active Active
- 2013-04-08 CN CN201310119065.3A patent/CN103358410B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1144396A (zh) * | 1995-06-14 | 1997-03-05 | 三菱电机株式会社 | 半导体器件的制造方法和半导体器件 |
JP2005317570A (ja) * | 2004-04-26 | 2005-11-10 | Fuji Electric Device Technology Co Ltd | 半導体素子の製造方法 |
JP2007311570A (ja) * | 2006-05-18 | 2007-11-29 | Lintec Corp | 貼替装置および貼替方法 |
CN101620986A (zh) * | 2008-07-03 | 2010-01-06 | 株式会社迪思科 | 粘接带的粘贴方法 |
JP2012038879A (ja) * | 2010-08-06 | 2012-02-23 | Lintec Corp | シート貼付装置及び貼付方法 |
WO2012026275A1 (ja) * | 2010-08-26 | 2012-03-01 | リンテック株式会社 | シート貼付装置および貼付方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110391162A (zh) * | 2018-04-19 | 2019-10-29 | 株式会社迪思科 | 搬送机构 |
CN110335825A (zh) * | 2019-05-29 | 2019-10-15 | 宁波芯健半导体有限公司 | 一种晶圆级芯片封装方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2013219175A (ja) | 2013-10-24 |
JP5895676B2 (ja) | 2016-03-30 |
KR20130114610A (ko) | 2013-10-18 |
DE102013205126B4 (de) | 2023-08-03 |
US9324581B2 (en) | 2016-04-26 |
US20130267065A1 (en) | 2013-10-10 |
KR101475384B1 (ko) | 2014-12-22 |
CN103358410B (zh) | 2016-03-02 |
DE102013205126A1 (de) | 2013-10-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103358410B (zh) | 半导体装置的制造方法 | |
TWI609418B (zh) | 半導體元件之製造方法以及晶圓安裝裝置 | |
TWI553721B (zh) | 擴展方法、以及半導體裝置的製造方法 | |
JP4574251B2 (ja) | 半導体装置の製造方法 | |
CN103295892B (zh) | 半导体装置的制造方法 | |
TW202007742A (zh) | 晶圓加工方法 | |
CN110491783B (zh) | 晶片的加工方法 | |
CN109599352B (zh) | 带扩展装置和带扩展方法 | |
KR20190143359A (ko) | 웨이퍼의 가공 방법 | |
KR20130090827A (ko) | 기판 반송 방법 및 기판 반송 장치 | |
CN104221131A (zh) | 半导体元件的制造方法 | |
CN110571132B (zh) | 晶片的加工方法 | |
CN110690111A (zh) | 晶片的加工方法 | |
JP4306359B2 (ja) | エキスパンド方法 | |
CN110808226B (zh) | 晶片的加工方法 | |
KR102351927B1 (ko) | 브레이크 장치 및 브레이크 장치에 있어서의 취성 재료 기판의 분단 방법 | |
CN110571133A (zh) | 晶片的加工方法 | |
CN103579127B (zh) | 硅片的键合方法 | |
US20080257474A1 (en) | Adhesive film bonding method | |
KR20200042847A (ko) | 웨이퍼의 가공 방법 | |
KR20200028833A (ko) | 웨이퍼의 가공 방법 | |
CN110880479A (zh) | 晶片的加工方法 | |
CN111063608A (zh) | 晶片的加工方法 | |
US20230154782A1 (en) | Tape pressure bonding apparatus | |
KR102658985B1 (ko) | 본딩 헤드 및 이를 포함하는 다이 본딩 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |