CN103295997A - 用于芯片尺寸封装的电连接件 - Google Patents

用于芯片尺寸封装的电连接件 Download PDF

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Publication number
CN103295997A
CN103295997A CN2012102727990A CN201210272799A CN103295997A CN 103295997 A CN103295997 A CN 103295997A CN 2012102727990 A CN2012102727990 A CN 2012102727990A CN 201210272799 A CN201210272799 A CN 201210272799A CN 103295997 A CN103295997 A CN 103295997A
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opening
size
substrate
semiconductor device
passivation layer
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CN103295997B (zh
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陈宪伟
梁世纬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种用于芯片尺寸封装的电连接件。在一个实施例中，半导体器件包括设置在衬底上方的后钝化层，衬底具有热膨胀系数失配的第一方向。半导体器件包括穿过后钝化层的第一开口，第一开口包括多个细长孔隙。多个细长孔隙中的最长孔隙包括第一尺寸，其中，第一尺寸基本上与热膨胀系数失配的第一方向垂直对准。

Description

用于芯片尺寸封装的电连接件
相关申请的交叉参考
本申请涉及于2011年10月7日提交的名称为“Electrical Connection forChip Scale Packaging”的共同待决的和共同转让的专利申请第13/269,310号，本申请的全部内容结合于此作为参考。
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及半导体器件。
背景技术
作为实例，半导体器件在多种电子应用中使用，诸如个人计算机、手机、数码相机以及其他电子设备。通常通过在半导体衬底上方顺序沉积绝缘层或介电层、导电层以及半导体材料层，并且使用光刻图案化各种材料层以在其上形成电路部件和元件来制造半导体器件。半导体工业继续通过不断减小最小部件尺寸来改进多种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这使得更多部件集成在给定区域中。在一些应用中，这些较小电子部件还需要利用面积比过去的封装件小的较小封装件。
已经开发的用于半导体器件的一种较小封装是晶圆级封装(WLP)，其中，集成电路管芯被封装在封装件中，该封装件通常包括再分布层(RDL)，该再分布层用于扇出(fan out)用于集成电路管芯的接触焊盘的布线，使得可以以比管芯的接触焊盘更大的间距制造电接触件。另一种用于半导体器件的封装被称为铜柱导线直连(BOT)封装。焊料凸块形成在半导体晶圆的管芯上方，并且切割管芯。使用焊料回流工艺将管芯或“倒装芯片”附接或焊接至BOT封装件上的导线。
通常，半导体管芯可以通过利用焊料凸块的封装类型连接至半导体管芯外部的其他器件。可以通过最初在半导体管芯上方形成底部接触金属化层(layer of undercontact metallization)然后将焊料置于底部接触金属化层上来形成焊料凸块。在放置焊料之后，可以实施回流工艺以使焊料形成期望的凸块形状。然后，焊料凸块可以放置在与外部设备的物理接触件中，并且可以实施另一个回流操作，以使焊料凸块与外部设备接合。以这种方式，可以在半导体管芯和外部设备(诸如印刷电路板、另一半导体管芯等)之间进行物理和电连接。
然而，包括底部接触金属化层的材料仅是置于多种不同材料(诸如介电材料、金属化材料、蚀刻停止材料、阻挡层材料和在形成半导体管芯期间利用的其他材料)的叠层上方的多种类型的材料中的一种。这些不同材料中的每一种都可以具有不同于其他材料的唯一热膨胀系数。如果半导体管芯经受高温，则这种类型的热膨胀系数失配会引起问题。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：后钝化层，设置在衬底上方，所述衬底具有热膨胀系数失配的第一方向；以及第一开口，穿过所述后钝化层，所述第一开口包括多个细长孔隙，所述多个细长孔隙中的最长孔隙包括第一尺寸，其中，所述第一尺寸基本上与所述热膨胀系数失配的第一方向垂直对准。
该半导体器件进一步包括：底部接触金属化层，延伸穿过所述第一开口的多个细长孔隙。
该半导体器件进一步包括：穿过所述后钝化层的第二开口，所述第二开口基本上为圆形。
在该半导体器件中，所述第一开口沿着所述衬底的边缘进行定位。
在该半导体器件中，所述第一开口位于所述衬底的角部区域处，并且所述第二开口沿着所述衬底的边缘进行定位。
在该半导体器件中，所述第二开口位于所述衬底的内部区域内。
在该半导体器件中，横跨所述第一开口的多个细长孔隙的间距包括第二尺寸，所述第二尺寸小于所述第一尺寸。
该半导体器件进一步包括：穿过所述后钝化层的第二开口，所述第二开口包括多个第二细长孔隙，所述多个第二细长孔隙中的最长孔隙包括第三尺寸，横跨所述多个第二细长孔隙的间距包括小于所述第三尺寸的第四尺寸，其中，所述第三尺寸基本上与所述衬底的热膨胀系数失配的第二方向垂直对准。
根据本发明的另一方面，提供了一种半导体器件包括：介电层，设置在衬底上方；第一开口，穿过所述介电层，所述第一开口包括多个细长孔隙，所述多个细长孔隙的最长孔隙包括第一尺寸，横跨所述多个细长孔隙的间距包括小于所述第一尺寸的第二尺寸，其中，所述第一尺寸基本上与在所述衬底的中心和所述第一开口的多个细长孔隙的中心之间延伸的第一线垂直对准；以及底部接触金属化层，延伸至所述第一开口的所述多个细长孔隙中。
该半导体器件进一步包括：设置在所述衬底的表面上方的多个所述第一开口。
该半导体器件进一步包括：连接至所述底部接触金属化层的连接器。
在该半导体器件中，所述连接器包括焊球。
在该半导体器件中，所述焊球基本上是圆形的。
在该半导体器件中，所述焊球基本是细长的。
该半导体器件进一步包括：设置在所述第一开口下方的导电部件，其中，所述底部接触金属化层通过所述第一开口电连接至所述导电部件。
在该半导体器件中，所述导电部件包括后钝化互连件或接触焊盘。
根据本发明的又一方面，提供了一种制造半导体器件的方法，所述方法包括：提供衬底，所述衬底具有热膨胀系数失配的第一方向；在所述衬底上方形成钝化层；形成穿过所述钝化层的第一开口，所述第一开口包括多个细长孔隙，所述多个细长孔隙中的最长孔隙包括第一尺寸，横跨所述多个细长孔隙的间距包括小于所述第一尺寸的第二尺寸，其中，所述第一尺寸基本上与所述热膨胀系数失配的第一方向垂直对准；以及在所述第一开口上方形成底部接触金属化层。
在该方法中，所述热膨胀系数失配的第一方向与所述第一开口的多个细长孔隙的中心和所述衬底的中心之间的线对准。
该方法进一步包括：沿着所述衬底的外边缘形成多个所述第一开口或者在所述衬底的角部区域中形成多个所述第一开口。
该方法进一步包括：通过测试确定所述热膨胀系数失配的第一方向。
附图说明
为了更完整地理解多种实施例及其优点，现在结合附图所进行的以下描述作为参考，其中：
图1示出根据实施例的后钝化互连开口和底部接触金属化层的横截面图；
图2示出图1的后钝化互连开口和底部接触金属化层的俯视图；
图3示出图1的后钝化互连开口的对准的俯视图；
图4A至图4C示出根据实施例的可以结合后钝化互连开口的布局；
图5示出后钝化互连开口暴露接触焊盘的另一个实施例；以及
图6A和图6B示出分别连接至在此描述的后钝化互连开口的细长和圆形焊球的俯视图。
除非另外指定，不同图中的相应数字和标号通常指的是相应部件。绘制附图以清楚地示出实施例的相关方面并且不必须按比例进行绘制。
具体实施方式
以下详细地讨论了本实施例的制造和使用。然而，应该理解，实施例提供了多种可以在各种具体环境中实现的可应用发明思想。所论述的实施例仅示出制造和使用实施例的特定方式，并且不限制实施例的范围。
结合具体上下文中的实施例来描述实施例，即，底部接触金属化层下方的后钝化互连件。然而，实施例还可以应用于半导体器件的其他金属化层。实施例描述可以在芯片级封装和其他应用中利用的制造电连接件的结构和方法。
首先参考图1，示出了半导体管芯100的一部分，该半导体管芯包括：具有金属化层103的半导体衬底101、接触焊盘105、第一钝化层107、第二钝化层109、后钝化互连件(PPI)111、包括多个孔隙108a、108b和108c的PPI开口108、第三钝化层113、底部接触金属化层(UCM)115以及连接器117。为了制造半导体器件，首先提供了衬底101。半导体衬底101可以包括掺杂或不掺杂的体硅、或者绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括半导体材料层，诸如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)、或它们的组合。作为实例，可以使用的其他衬底包括多层衬底、梯度衬底或混合定向衬底。
可以在半导体衬底101上方形成有源器件(未示出)。本领域普通技术人员会认识到，诸如电容器、电阻器、电感器等的多种有源器件可以用于生成半导体管芯100的设计的期望结构和功能要求。有源器件可以在半导体衬底101的表面内或者上方使用任何合适方法形成。
金属化层103形成在半导体衬底101和有源器件上方并且金属化层103被设计成连接多种有源器件以形成功能电路。虽然在图1中作为单层示出了金属化层103，但是金属化层103可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，并且可以通过任何适当工艺(诸如，沉积、镶嵌、双镶嵌等)形成。可选地，可以使用其他材料和工艺制造金属化层103。在一个实施例中，存在通过至少一个层间介电层(ILD)与半导体衬底101隔离的四个金属化层，但是金属化层103的准确数量取决于半导体管芯100的设计。
接触焊盘105形成在金属化层103上方并且与其电接触。接触焊盘105可以包括铝，但是可选地，可以使用诸如铜的其他材料。接触焊盘105可以使用诸如溅射的沉积工艺形成，以形成材料层(未示出)。然后，该材料层的多个部分可以通过合适工艺(诸如，光刻掩模和蚀刻)去除，以形成接触焊盘105。然而，可以利用任何其他合适工艺以形成接触焊盘105。可以形成接触焊盘105以具有约0.5μm和约4μm之间的厚度，诸如，约1.45μm。可选地，接触焊盘105可以包括其他尺寸。
可以在半导体衬底101上的金属化层103和接触焊盘105的上方形成第一钝化层107。第一钝化层107可以由一种或多种合适的介电材料(诸如，氧化硅、氮化硅、它们的结合等)制成。第一钝化层107可以通过诸如化学汽相沉积(CVD)的工艺形成，但是可选地，可以利用任何其他合适工艺。第一钝化层107的厚度可以在约0.5μm和约5μm之间，诸如，约
Figure BDA00001962396300061
可选地，第一钝化层107可以包括其他尺寸。
在形成第一钝化层107之后，可以通过去除第一钝化层107的多个部分来制造穿过第一钝化层107的开口106a以暴露下面的接触焊盘105的至少一部分。开口106a允许接触焊盘105和PPI 111之间接触。开口106a可以使用合适光刻掩模和蚀刻工艺形成，但是可以使用任何合适工艺以暴露接触焊盘105的多个部分。
在接触焊盘105和第一钝化层107上方可以形成第二钝化层109。第二钝化层109可以由诸如聚酰亚胺的聚合物形成。可选地，第二钝化层109可以由类似于用作第一钝化层107的材料形成(诸如，氧化硅、氮化硅、它们的组合等)。第二钝化层109的厚度可以在约2μm和约15μm之间，诸如约5μm。可选地，第二钝化层109可以包括其他尺寸。
在形成第二钝化层109之后，可以通过去除第二钝化层109的多个部分来制造穿过第二钝化层109的开口106b以暴露下面的接触焊盘105的至少一部分。开口106b允许接触焊盘105和PPI 111之间接触。开口106b可以使用合适光刻掩模和蚀刻工艺形成，但是可以使用任何合适工艺以暴露接触焊盘105的多个部分。
在暴露接触焊盘105之后，可以形成包括导电材料的PPI 111，以沿着第二钝化层109延伸。PPI 111在本文(例如，在权利要求中)还被称为导电部件。代替将UCM 115的位置限制到直接在接触焊盘105上方的区域，PPI 111可以用作再分布层，以允许电连接至接触焊盘105的UCM 115位于半导体管芯100上方的任何期望位置。在一个实施例中，可以通过最初通过诸如CVD或溅射的合适形成工艺形成钛铜合金的晶种层(未示出)来形成PPI 111。然后，形成光刻胶(未示出)以覆盖晶种层，随后图案化光刻胶以暴露晶种层位于期望定位PPI 111的位置处的那些部分。
在形成和图案化光刻胶之后，可以通过诸如电镀的沉积工艺在晶种层上方形成诸如铜的导电材料。导电材料可以被形成为具有约1μm和约10μm之间的厚度，诸如约5μm，并且沿着衬底101的宽度在约5μm和约300μm之间，诸如，约15μm。然而，虽然所论述的材料和方法适用于形成导电材料，但是这些材料和尺寸仅是示例性的。可以可选地使用诸如AlCu或Au的任何其他合适材料和诸如CVD或物理汽相沉积(PVD)的任何其他合适形成工艺以形成PPI 111。
在形成导电材料之后，可以通过诸如灰化的合适去除工艺来去除光刻胶。另外，在去除光刻胶之后，例如，可以通过使用导电材料作为掩膜的任何蚀刻工艺去除晶种层中被光刻胶覆盖的那些部分。
在形成PPI 111之后，可以形成第三钝化层113以保护PPI 111和其他下面的结构。第三钝化层113在本文(例如，在权利要求中)还被称为后钝化层或介电层。第三钝化层113类似于第二钝化层109并且可以由诸如聚酰亚胺的聚合物形成，或者可以可选地由与第一钝化层107类似的材料(例如，氧化硅、氮化硅、它们的组合等)形成。可以形成第三钝化层113以具有约2μm和约15μm之间的厚度，诸如约5μm。可选地，第三钝化层113可以包括其他尺寸和材料。
在形成第三钝化层113之后，可以通过去除第三钝化层113的多个部分来制造穿过第三钝化层113的PPI开口108以暴露下面的PPI 111的至少一部分。PPI开口108允许UCM 115和PPI 111之间接触。PPI开口108可以使用合适光刻掩模和蚀刻工艺形成，但是可选地可以使用任何合适工艺以暴露PPI 111的多个部分。
根据本公开内容的实施例，PPI开口108包括多个孔隙108a、108b和108c。图1至图3、图4A至图4C、图5和图6A中示出三个孔隙108a、108b和108c。根据实施例，PPI开口108还可以包括两个孔隙108a和108b，或四个孔隙108a、108b、108c和108d或更多孔隙。例如，图6B示出开口108包括五个孔隙108a、108b、108c、108d和108e的实施例。
如图所示，多个孔隙108a、108b和108c是细长的并且可以包括卵形或椭圆形。可选地，多个孔隙108a、108b和108c可以包括其他细长形状，诸如矩形或梯形(未示出)。多个孔隙108a、108b和108c在本文还被称为多个细长孔隙。如以下进一步描述的，对多个孔隙108a、108b和108c进行定向，使得它们的细长边基本上与从形成多个孔隙108a、108b和108c的半导体管芯(诸如，衬底101)的中心延伸的线垂直。
在通过第三钝化层113中的开口108的多个细长孔隙108a、108b和108c暴露PPI 111之后，可以形成UCM 115，使得UCM 115与PPI 111电接触。例如，UCM 115延伸穿过开口108的多个细长孔隙108a、108b和108c或者延伸到其中。例如，UCM 115可以包括凸块底部金属化层(UBM)并且可以包括三层导电材料，诸如钛层、铜层和镍层。然而，本领域普通技术人员将认识到，存在材料和层的多种合适布置，诸如，铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置、或铜/镍/金的布置，这些布置适用于形成UCM 115。可以用于UCM 115的任何合适材料或材料层完全旨在包括在当前申请的范围内。
可以通过在第三钝化层113上方并且沿着穿过第三钝化层113的PPI开口108的内部(例如，沿着第三钝化层113中的多个细长孔隙108a、108b和108c的侧壁和顶面并且在PPI 111的暴露部分上方)形成每层来创建UCM 115。可以使用诸如电化学镀的电镀工艺来实施每层的形成，但是根据期望材料，可以可选地使用诸如溅射、蒸发或等离子体增强的化学汽相沉积(PECVD)工艺的其他形成工艺。可以形成UCM 115以具有约0.7μm和约10μm之间的厚度，诸如，约5μm。可选地，UCM 115可以包括其他尺寸。在形成期望层之后，然后可以通过合适光刻掩模和蚀刻工艺去除层的多个部分，以去除不期望材料并且在俯视图中留下期望形状的UCM 115，诸如，圆形、八边形、正方形或矩形形状，但是可以可选地形成任何期望形状的UCM 115。
连接器117可以是接触凸块，并且可以包括诸如锡的材料或诸如银、无铅锡、或铜的其他合适材料。在一些实施例中，连接器117可以包括焊球或可控塌陷芯片连接(controlled collapse chip connection，C4)凸块。在控制器117包括锡焊料凸块的实施例中，可以通过最初利用通用方法(诸如蒸发、电镀、印刷、焊料转移、焊球放置等)形成厚度为大约100μm的锡层来形成连接器117。可选地，连接器117可以包括其他尺寸。在结构上形成锡层之后，可以实施回流，以使材料成型为期望凸块形状，如图6A和图6B所示，期望凸块形状可以是细长的或圆形的。
图2示出沿着线A-A′(图1中)的包括PPI 111上方的多个孔隙108a、108b和108c以及UCM 115的PPI开口108的俯视图。为了清楚起见，从图2去除连接器117、第三钝化层113以及PPI 111下面的层，以更清楚地示出实施例的特征。另外，在该视图中，PPI开口108内的UCM 115和PPI开口108本身基本上共享相同边界；例如，UCM 115边界设置在多个孔隙108a、108b和108c周围。
可以从俯视图中看出，PPI开口108(例如，多个细长孔隙108b的最长孔隙)和PPI开口108内的UCM 115可以具有沿着开口纵轴LO-LO′的第一长度L1和沿着RDL纵轴RL-RL′的第一宽度W1。第一长度L1在本文还被称为第一尺寸，其中，第一尺寸基本上与热膨胀系数失配的第一方向垂直对准。例如，第一宽度W1包括横跨多个细长孔隙108a、108b和108c的尺寸。第一宽度W1在本文还被称为第二尺寸，其中，第二尺寸小于第一尺寸L1。例如，第一宽度W1包括横跨多个细长孔隙108a、108b和108c的间距。
在一个实施例中，第一长度L1可以大于第一宽度W1，使得与圆形开口相比来自第三钝化层113的更大数量的材料沿着RDL纵轴RL-RL′进行定位。通过沿着RDL纵轴RL-RL′放置第三钝化层113的大量材料，可以通过来自第三钝化层113的额外材料保护下面的层(诸如，金属化层103)免受由于沿着RDL纵轴RL-RL′的热膨胀系数失配所产生的应力。另外，通过与第一长度L1相比具有减小的第一宽度W1，可以沿着第一宽度W1获得由额外材料提供的保护，而不需要减小PPI开口108的每个尺寸(诸如，第一长度L1)，从而有助于保持UCM 115和PPI 111之间的接触电阻较低，同时仍然允许PPI开口108帮助保护下面的层。
在一个实施例中，第一长度L1可以在约50μm和约500μm之间，诸如约200μm，并且第一宽度W1可以在约30μm和约400μm之间，诸如约150μm。可选地，第一长度L1和第一宽度W1可以包括其他尺寸。
而且，在开口108的多个孔隙108a、108b和108c之间设置的附加第三钝化材料113为下面的材料层提供附加保护。在一些实施例中，多个细长孔隙108a、108b和108c可以间隔开约50μm以下，但是可选地，细长孔隙108a、108b和108c可以间隔开不同数量和尺寸。
PPI 111可以具有互连区204和第一区域202，第一区域包括在UCM115下面的接合焊盘，接合焊盘在每个方向上都具有比PPI开口108更大的尺寸，并且从俯视图中来看，有效地围绕PPI开口108和PPI开口108内的UCM 115。PPI 111可以在第一方向(例如，与RDL纵轴RL-RL′平行)上具有第二长度L2并且在另一方向(例如，与开口纵轴OL-OL′平行)上具有第二宽度W2。在一个实施例中，第二长度L2可以与第二宽度W2相同，或者可选地，第二长度L2可以大于或小于第二宽度W2。另外，互连区204可以具有小于第二宽度W2的第三宽度W3(包括在约60μm和约550μm之间，诸如约300μm)。可选地，第三宽度W3和第二宽度W2可以包括其他尺寸。
作为实例，在图2所示的实施例中，PPI 111的第二长度L2可以延伸到PPI开口108外第一距离A1，其可以在约1μm和约200μm之间，诸如约10μm。在相反方向上，PPI 111的第二长度L2可以延伸到PPI开口108外第二距离A2，其可以在约1μm和约200μm之间，诸如约10μm。同样地，PPI 111的第二长度L2可以基本上等于PPI开口108的第一宽度W1加上第一距离A1和第二距离A2。另外，PPI 111的第一区域202的第二宽度W2可以延伸第三距离B1，其可以在约1μm和约150μm之间，诸如约10μm。在与开口纵轴OL-OL′平行的相反方向上，PPI 111可以延伸第四距离B2，其可以在约1μm和约150μm之间，诸如约10μm。同样地，PPI 111的第一区域202的第二宽度W2可以基本等于PPI开口108的第一长度L1加上第三距离B1和第四距离B2。可选地，第一距离A1、第二距离A2、第三距离B1以及第四距离B2可以包括其他尺寸。
在一个实施例中，第一距离A1和第二距离A2可以基本上彼此相等，但是可选地，它们可以彼此不相等。类似地，第三距离B1可以基本上与第四距离B2相同，但是可选地，它们也可以是不同距离。然而，在一个实施例中，第一距离A1和第二距离A2的总和大于第三距离B1和第四距离B2的总和。同样地，PPI 111的第一区域202的第二长度L2可以是第一宽度W1加上第一距离A1和第二距离A2的总和，同时UCM 115下面的PPI 111的第一区域202的第二宽度W2可以是第一长度L1加上第三距离B1和第四距离B2的总和。
通过使第一区域202中的PPI开口108成形，使得来自第三钝化层113的额外材料沿着RDL纵轴RL-RL′进行定位，来自第三钝化层113的额外材料可以有效地保护下面的层(诸如金属化层103(参见图1)，下面的层可以具有金属和超低k介电层的组合)免受可能在热处理期间产生的沿着RDL纵轴RL-RL′的剥离应力。具体地，来自第三钝化层113的额外材料可以有效地保护下面的层免受由层之间的热膨胀失配所生成的应力。同样地，不可能发生这些层的分层，并且可以提高制造工艺的总产量。
图3示出具有位于其上的多个UCM 115的半导体管芯100的俯视图。俯视图仅示出位于管芯上方的UCM 115，同时第一实例305和第二实例307示出UCM 115以及PPI 111和PPI开口108。如图所示，在一个实施例中，UCM 115下方的PPI开口108的开口纵轴OL-OL′可以基本上与热膨胀系数失配的方向(通过线303在图3中所示)垂直对准。纵轴OL-OL′与PPI开口108的多个细长孔隙108a、108b和108c的中心和衬底100的中心之间的线201垂直地进行定位。纵轴OL-OL′基本上与用于特定PPI开口108的热膨胀系数失配的方向303垂直对准。仅作为实例，在半导体管芯100上方，热膨胀系数失配的方向303从半导体管芯100的中心向外呈放射状延伸。同样地，对于图3所示的每一个UCM 115来说，热膨胀系数失配的方向303可以通过绘制从半导体管芯100的中心到对应UCM 115的中心的线(例如，图3中的第一线309和第二线311)确定。在确定用于每个对应UCM 115的热膨胀系数失配的方向303之后，每个对应UCM 115的下方的每个PPI 111的开口纵轴OL-OL′可以基本上与热膨胀系数失配的方向303垂直对准，例如，沿着线201。
在图3中示出了这两个实例，第一实例由虚线框305表示，并且第二实例由虚线框307表示。在第一实例305中，UCM 115沿着半导体管芯100的外边缘进行定位，并且热膨胀系数失配的第一方向303可以通过在使第一线309从半导体管芯100的中心延伸到虚线框305内的UCM 115的中心来确定。在确定用于虚线框305内的UCM 115的热膨胀系数失配的方向303之后，PPI开口108(例如，多个细长孔隙108a、108b和108c的)的开口纵轴OL-OL′可以与热膨胀系数失配的第一方向303垂直对准，从而帮助保护下面的层免受由热膨胀系数的差异所产生的应力。
在第二实例307中，类似于第一实例305，热膨胀系数失配的第二方向303可以通过使第二线311从半导体管芯100的中心延伸到在虚线框307内的UCM 115的中心来确定。在确定用于虚线框307内的UCM 115的热膨胀系数失配的第二方向303之后，下面的PPI开口108的开口纵轴OL-OL′(例如，沿着最长细长孔隙108b的长度)可以基本上与热膨胀系数失配的第二方向303垂直对准，由此还帮助保护下面的层免受由热膨胀系数的差异所产生的应力。
然而，本领域普通技术人员将认识到，确定热膨胀系数失配的方向303的上述方法不是可以使用的唯一方法。可以可选地利用可选方法，诸如测试半导体管芯100和/或用实验的方法测量热处理下的热膨胀系数失配的实际方向303。可以可选地使用这些方法和任何其他合适方法，并且完全旨在包括在本实施例的范围内。
图4A至图4C示出PPI开口108可以相对于热膨胀系数失配的方向303对准的不同实施例。在图4A的俯视图所示的实施例中，所有PPI开口108都包括位于半导体管芯100上的多个细长孔隙108a、108b和108c，并且所有PPI开口108都单独对准以基本上与热膨胀系数失配的方向303(如通过三条虚线401所示的)垂直。每个PPI开口108都根据其在半导体管芯100上的位置和其相对于半导体管芯100的中心的位置不同地进行对准。
图4B示出仅位于半导体管芯100的角部区域403内的那些PPI开口108基本上与热膨胀系数失配的方向303垂直对准的实施例的俯视图。在这样的实施例中，例如，在位于角部区域403内的PPI开口108包括基本上与热膨胀系数失配的方向303垂直对准的细长孔隙108a、108b和108c的同时，在管芯100的中心区域和沿着管芯100的边缘的剩余PPI开口108′可以包括圆形开口。在一个实施例中，每个角部区域403都可以包括位于半导体管芯100的角部中的一个PPI开口108。如图4B所示，角部区域403还可以可选地包括角部PPI开口108的每侧上的邻近PPI开口108，邻近PPI开口108还沿着半导体管芯100的边缘进行定位并且基本上与热膨胀系数失配的方向垂直对准。例如，可选地，角部区域403中的PPI开口108可以包括任何合适形状或布置，以帮助防止下面的层的分层。
图4C示出仅沿着半导体管芯100的外边缘405的那些PPI开口108与热膨胀系数失配的方向303垂直对准的另一个实施例，而例如衬底101的内部区域中的剩余PPI开口108′可以包括圆形开口。在该实施例中，外边缘405可以包括宽度为一个PPI开口108的边缘。可选地，外边缘405的厚度可以大于一个PPI开口108宽度，诸如，两个或更多PPI开口108的宽度；例如，外边缘405可以包括在本文描述的两行PPI开口108(未示出)。
图5示出第二钝化层109和PPI 111不包括在结构中的另一个实施例；例如，在衬底101和金属化层103上方没有形成先前实施例中所示的第二钝化层109和PPI 111。而是，在形成接触焊盘105之前，可以在金属化层103上方形成第一钝化层107。在一个实施例中，如以上关于图1所述的，可以形成第一钝化层107，但是可以可选地利用其他材料和方法。
在形成第一钝化层107之后，可以使用合适光刻掩模和蚀刻工艺图案化第一钝化层107，以暴露金属化层103的一部分。在暴露金属化层103的部分之后，可以通过使用以上参照图1描述的类似材料和工艺形成穿过第一钝化层107的接触焊盘105。另外，在该实施例中，接触焊盘105可以形成为沿着第一钝化层107延伸，用作再分布层并且代替PPI 111的作用，在该实施例中可以不形成PPI 111。接触焊盘105在本文(例如，在权利要求中)还被称为导电部件。
在形成接触焊盘105以沿着第一钝化层107延伸之后，使用类似于以上参照图1描述的材料和工艺在接触焊盘105上方形成第三钝化层113，并且可以图案化第三钝化层113以形成穿过第三钝化层113的接触焊盘开口501。可以类似于以上参照图1至图3和图4A至图4C描述的形成和成形PPI开口108来形成和成形接触焊盘开口501。例如，接触焊盘开口501包括被成形为具有以上参照图2描述的第一长度L1和第一宽度W1的多个细长孔隙108a、108b和108c。另外，接触焊盘开口501的第一长度L1(例如，最长的细长孔隙108b的)还可以基本上与衬底101的热膨胀系数失配的方向垂直对准。
通过形成接触焊盘开口501以暴露接触焊盘105，接触焊盘开口501可以用于帮助在接触焊盘105层处保护下面的层。另外，在该实施例中可以不利用第二钝化层109和PPI 111，并且在半导体器件中可以不包括第二钝化层109和PPI 111。在没有附加材料层的情况下，整个制造工艺可以被简化并且更加有效。
在形成包括细长的多个孔隙108a、108b和108c的PPI开口108或接触焊盘开口501之后，在开口108或501上方形成UCM 115。UCM 115通过图1中的PPI开口108的多个细长孔隙108a、108b和108c电连接至导电部件(例如PPI 111)，或者通过图5中的接触焊盘开口501的多个细长孔隙108a、108b和108c连接至接触焊盘105。连接器117形成在每个UCM115上方。根据多个孔隙108a、108b和108c(并且还有图6B中所示的孔隙108d和108e)的整体形状，连接器117可以包括可以是细长的或圆形的焊球。图6A和图6B示出分别连接至在此描述的后钝化互连开口108或接触焊盘开口501的细长和圆形焊球的俯视图。
本公开内容的实施例包括具有新开口108和501的半导体器件，新开口108和501包括细长孔隙108a、108b、108c、108d和108e。实施例还包括制造半导体器件的方法。
根据本公开内容的一个实施例，半导体器件包括：设置在衬底上方的后钝化层，衬底具有热膨胀系数失配的第一方向。半导体器件包括穿过后钝化层的第一开口，第一开口包括多个细长孔隙。多个细长孔隙中的最长孔隙包括第一尺寸，其中，第一尺寸基本上与热膨胀系数失配的第一方向垂直对准。
根据另一个实施例，半导体器件包括在衬底上方设置的介电层和穿过介电层的第一开口。第一开口包括多个细长孔隙，多个细长孔隙中的最长孔隙包括第一尺寸。横跨多个细长孔隙的间距包括小于第一尺寸的第二尺寸。第一尺寸与在衬底的中心和第一开口的多个细长孔隙的中心之间的第一线垂直对准。底部接触金属化层延伸到第一开口的多个细长接触件。
根据又一个实施例，制造半导体器件的方法包括：提供衬底，衬底具有热膨胀系数失配的第一方向。该方法包括：在衬底上方形成钝化层并且形成穿过钝化层的第一开口。第一开口包括多个细长孔隙，多个细长孔隙中的最长孔隙包括第一尺寸。横跨多个细长孔隙的间距包括小于第一尺寸的第二尺寸，并且第一尺寸基本上与热膨胀系数失配的第一方向垂直对准。该方法包括在第一开口上方形成底部接触金属化层。
虽然详细描述了本实施例及其优点，但是应该理解，可以在不背离由所附权利要求限定的实施例的精神和范围的情况下，在此可以进行多种改变、替换和更改。例如，角部区域或外边缘的准确形状可以被修改，或者用于确定热膨胀系数失配的方向的方法可以被改变，但是仍然保持在实施例的范围内。
而且，本申请的范围不旨在限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。由于本领域技术人员根据本公开可以很容易地想到，当前存在的或者今后开发的执行与这里所述的相应实施例基本相同的功能或者完成与这里所述的相应实施例基本相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤的可以根据本公开被利用。从而，所附权利要求旨在包括这种工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种半导体器件，包括：
后钝化层，设置在衬底上方，所述衬底具有热膨胀系数失配的第一方向；以及
第一开口，穿过所述后钝化层，所述第一开口包括多个细长孔隙，所述多个细长孔隙中的最长孔隙包括第一尺寸，其中，所述第一尺寸基本上与所述热膨胀系数失配的第一方向垂直对准。
2.根据权利要求1所述的半导体器件，进一步包括：底部接触金属化层，延伸穿过所述第一开口的多个细长孔隙。
3.根据权利要求1所述的半导体器件，进一步包括：穿过所述后钝化层的第二开口，所述第二开口基本上为圆形。
4.根据权利要求3所述的半导体器件，其中，所述第一开口沿着所述衬底的边缘进行定位。
5.根据权利要求4所述的半导体器件，其中，所述第一开口位于所述衬底的角部区域处，并且所述第二开口沿着所述衬底的边缘进行定位。
6.根据权利要求4所述的半导体器件，其中，所述第二开口位于所述衬底的内部区域内。
7.根据权利要求1所述的半导体器件，其中，横跨所述第一开口的多个细长孔隙的间距包括第二尺寸，所述第二尺寸小于所述第一尺寸。
8.根据权利要求7所述的半导体器件，进一步包括：穿过所述后钝化层的第二开口，所述第二开口包括多个第二细长孔隙，所述多个第二细长孔隙中的最长孔隙包括第三尺寸，横跨所述多个第二细长孔隙的间距包括小于所述第三尺寸的第四尺寸，其中，所述第三尺寸基本上与所述衬底的热膨胀系数失配的第二方向垂直对准。
9.一种半导体器件包括：
介电层，设置在衬底上方；
第一开口，穿过所述介电层，所述第一开口包括多个细长孔隙，所述多个细长孔隙的最长孔隙包括第一尺寸，横跨所述多个细长孔隙的间距包括小于所述第一尺寸的第二尺寸，其中，所述第一尺寸基本上与在所述衬底的中心和所述第一开口的多个细长孔隙的中心之间延伸的第一线垂直对准；以及
底部接触金属化层，延伸至所述第一开口的所述多个细长孔隙中。
10.一种制造半导体器件的方法，所述方法包括：
提供衬底，所述衬底具有热膨胀系数失配的第一方向；
在所述衬底上方形成钝化层；
形成穿过所述钝化层的第一开口，所述第一开口包括多个细长孔隙，所述多个细长孔隙中的最长孔隙包括第一尺寸，横跨所述多个细长孔隙的间距包括小于所述第一尺寸的第二尺寸，其中，所述第一尺寸基本上与所述热膨胀系数失配的第一方向垂直对准；以及
在所述第一开口上方形成底部接触金属化层。
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