CN102347314A - 电动马达驱动用半导体元件 - Google Patents
电动马达驱动用半导体元件 Download PDFInfo
- Publication number
- CN102347314A CN102347314A CN2011101957596A CN201110195759A CN102347314A CN 102347314 A CN102347314 A CN 102347314A CN 2011101957596 A CN2011101957596 A CN 2011101957596A CN 201110195759 A CN201110195759 A CN 201110195759A CN 102347314 A CN102347314 A CN 102347314A
- Authority
- CN
- China
- Prior art keywords
- inspection
- electrode
- main electrode
- probe
- electrode surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000007689 inspection Methods 0.000 claims abstract description 79
- 230000033228 biological regulation Effects 0.000 claims description 7
- 239000000523 sample Substances 0.000 abstract description 53
- 101150073536 FET3 gene Proteins 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005755 formation reaction Methods 0.000 description 7
- 230000005764 inhibitory process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100500641 Oscheius tipulae eft-3 gene Proteins 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
本发明提供一种电动马达驱动用半导体元件。电动马达驱动用FET(3)包括源电极(5)。源电极(5)包括接合流过电动马达(50)的驱动电流的键合线(31)的主电极面(11、12、13),与这些主电极面(11、12、13)独立且分离地配置的检查用电极面(21、22、23)。检查用电极面(21、22、23)是用于与检查FET(3)的检测装置的探针接触而设置的。
Description
技术领域
本发明请求2010年7月23日在日本提出的专利申请No.2010-16155的优先权,并将其说明书、附图及摘要引入本申请。
本发明涉及电动马达驱动用半导体元件。
背景技术
车辆用电动动力转向装置具备无刷电动马达等电动马达及驱动电路。驱动电路驱动电动马达。驱动电路包括MOSFET等开关元件(半导体元件)。开关元件例如以裸芯片状态被安装于电路基板。键合线与电路基板上安装的开关元件的例如源电极接合。键合线与电动马达的线圈接合。键合线连接电路基板上安装的开关元件的例如源电极和电动马达的线圈。
包含该开关元件的驱动电路在从工厂出厂前进行检查。该检查例如通过用检查用探针接触上述的源电极的表面而进行。例如在日本特开2002-329742号公报、日本特开2005-527968号公报记载有使用探针的半导体元件的检查方法。
在日本特开2002-329742号公报、日本特开2005-527968号公报所记载的半导体元件的电极表面具有键合线接合的区域和检查用探针接触的区域。键合线接合的区域与接触检查用探针的区域相连。但是,这样的构成可以说对电动马达驱动用的开关元件的检查没有经过特别的考虑。
电动马达驱动用的开关元件驱动电动马达时,在电动马达驱动用的开关元件中流过大电流。因此,在检查电动马达驱动用的开关元件时有时不使用普通的探针而使用专用的探针。该专用探针具有与普通探针不同的形状。例如,专用探针的前端部是花插座形状。花插座形状的专用探针的前端部具有多个与开关元件的电极表面接触的尖锐的接触部。或者,专用探针的前端部是极粗的形状。因此,专用探针的前端部与普通探针的前端部相比,以宽的范围与开关元件的电极表面接触。因此,专用探针的前端部不仅以不与键合线接合的区域接触的方式严格地定位在开关元件的电极表面,还需要接触开关元件的电极表面。
但是,如上所述在专利文献1、2的构成中,半导体元件的电极的表面上键合线接合的区域和检查用探针接触的区域相连。因此,很难分开键合线接合的区域和检查用探针接触的区域。因此,操作员在使用探针进行检查时,存在操作员错误地将检查用探针的前端接触到键合线接合的区域而造成损伤的问题。因该检查用探针而被损伤的键合线接合的区域上的损伤是造成键合线与键合线接合的区域进行接合时的接合不良的原因。
并且,操作员在使用检查用探针进行开关元件的检查时,区分键合线接合的区域和检查用探针接触的区域需要花费时间,降低制造效率。结果,使制造成本变高。
另一方面,考虑到使用自动检查装置检查开关元件的情况。此时,考虑如下的检查方法。自动检查装置首先通过摄像机对开关元件的电极表面进行拍摄。接着,自动检查装置通过图像处理装置识别键合线接合的区域和检查用探针接触的区域。接着,自动检查装置利用机器臂等移动检查用探针,使检查用探针接触到接触检查用探针的区域。
在使用自动检查装置检查开关元件时也存在与操作员使用检查用探针检查开关元件时一样的不良情况。该不良情况是很难区分键合线接合的区域和检查用探针接触的区域。存在自动检查装置误检测出键合线接合的区域和检查用探针接触的区域的问题。此时也存在自动检查装置错误地使检查用探针的前端接触到键合线接合的区域而造成损伤的问题。使用自动检查装置检查开关元件时为了能够准确地识别上述两个区域而需要包含高分辨率的摄像机的高级的图像处理装置,从而会使成本变高。
发明内容
本发明的目的之一在于,在电动马达驱动用半导体元件中,实现对发生接合不良的抑制,以及对制造成本的抑制。
本发明的一方面的电动马达驱动用半导体元件3的构成上的特征是:具有规定的电极5,上述规定的电极具有:主电极面10,其接合流过上述电动马达的驱动电流的导电部件31;检查用电极面20,其与该主电极面独立且分离地配置,用于与检查上述半导体元件的检测装置40的接触部47接触。
附图说明
本发明的这些特征和其它优点能够通过参照附图的下述实施方式的说明而变得明确,这些附图中相同或相似的部位被标注了相同符号。
图1是包含本发明的一个实施方式的半导体元件的元件安装基板的主要部分的示意性俯视图。
图2是用于说明FET检查的图,(A)是检查装置及FET的示意性立体图,(B)是用于说明检查时的状态的示意性立体图。
具体实施方式
参照附图说明本发明的优选实施方式。
图1是包含本发明的一个实施方式的半导体元件的元件安装基板1的主要部分的示意性俯视图。参照图1,元件安装基板1例如是用于驱动电动动力转向装置的电动马达50的配电板。该元件安装基板1通过未图示的母线等连接部件向电动马达50的U相线圈51、V相线圈52以及W相线圈53提供电力。借助该电力驱动电动马达50。
元件安装基板1包括基板主体2和安装于基板主体2的作为半导体元件的FET3。
基板主体2例如是在多个绝缘层之间分别形成有导体层的多层电路基板。在基板主体2的表面上形成有焊盘4。FET3安装于焊盘4上。
EFT3例如是MOSFET(Metal Oxide SemiconductorFieldEffectTransistor:金属氧化物半导体场效应晶体管),是开关元件。而且,FET3是用于驱动电动马达50的功率FET。FET3会流过大电流(例如数十A)。FET3是半导体芯片。FET3以裸芯片的状态安装于基板主体2上。FET3包含作为规定电极的源电极5、漏电极6以及栅电极7。
漏电极6在FET3的背面露出。漏电极6和焊盘4通过未图示的焊接部件(未图示)而焊接接合。
源电极5是规定电极,并且是单一的(仅设置有一个)电极。源极5在FET3的表面3a露出。源电极5包括形成于FET3的表面3a的焊盘即电极面8。电极面8包括主电极面10和检查用电极20。检查用电极20与主电极面10独立且分离地配置。更具体而言,在俯视FET3时,主电极面10和检查用电极面20独立且分离地配置。
主电极面10为了与作为导电部件的键合线31接合而设置。检查用电极面20为了在制造FET3时、制造元件安装基板1时等检查FET3而设置。
主电极面10设置有多个(本实施方式中例如是三个)。主电极面10包括第一、第二及第三主电极面11、12、13。另外,以下,对各主电极面11、12、13进行统称时仅称为主电极面10。
各主电极面11、12、13在俯视时形成为矩形形状。各主电极面11、12、13形成为平滑的平面。
作为导电部件的键合线31的一端31a通过引线键合被接合在各主电极面11、12、13上。各键合线31的另一端31b与形成于基板主体2的焊盘32接合。相同数量(例如本实施方式中为2)的键合线31被接合在各主电极面11、12、13上。各键合线31上流过电动马达50的驱动电流。
检查用电极面20设置有多个(在本实施方式中是与主电极面11、12、13相同的数量即3个)。检查用电极20包括第一、第二及第三检查用电极面21、22、23。另外,以下,对各检查用电极面21、22、23进行统称时仅称为检查用电极面20。
各检查用电极面21、22、23形成为与各主电极面11、12、13相同的形状。即、各检查用电极面21、22、23在俯视时形成为矩形形状。各检查用电极面21、22、23上形成有多个凹部33。凹部33是由于后述的检测装置40的探针46与各检查用电极21、22、23接触而形成的微小的压痕。
主电极面10和检查用电极面20沿规定的第一排列方向X1交替地且等间隔地配置。第一排列方向X1例如与FET3的一个边部3b平行。具体而言,沿第一排列方向X1,按照第一主电极面11、第一检查用电极面21及第二主电极面12的顺序排列。
而且,在俯视时,第二排列方向与第一排列方向X1正交。关于第二排列方向X2,以与这些第一主电极面11、第一检查用电极面21及第二主电极面12并排的方式,配置有第二检查用电极面22、第三主电极面12及第三检查用电极面23。第二检查用电极面22、第三主电极面13及第三检查用电极面23沿第一排列方向X1交替地且等间隔地配置。
根据上述构成,主电极面10在俯视时交错配置。各主电极面11、12、13和各检查用电极面21、22、23通过FET3的表面3a的钝化膜34被分割为网格状。钝化膜34是在制造FET3时形成的绝缘膜,例如是黑色的。钝化膜34的颜色与主电极面10的颜色以及检查用电极面20的颜色不同。
与第一主电极面11及第二主电极面12接合的各键合线31未横跨检查用电极面20。另一方面,与第三主电极面13接合的键合线31横跨检查用电极面20(第一检查用电极面21)。这样,横跨检查用电极面20的键合线31的数量比未横跨检查用电极面20的键合线31的数量要少。
栅极7在FET3的表面3a露出。栅极7与源极5分离地配置于FET3的表面3a。键合线35的一端接合于该栅极7。键合线35的另一端接合于在基板主体2的表面上形成的焊盘36。
接着,说明FET3的检查。FET3是单品状态或是安装于基板主体2的状态,是在进行引线键合前要进行的检查。
图2是用于说明FET3的检查的图,图2(A)是检测装置40及FET3的示意性立体图,图2(B)是用于说明检查时的状态的示意性立体图。参照图2(A)及图2(B),利用检测装置40对FET3自动地(未介入人工)进行特性检查。检测装置40包括探针单元41、驱动装置42、摄像机43以及控制部44。驱动装置42使探针单元41进行变位。摄像机43是摄像装置。控制部44包括CPU等。控制部44控制探针单元41、驱动装置42和摄像机43。
探针单元41包括多个探针46。探针单元41整体呈花插座形状。各探针46例如是电流探针。各探针46具有用于与FET3的检查用电极面20接触的接触部47。各接触部47形成在探针46的前端部。各接触部47形成为尖锐的形状。通过在探针单元41中设置有多个接触部47,从而在俯视时,被各接触部47包围的区域的面积变大。这样,通过在探针46的前端设置多个接触部47,而能够对FET3施加大的电荷(大电流)来检查FET3。由此,能够进行假定了FET的实际使用状态的检查。
控制部44使摄像机43对FET3的表面3a进行摄影。而且,控制部44基于由摄像机43得到的图像数据以及预先存储于ROM中的数据等,识别主电极面10和检查用电极面20。控制部44通过驱动驱动装置42而使各探针46的接触部47接触已被识别的检查用电极面20。
由此,如图2(B)所示,例如各探针46的接触部47按压第一检查用电极面21。在该状态下,进行FET3的特性检查。此时,在第一检查用电极面21上形成凹部(参照图1)。另外,各探针46的接触部47既可仅按压一个或两个检查用电极面20(例如检查用电极面21、22),也可按压所有的检查用电极面21、22、23。在各探针46的接触部47按压所有的检查用电极面21、22、23的情况下,可以使各接触部47一起按压各检查用电极面21、22、23,也可使接触部47单个地按压各检查用电极面21、22、23。而且,也可通过操作员(检查员)的手来代替驱动装置42操作探针单元41。
如上述说明那样,根据本实施方式,源电极5的主电极面10和检查用电极面20是独立的且相互分离地配置的。由此,能够容易地区分主电极面10和检查用电极面20。因此,能够抑制操作员或检测装置40对主电极面10和检查用电极面20的误识别。其结果,能够抑制操作员或检测装置40使探针46的接触部47对主电极面10的误接触。其结果,能够抑制由于各探针46的接触部47接触主电极面10而造成的主电极面10的损伤。由此,能够抑制主电极面10和键合线31基于引线键合而接合时的接合不良。
而且,能够容易地区分主电极面10和检查用电极面20的结果是,在由操作员进行检查时,操作员能够在短时间内区分这些主电极面10和检查用电极面20。由此,能够提高制造效率,因此能够抑制制造成本。而且,由于在使用了驱动装置42等的自动检查的情况下,检测装置40识别主电极面10和检查用电极面20的精度变低也可以,所以能够利用廉价的检测装置40,能够抑制制造成本。并且,采用使主电极面10和检查用电极面20分离地配置即可这样的成本廉价的构成,因此能够进一步地降低制造成本。
如上所述,能够以低成本解决流过大电流的电动马达驱动用的FET3特有的问题,即、由检测装置40的探针单元41的形状的特殊性等引起的需要准确地识别主电极面10和检查用电极面20这样的问题。并且,能够抑制流过大电流的源电极5处的接合不良。
而且,沿第一排列方向X1交替地配置有第一主电极面11、第一检查用电极面21以及第二主电极面12。此处,各主电极面11、12与键合线31连接,因此发热量大。能够使该发热量多的多个主电极面11、12彼此在第一排列方向X1上更分离地配置。由此,能够容易地释放出驱动FET3时的各主电极面11、12的热量。因此,能够高效地释放出FET3的热量。并且,采用沿第一排列方向X1交替地配置主电极面10和检查用电极面20这样的简单的构成,因此能够抑制制造成本。
并且,主电极面10交错配置。这样,将源电极5的电极面8中发热量多的主电极面10交错配置。由此,能够容易地释放出驱动FET3时的各主电极面11、12、13的热量。因此,能够更高效地释放出FET3的热量。并且,采用将主电极面10交错配置这样的简单的构成,能够抑制制造成本。
而且,通过钝化膜34分隔主电极面10和检查用电极面20。由此,能够更准确地识别主电极面10和检查用电极面20。并且,钝化膜34通常设置于FET3。因此,不必另外设置用于分隔主电极面10和检查用电极面20的专用部件,能够进一步地抑制制造成本。
本发明并不限定于上述实施方式,在权利要求所记载的范围内能够有各种变更。
例如,探针单元也可仅具有一个探针。此时,探针例如可以是前端部粗大的棒状。并且,主电极面10和检查用电极面20也可通过钝化膜34以外的其他绝缘部件来进行分隔。而且,主电极面10和检查用电极面20也分别仅设置一个。
并且,也可在漏电极、栅电极等其他电极上设置本发明的主电极面和检查用电极面。而且,作为开关元件以MOSFET进行了例示,也可使用其他的FET、晶体管等电动马达驱动用的开关元件(半导体元件)。
Claims (5)
1.一种电动马达驱动用半导体元件,其特征在于,
具有规定的电极;
所述规定的电极具有:主电极面,其接合流过所述电动马达的驱动电流的导电部件;检查用电极面,其与该主电极面独立且分离地配置,用于与检查所述半导体元件的检测装置的接触部接触。
2.根据权利要求1所述的电动马达驱动用半导体元件,其特征在于,
所述半导体元件具有源电极、漏电极及栅电极;
所述规定的电极是所述源电极。
3.根据权利要求1或2所述的电动马达驱动用半导体元件,其特征在于,
所述主电极面和所述检查用电极面沿规定的排列方向交替地配置。
4.根据权利要求1至3中任一项所述的电动马达驱动用半导体元件,其特征在于,
所述主电极面交错配置。
5.根据权利要求1至4中任一项所述的电动马达驱动用半导体元件,其特征在于,
所述主电极面和所述检查用电极面通过钝化膜被分隔。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010166155A JP5557100B2 (ja) | 2010-07-23 | 2010-07-23 | 電動モータ駆動用の半導体素子 |
JP2010-166155 | 2010-07-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102347314A true CN102347314A (zh) | 2012-02-08 |
CN102347314B CN102347314B (zh) | 2015-11-25 |
Family
ID=44645506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110195759.6A Expired - Fee Related CN102347314B (zh) | 2010-07-23 | 2011-07-08 | 电动马达驱动用半导体元件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8648340B2 (zh) |
EP (1) | EP2410559A3 (zh) |
JP (1) | JP5557100B2 (zh) |
CN (1) | CN102347314B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6305754B2 (ja) * | 2013-12-20 | 2018-04-04 | 東京特殊電線株式会社 | コンタクトプローブユニット |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004172448A (ja) * | 2002-11-21 | 2004-06-17 | Renesas Technology Corp | 半導体装置 |
CN1652329A (zh) * | 2004-02-05 | 2005-08-10 | 松下电器产业株式会社 | 半导体装置 |
CN101339946A (zh) * | 2007-02-28 | 2009-01-07 | 松下电器产业株式会社 | 半导体集成电路器件及其制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0335542A (ja) * | 1989-06-30 | 1991-02-15 | Fujitsu Ltd | 電界効果型トランジスタ及びその製造方法 |
JP2536419B2 (ja) * | 1993-07-23 | 1996-09-18 | 日本電気株式会社 | 半導体集積回路装置 |
JPH07221102A (ja) | 1994-01-31 | 1995-08-18 | Casio Comput Co Ltd | 半導体装置の突起電極構造およびその突起電極形成方法 |
JP3022819B2 (ja) * | 1997-08-27 | 2000-03-21 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
US20020016070A1 (en) * | 2000-04-05 | 2002-02-07 | Gerald Friese | Power pads for application of high current per bond pad in silicon technology |
JP2002329742A (ja) * | 2001-05-07 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置 |
US6844631B2 (en) | 2002-03-13 | 2005-01-18 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
JP2004055756A (ja) * | 2002-07-18 | 2004-02-19 | Sanyo Electric Co Ltd | 混成集積回路装置 |
JP4611067B2 (ja) * | 2004-03-16 | 2011-01-12 | パナソニック株式会社 | 半導体装置 |
JP4538359B2 (ja) * | 2005-03-31 | 2010-09-08 | 株式会社日立産機システム | 電気回路モジュール |
-
2010
- 2010-07-23 JP JP2010166155A patent/JP5557100B2/ja not_active Expired - Fee Related
-
2011
- 2011-07-08 CN CN201110195759.6A patent/CN102347314B/zh not_active Expired - Fee Related
- 2011-07-12 US US13/181,053 patent/US8648340B2/en not_active Expired - Fee Related
- 2011-07-21 EP EP11174820.8A patent/EP2410559A3/en not_active Ceased
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004172448A (ja) * | 2002-11-21 | 2004-06-17 | Renesas Technology Corp | 半導体装置 |
CN1652329A (zh) * | 2004-02-05 | 2005-08-10 | 松下电器产业株式会社 | 半导体装置 |
CN101339946A (zh) * | 2007-02-28 | 2009-01-07 | 松下电器产业株式会社 | 半导体集成电路器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102347314B (zh) | 2015-11-25 |
JP5557100B2 (ja) | 2014-07-23 |
EP2410559A2 (en) | 2012-01-25 |
US20120018725A1 (en) | 2012-01-26 |
EP2410559A3 (en) | 2014-04-30 |
JP2012028574A (ja) | 2012-02-09 |
US8648340B2 (en) | 2014-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102053437B (zh) | 显示面板 | |
KR101571768B1 (ko) | 표시 기판, 이의 불량 리페어 방법 및 이 표시 기판을 갖는모기판 | |
JP4774071B2 (ja) | プローブ抵抗値測定方法、プローブ抵抗値測定用パッドを有する半導体装置 | |
CN107367678B (zh) | 测试结构、测试探针卡、测试系统及测试方法 | |
TWI395037B (zh) | 主動元件陣列基板及其檢測方法 | |
JP2006350064A (ja) | 表示装置および位置ずれ検査方法 | |
US10043466B2 (en) | Display device | |
KR20130055504A (ko) | 퓨즈 소자를 이용한 집적회로장치의 테스트 방법 | |
CN105074482A (zh) | 被测试器件的检查系统及其操作方法 | |
TW201447334A (zh) | 基板檢測裝置、基板檢測方法及基板檢測用夾具 | |
CN102347314A (zh) | 电动马达驱动用半导体元件 | |
JP2001156417A (ja) | 回路基板間の接続状態検査用パターン | |
JP4803692B2 (ja) | 液晶表示パネルの点灯検査方法 | |
US9229052B2 (en) | Stack including inspection circuit, inspection method and inspection apparatus | |
US20120126230A1 (en) | Method for manufacturing a semiconductor chip stack device | |
CN106158687A (zh) | 贯孔漏电与击穿测试 | |
CN113539087B (zh) | 第一显示面板、第二显示面板及其制作方法、显示装置 | |
JPH0990398A (ja) | 電気配線基板の接続構造 | |
JP4537261B2 (ja) | 検査装置 | |
US20050265009A1 (en) | Detecting short circuits and detecting component misplacement | |
US20140320156A1 (en) | Apparatus for detecting misalignment of test pad | |
JPH11142472A (ja) | フィルムキャリア型半導体装置及び検査用プローブヘッド並びに位置合わせ方法 | |
US20150084659A1 (en) | Contact arrangements and methods for detecting incorrect mechanical contacting of contact structures | |
CN106601639B (zh) | 不着检出测试方法及其所用的基板与压板 | |
CN219143031U (zh) | 一种双路芯片测试电路板及测试系统 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151125 Termination date: 20200708 |
|
CF01 | Termination of patent right due to non-payment of annual fee |