CN1652329A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1652329A
CN1652329A CNA2005100091849A CN200510009184A CN1652329A CN 1652329 A CN1652329 A CN 1652329A CN A2005100091849 A CNA2005100091849 A CN A2005100091849A CN 200510009184 A CN200510009184 A CN 200510009184A CN 1652329 A CN1652329 A CN 1652329A
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pad metal
metal layer
metal
pad
semiconductor device
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CN100365809C (zh
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三村忠昭
滨谷毅
水谷笃人
植田贤治
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Nuvoton Technology Corp Japan
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明涉及半导体装置。作为半导体装置的外部连接用电极的焊盘部，由形成于最上层的第1焊盘金属(61)、夹着层间绝缘膜(71)形成于第1焊盘金属(61)之下的第2焊盘金属(62)、以及贯通层间绝缘膜(71)，电气连接第1焊盘金属(61)与第2焊盘金属(62)的通路(63)所构成，配置第1焊盘金属(61)的端部与第2焊盘金属(62)的端部，使沿各层的厚度方向不一致地互相偏移。采用这样的结构，可减小发生于第2焊盘金属(62)的边沿上的应力，能减少层间绝缘膜(71)等的损坏。

Description

半导体装置
发明领域
本发明涉及半导体装置的外部连接用电极，特别涉及焊盘部的构造与配置。
背景技术
已有的半导体装置中，例如图11所示，作为外部连接用电极的电极焊盘22，采用通过通路66电气连接形成于最上层的第1焊盘金属67与形成于下一配线层的第2焊盘金属65的层叠通路构造，利用形成于不在电极焊盘22的正下方区域的，对连接于半导体基板上的电路元件的配线10等，利用引出部金属81的叠层构造进行连接。
以芯片尺寸的缩小为目的，也有人提出将外部连接用的焊盘配置于输入输出电路单元的元件形成区域上的构造的方案。例如提出将层间绝缘膜设于逻辑电路或驱动电路之上，在其上形成输入焊盘或输出焊盘的半导体集成电路的方案(参照例如日本特开平06-244235号公报)。
然而将电极焊盘形成于元件上时，由于引线接合等情况下的冲击负荷的影响，存在着在焊盘正下方的配线或层间绝缘膜发生损坏的坦心。或者有可能对焊盘正下方形成的扩散元件、如晶体管的工作特性发生影响，造成变化(劣化)。
特别在由金粒粘接形成的引线接合的情况下，通过将半导体芯片加热到230～240℃，一面加上规定的荷重，一面施加超声波，破坏铝焊盘表面的氧化膜，以在铝的本征面与金的界面上形成金-铝合金，故由于超声波能量在焊盘下的层间绝缘膜与金属的界面上产生的应力，在(SiO2等形成的)层间绝缘膜上发生裂纹。
作为探针检查(P检)的一般方法的悬臂方式的P检，也因用钨等制造的探针按压电极焊盘，故在其下方加上较大的集中负荷，层间绝缘膜发生裂纹。而且在电极焊盘上残留探针的针迹(压痕)。压痕因探针括削了焊盘表面的铝，故在P检后的电极焊盘上成为用引线接合不形成与金粒的合金的区域。近年来，由于要求引线接合的接合间距的缩小，焊盘尺寸、金粒直径变得小了起来，因此压迹的面积相对增大起来，产生了规定面积的合金形成、接合不再可能的问题。
图12为在下面具有配线部的电极焊盘上进行金粒粘接时在层间绝缘膜上产生的应力分布图。这里表示用CAE分析(有限要素法)计算用金粒粘接工艺在4层配线构造之上形成金属凸起时的应力分布得到的结果。
在最上层的焊盘金属61(以下称作第1金属61)之下，形成第1层间绝缘膜71、第2层焊盘金属62(以下称作第2金属62)，其下形成第2层间绝缘膜72、第3金属91、第3层间绝缘膜73、最下层金属10。为在第1金属61上形成金属凸起43，当如图中箭头所示那样施加超声波时，应力便集中于下层金属62、91的边缘部分(图中以白色表示)。
当该应力超过层间绝缘膜71、72、73的屈服应力时，就产生脆性破坏，发生裂纹。这时利用CAE分析判明，相应于所加的超声波能量的大小，内部应力也变大。而且判明了形成于粘接的电极焊盘正下方的晶体管的特性(Vt、Gm、热载流子寿命等)劣化的事实。
本发明为解决上述问题而作，其目的在于，在接合或探针检测时减小对电极焊盘表面、下层的配线和层间绝缘膜的损害。
发明内容
为解决上述问题，本发明的半导体装置，其特征在于，作为外部连接用的电极的焊盘部，由形成于最上层的第1焊盘金属层、夹着层间绝缘膜形成于所述第1焊盘金属层之下的第2焊盘金属层、以及贯通所述层间绝缘膜，电气连接第1焊盘金属层与第2焊盘金属层的通路构成，互相偏移地配置所述第1焊盘金属层的端部与第2焊盘金属层的端部，使其沿各层的厚度方向不一致。
又，本发明的半导体装置，其特征在于，作为外部连接用电极的焊盘部，由接合用的第1焊盘区域与探针检测用的第2焊盘区域构成，所述第1焊盘区域由形成于最上层的第1焊盘金属层、夹着层间绝缘膜形成于所述第1焊盘金属层之下的第2焊盘金属层、以及贯通所述层间绝缘膜，电气连接第1焊盘金属层与第2焊盘金属层的通路所构成，互相偏移地配置所述第1焊盘金属层的端部与第2焊盘金属层的端部，使其沿各层的厚度方向不一致，所述第2焊盘区域只用所述第1焊盘金属层构成。
最好是，第1焊盘金属层的端部与第2焊盘金属层端部偏移1.5～2μm。
第2焊盘金属层的端部可以偏移到比第1焊盘金属层的端部更外侧处。又，第2焊盘金属层的端部可偏移到比第1焊盘金属层的端部更内侧处。
最好是，在第2焊盘区域的第1焊盘金属层之下夹着层间绝缘膜使其做成与第2焊盘金属层相同的层地配设多个虚设金属。
电路元件或配线可配设于焊盘部之下的层中。
电路元件或配线可配设于第1焊盘区域与第2焊盘区域中的至少一方之下的层中。
附图说明
图1A、图1B分别为表示本发明的第1实施例的半导体装置的焊盘部及其周边部的构成的平面图和剖面图。
图2为图1的焊盘部的各层的平面图。
图3A、图3B分别为表示图1的焊盘部的检验和金粒粘接时的状态的平面图和剖面图。
图4A、图4B分别为表示本发明的第2实施例的半导体装置的焊盘部及其周边部的构成的平面图和剖面图。
图5为图4的焊盘部的各层的平面图。
图6A、图6B分别为表示本发明的第3实施例的半导体装置的焊盘部及其周边部的构成的平面图和剖面图。
图7为图6的焊盘部的各层的平面图。
图8A、图8B分别为表示图6的焊盘部的检验和金粒粘接时的状态的平面图和剖面图。
图9为示出配置多个图6的焊盘部的样子的平面图。
图10为示出配置多个图6的焊盘部的样子的另一平面图。
图11A、图11B分别为表示已有的半导体装置的焊盘部及其周边部的构成的平面图和剖面图。
图12为产生于层叠构造的电极焊盘的层间绝缘膜上的应力的分布图。
具体实施方式
以下参照附图说明本发明的实施例。
本发明的所谓半导体装置包含晶片状态的半导体集成电路装置及其分立的半导体装置两者，这里就半导体集成电路装置进行说明。
图1示出本发明的第1实施例的半导体装置的主要部分的构成，图1A、图1B分别为该半导体装置的外部连接用电极即焊盘部其周边部的平面图、剖面图。焊盘部形成于输入输出电路的元件区域或配线上，表示是4层配线结构的情况。
图1中，11为因检验需要的晶片检查用的检验焊盘，21为用于引线接合等的组装的接合焊盘，31为形成于去除了检验焊盘11和接合焊盘21的上表面的半导体基板上的第1保护膜(例如P掺杂的P-SiN膜)，32为形成于第1保护膜31上的第2保护膜(例如聚酰亚胺膜)。
接合焊盘21具有由最上层的焊盘金属61(以下称为第1金属61)、形成于下一配线层的第2焊盘金属62(以下称为第2金属62)、贯通第1金属61与第2金属62之间的层间绝缘71，电气连接这些金属61、62的通路63(如钨(W)等金属)构成的层叠通路构造。层叠通路构造具有吸收引线接合等接合工序中产生的冲击能量，缓和作用于焊盘正下方的配线部或扩散元件上的应力，抑制损坏的发生的效果。
在接合焊盘21的第2金属62之下，形成例如电源供给用的电源层、即第3金属91，在再下层形成对输入输出电路提供信号用的配线、即最下层金属10，第1和第2金属61、62与最下层金属10利用引出部金属81的叠层构造进行电气连接。第2金属62与第3金属91之间，以及第3金属91与最下层金属10之间，形成各层间绝缘膜72、73。
接合焊盘21与检验焊盘11成一整体地形成于第1金属61上，从由第1金属61上的第1保护膜31分隔形成的2个接触窗分别露出。但在实际上也可分开使用检验焊盘11与结合焊盘21作为单独区域，不必一定用第1保护膜31来分隔。
检验焊盘11不是像接合焊盘那样的由2层金属61、62形成的层叠通路结构，而仅用第1金属61构成，其下隔着层间绝缘膜71、72，有第3金属91。第3金属91之下与接合焊盘21一样，有层间绝缘膜73与最下层金属10。
第2金属62在纵横方向上都比接合焊盘21来得大，位于接合焊盘21、检验焊盘11各下层的2个第3金属91以比第2金属62的边缘部更靠近中央地相邻接。
图2是检验焊盘11和接合焊盘21的各层的平面图，图2A表示第1金属61的层，图2B、图2C举出2例表示第2金属62的层。
图2A对于第1金属61示出由第1保护膜31分隔开的检验焊盘11的区域与结合焊盘21的区域。引出部金属81与焊盘金属61相同宽度。
图2B中，为从引出部金属81的宽度来理解，将第2金属62的宽度做得比第1金属61的宽度更大。
图2C中，为从引出部金属81的宽度来理解，将第2金属62的宽度做得比第1金属61的宽度更小。
图2B、图2C的构造都使第1金属61的边缘61a与第2金属62的边缘62a在沿各层的厚度方向上不一致，即平面观看时沿垂直方向不一致，且使稍微不重叠地互相偏移地配置。这里，与第1金属61相比，第2金属62的一对端部伸出或凹进，但不限于此，如相互的端部偏移使在层间绝缘膜的上下不一致，则也可以一方伸出而另一方凹进。又，从图1可见，第2金属62的另一对边缘62a也连接于引出部金属81，或偏离第1金属61的边缘61a。51表示检验焊盘11之下的区域的层间绝缘膜，是上述的层间绝缘膜17的一部分。该区域中不形成金属。
图3示出进行检验、接合时的焊盘周边部的状态，图3A、图3B分别为平面图、剖面图。由于探针42的滑移，检验焊盘上产生检验痕迹41。为了能够实施引线接合，接合焊盘21上形成金属凸起43。
这样，即使检验、接合时的荷重作用于焊盘上，也由于如上述所述第1金属61的边缘61a与第2金属62的边缘62a互相错开而能缓和各自的边缘部61a、62a上产生的应力集中，能抑制层间绝缘膜71、72的裂纹等物理损坏的发生。检验焊盘11之下的区域，由于不形成金属而加厚层间绝缘膜71、72的总膜厚，故也能抑制其裂纹的发生。结果可防止第1金属61与第3金属91之间的电气短路/漏电。因此，对位于比第2金属62更下层的第3金属91、最下层金属10、层间绝缘膜72、73而言也有此效果。
设引线接合时的引线的原始粒直径为45μm，引线接合时超声波功率为一定时，在第1金属61与第2金属62的端部做成一致的已有构造中，裂纹发生率为3.2％，与此相对，使图2B、图2C所示的第1金属61与第2金属62的两端部错开的本发明的构造中，裂纹发生率降低，错开1.5～2μm时例纹发生率为0％。即使错开比上述更大，效果也不变，错开过大时焊盘间的距离加大，降低了焊盘配置密度。
该第1实施例中，就具备检验焊盘11与接合焊盘21两者的外部连接用电极作了说明，但若将上述构造应用于至少具备接合焊盘21的外部连接用电极，则可抑制施加荷重时层间绝缘膜裂纹的发生。
图4示出本发明的第2实施例的半导体装置的主要部分的构成，图4A、图4B分别为该半导体装置的外部连接用电极、即焊盘及其周边部的平面图和剖面图。
第2实施例半导体装置与第1实施例半导体装置的不同在于，在检验焊盘11之下形成与接合焊盘21的第2金属62相同的层地，格子状即纵横排列多列几μm的方形的微小的缓冲金属64。由于存在这些微小的缓冲金属64，能缓和因检验时的荷重而产生于检验焊盘11之下的层间绝缘膜71内的应力集中，可防止层间绝缘膜71、72的裂纹发生。从而能更可靠地防止第1金属61与第3金属91之间的电气短路/漏电。
图5是检验焊盘11和接合焊盘21的各层的平面图，图5A表示第1金属61的层，图5B、图5C举出2例表示第2金属62和金属64的层。
与前面说明过的图2相同，图5A中示出在第1金属61上由第1保护膜31分隔开的检验焊盘11的区域与接合焊盘21的区域。引出部金属81与焊盘金属61等宽。
图5B中，为从引出部金属81的宽度来理解，将第2金属62的宽度、金属64的排列宽度做得比第1金属61的宽度更大。
图5C中，为从引出部金属81的宽度来理解，将第2金属62的宽度做得比第1金属61的宽度更小。
图5B、图5C的情况都是没有金属边缘61a、62a的重叠，可缓和接合时的应力。
图6示出本发明第3实施例的半导体装置的主要部分构成，图6A、图6B分别为该半导体装置的外部连接用电极、即焊盘部及其周边部的平面图、剖面图。
该第3实施例的半导体装置与第1实施例的半导体装置的区别在于，在第1实施例中的接合焊盘21的外侧，即芯片外周的划线区域侧，配置外部焊盘。这里称这两个焊盘为内部焊盘68、外部焊盘69。
内部焊盘68、外部焊盘69都与接合焊盘21一样，做成由第1金属61与第2金属62、65以及连接它们之间的通路63、66构成的层叠通路焊盘构造。92是作为例如电源供给用的第2电源层形成的金属。如果是电源层，则与第3层的第3金属91一起形成，从而能实现电源配线内的电位的更加稳定化。
图7为内部焊盘68和外部焊盘69的各层的平面图，图7A示出第1金属61的层，图7B、图7C举出两个例子示出第2金属62、金属65的层。
与前面说明过的图2相同，图7A中示出在第1金属61上由第1保护膜31分隔开的内部焊盘68的区域与外部焊盘69的区域。引出部金属81与焊盘金属61等宽。
图7B中，为从引出部金属81的宽度来理解，将第2金属62的宽度做得比第1金属61的宽度更大。
图7C中，为从引出部金属81的宽度来理解，将第2金属62的宽度做得比第1金属61的宽度更小。
图7B、7C的情况都没有金属边缘61a、62a的重叠，可缓和接合时的应力。
图8示出对图6所示的第3实施例的半导体装置进行检验、金粒粘接时的焊盘周边部的状态，图8A、图8B分别为平面图、剖面图。用探针42对外部焊盘69进行检验，由于探针42的滑移，在外部焊盘69上产生检验痕迹41。金属凸起43形成在内部焊盘68上。
内部焊盘68与外部焊盘69不一定由同一种金属作为单一的膜形成，也可是由另一种金属形成的另一个膜。
图9为在输入输出电路的区域上配置多个焊盘部的样子的平面图。多个焊盘部的各个中，金属凸起43设在内部焊盘68上，检验痕迹41产生在外部焊盘69上。
图10也是在输入输出电路的区域上配置多个焊盘部的样子的平面图。金属凸起43交互地设在内部焊盘68上与外部焊盘69上，剩下的内部焊盘68与外部焊盘69上产生检验痕迹41。
这样，通过分别锯齿形配置检验用的焊盘与接合用的焊盘(或焊盘区域)，可扩大外观上的焊盘间距。又通过在单元内设置多个焊盘，可扩大凸起连接时的间距。
因此，在用金属凸起43将分立的半导体装置作翻转片式安装于载置基板上，作为芯片尺寸封装(Chip Size Package)或球网格陈列(Ball Grid Array)等的表面安装型封装时，能扩大载置基板的电极间距，使基板设计上的规则缓和，也能谋求基板成本的降低等，具有非常大的优点。
作为金属凸起43，可以形成以金粒为基础的2级突起形状的柱形凸起，或由电解电镀法或无电解镀法形成的金、镍、铜等的金属凸起。无论那种情况，如上所述通过交互使用如形成于输入输出电路区域上的多个焊盘(或焊盘区域)，都能扩大实质上的连接间距，因此能提高连接的成品率，提高生产率。
如上所述，采用本发明，则由于能够减小接合时或检验时发生在焊盘金属层边缘处的应力，缓加作用于焊盘金属层之下的层间绝缘膜上的应力，故能减少焊盘金属层之下的层间绝缘膜的损坏。
又，通过与接合用的第1焊盘区域分开设置探认检查用的第2焊盘区域，能在第1焊盘区域中避免因检验引起的层间绝缘膜的损坏与压迹。
在将焊盘部配置于电路元件或配线的区域上时，也能不因接合荷重引起配线部或扩散部发生损坏，容易实施对焊盘部的连接。因此，与避开电路元件或配线的区域配置焊盘部的情况相比，至少能缩小焊盘部的总面积相应部分的芯片尺寸，也能降低芯片的成本。
因此，本发明的半导体装置，作为以外部连接用电极实施探针检查或外部连接用的接合的半导体装置，是特别有用的。

Claims (8)

1.一种半导体装置，其特征在于，作为外部连接用电极的焊盘部，由形成于最上层的第1焊盘金属层、夹着层间绝缘膜形成于所述第1焊盘金属层之下的第2焊盘金属层、以及贯通所述层间绝缘膜，电气连接第1焊盘金属层与第2焊盘金属层的通路构成，互相偏移地配置所述第1焊盘金属层的端部与第2焊盘金属层的端部，使其沿各层的厚度方向不一致。
2.一种半导体装置，其特征在于，作为外部连接用电极的焊盘部，由接合用的第1焊盘区域与探针检测用的第2焊盘区域构成，所述第1焊盘区域由形成于最上层的第1焊盘金属层、夹着层间绝缘膜形成于所述第1焊盘金属层之下的第2焊盘金属层、以及贯通所述层间绝缘膜，电气连接第1焊盘金属层与第2焊盘金属层的通路构成，互相偏移地配置所述第1焊盘金属层的端部与第2焊盘金属层的端部，使其沿各层的厚度方向不一致，所述第2焊盘区域只用所述第1焊盘金属层构成。
3.如权利要求1或2所述的半导体装置，其特征在于，第1焊盘金属层端部与第2焊盘金属层端部偏移1.5～2μm。
4.如权利要求1或2所述的半导体装置，其特征在于，第2焊盘金属层的端部偏移到比第1焊盘金属层的端部更外侧处。
5.如权利要求1或2所述的半导体装置，其特征在于，第2焊盘金属层的端部偏移到比第1焊盘金属层的端部更内侧处。
6.如权利要求2所述的半导体装置，其特征在于，在第2焊盘区域的第1焊盘金属层之下夹着层间绝缘膜配设多个虚设金属，使其与第2焊盘金属层做成相同的层。
7.如权利要求1所述的半导体装置，其特征在于，电路元件或配线配设于焊盘部之下的层中。
8.如权利要求2所述的半导体装置，其特征在于，电路元件或配线配设于第1焊盘区域与第2焊盘区域的至少一方之下的层中。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN102314009A (zh) * 2011-09-09 2012-01-11 深圳市华星光电技术有限公司 液晶显示模组及液晶显示面板
CN102347314A (zh) * 2010-07-23 2012-02-08 株式会社捷太格特 电动马达驱动用半导体元件

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2854731B1 (fr) * 2003-05-05 2005-08-12 St Microelectronics Sa Circuit integre et procede de test associe
US7157734B2 (en) * 2005-05-27 2007-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor bond pad structures and methods of manufacturing thereof
JP4449824B2 (ja) * 2005-06-01 2010-04-14 カシオ計算機株式会社 半導体装置およびその実装構造
JP4717523B2 (ja) * 2005-06-13 2011-07-06 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2007042817A (ja) * 2005-08-02 2007-02-15 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置およびその製造方法
US7947978B2 (en) * 2005-12-05 2011-05-24 Megica Corporation Semiconductor chip with bond area
JP2008098225A (ja) * 2006-10-06 2008-04-24 Nec Electronics Corp 半導体装置
JP4403424B2 (ja) 2006-11-30 2010-01-27 ソニー株式会社 固体撮像装置
JP5111878B2 (ja) * 2007-01-31 2013-01-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5010948B2 (ja) * 2007-03-06 2012-08-29 オリンパス株式会社 半導体装置
US20080303177A1 (en) * 2007-06-06 2008-12-11 United Microelectronics Corp. Bonding pad structure
JP5027605B2 (ja) * 2007-09-25 2012-09-19 パナソニック株式会社 半導体装置
DE102007046556A1 (de) * 2007-09-28 2009-04-02 Infineon Technologies Austria Ag Halbleiterbauelement mit Kupfermetallisierungen
US8089156B2 (en) * 2007-10-24 2012-01-03 Panasonic Corporation Electrode structure for semiconductor chip with crack suppressing dummy metal patterns
US7786584B2 (en) * 2007-11-26 2010-08-31 Infineon Technologies Ag Through substrate via semiconductor components
KR101043748B1 (ko) 2007-12-18 2011-06-27 주식회사 하이닉스반도체 필링 방지를 위한 본딩패드 및 그 형성 방법
JP5342154B2 (ja) * 2008-02-25 2013-11-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
FR2930840B1 (fr) * 2008-04-30 2010-08-13 St Microelectronics Crolles 2 Procede de reprise de contact sur un circuit eclaire par la face arriere
JP4343256B1 (ja) 2008-07-10 2009-10-14 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US20100013109A1 (en) * 2008-07-21 2010-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fine pitch bond pad structure
US8581423B2 (en) 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
JP2011119765A (ja) * 2011-03-07 2011-06-16 Panasonic Corp 半導体装置およびその製造方法
US8532156B2 (en) 2011-09-13 2013-09-10 Seagate Technology Llc Semiconductor laser with test pads
US8923357B2 (en) 2011-09-13 2014-12-30 Seagate Technology Llc Semiconductor laser with cathode metal layer disposed in trench region
US8928142B2 (en) 2013-02-22 2015-01-06 Fairchild Semiconductor Corporation Apparatus related to capacitance reduction of a signal port
US9780051B2 (en) * 2013-12-18 2017-10-03 Nxp Usa, Inc. Methods for forming semiconductor devices with stepped bond pads
JP2016012650A (ja) * 2014-06-27 2016-01-21 ルネサスエレクトロニクス株式会社 半導体装置
KR20160056379A (ko) * 2014-11-10 2016-05-20 삼성전자주식회사 트리플 패드 구조를 이용하는 칩 및 그것의 패키징 방법
JP2017224753A (ja) * 2016-06-16 2017-12-21 セイコーエプソン株式会社 半導体装置及びその製造方法
JP2019169639A (ja) * 2018-03-23 2019-10-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2020098623A1 (en) * 2018-11-12 2020-05-22 Changxin Memory Technologies, Inc. Semiconductor device, pad structure and fabrication method thereof

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59222952A (ja) 1983-06-01 1984-12-14 Toshiba Corp 半導体装置
US5248903A (en) 1992-09-18 1993-09-28 Lsi Logic Corporation Composite bond pads for semiconductor devices
JP2749241B2 (ja) 1993-02-16 1998-05-13 ローム株式会社 半導体集積回路
US6300688B1 (en) * 1994-12-07 2001-10-09 Quicklogic Corporation Bond pad having vias usable with antifuse process technology
JPH08213422A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置およびそのボンディングパッド構造
JPH08293523A (ja) 1995-02-21 1996-11-05 Seiko Epson Corp 半導体装置およびその製造方法
US5723822A (en) * 1995-03-24 1998-03-03 Integrated Device Technology, Inc. Structure for fabricating a bonding pad having improved adhesion to an underlying structure
JP3482779B2 (ja) * 1996-08-20 2004-01-06 セイコーエプソン株式会社 半導体装置およびその製造方法
US5891805A (en) * 1996-12-13 1999-04-06 Intel Corporation Method of forming contacts
JP3660799B2 (ja) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6552438B2 (en) * 1998-06-24 2003-04-22 Samsung Electronics Co. Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same
JP2000198566A (ja) 1999-01-06 2000-07-18 Canon Inc シ―ト吸着搬送装置及び記録装置
TW442873B (en) * 1999-01-14 2001-06-23 United Microelectronics Corp Three-dimension stack-type chip structure and its manufacturing method
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance
US6306749B1 (en) * 1999-06-08 2001-10-23 Winbond Electronics Corp Bond pad with pad edge strengthening structure
US6291331B1 (en) * 1999-10-04 2001-09-18 Taiwan Semiconductor Manufacturing Company Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue
JP2001267323A (ja) 2000-03-21 2001-09-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2001284394A (ja) 2000-03-31 2001-10-12 Matsushita Electric Ind Co Ltd 半導体素子
JP2002016065A (ja) * 2000-06-29 2002-01-18 Toshiba Corp 半導体装置
JP2002016069A (ja) 2000-06-29 2002-01-18 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP3843708B2 (ja) * 2000-07-14 2006-11-08 日本電気株式会社 半導体装置およびその製造方法ならびに薄膜コンデンサ
US6586839B2 (en) 2000-08-31 2003-07-01 Texas Instruments Incorporated Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers
KR100368115B1 (ko) * 2001-01-26 2003-01-15 삼성전자 주식회사 반도체 소자의 본딩 패드 구조 및 그 제조방법
JP3561747B2 (ja) * 2001-03-30 2004-09-02 ユーディナデバイス株式会社 高周波半導体装置の多層配線構造
US6455943B1 (en) * 2001-04-24 2002-09-24 United Microelectronics Corp. Bonding pad structure of semiconductor device having improved bondability
FR2824954A1 (fr) * 2001-05-18 2002-11-22 St Microelectronics Sa Plot de connexion d'un circuit integre
JP3538170B2 (ja) * 2001-09-11 2004-06-14 松下電器産業株式会社 半導体装置及びその製造方法
JP2003142485A (ja) * 2001-11-01 2003-05-16 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2003209134A (ja) * 2002-01-11 2003-07-25 Hitachi Ltd 半導体装置及びその製造方法
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
US6844631B2 (en) * 2002-03-13 2005-01-18 Freescale Semiconductor, Inc. Semiconductor device having a bond pad and method therefor
US20030218259A1 (en) * 2002-05-21 2003-11-27 Chesire Daniel Patrick Bond pad support structure for a semiconductor device
JP3910493B2 (ja) * 2002-06-14 2007-04-25 新光電気工業株式会社 半導体装置及びその製造方法
US7023090B2 (en) * 2003-01-29 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad and via structure design
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells
US7049701B2 (en) * 2003-10-15 2006-05-23 Kabushiki Kaisha Toshiba Semiconductor device using insulating film of low dielectric constant as interlayer insulating film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347314A (zh) * 2010-07-23 2012-02-08 株式会社捷太格特 电动马达驱动用半导体元件
CN102347314B (zh) * 2010-07-23 2015-11-25 株式会社捷太格特 电动马达驱动用半导体元件
CN102136458A (zh) * 2011-02-24 2011-07-27 中颖电子股份有限公司 针对boac构架的改进结构
CN102314009A (zh) * 2011-09-09 2012-01-11 深圳市华星光电技术有限公司 液晶显示模组及液晶显示面板

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